Technical information

7-20
AIC-6915 Ethernet LAN Controller Programmer’s Manual
BacControl Register
Type: R/W
Internal Registers Subgroup: PCI Functional Registers
Byte Address: 44h - 47h
This register provides the software driver a way to configure and control BAC DMA
operation.
Table 7-28. BacControl Register
Bit(s) rw
Reset
Value Description/Function
31:22 r 0
Reserved:
Always read as 0.
7:6 r/w 0
DescSwapMode[1:0]:
Must always be 0.
5:4 r/w 0
DataSwapMode: Controls the way transmit/receive DMA data is
read and written to and from host memory. In the default state (‘0)
the swapper is disabled, and the data on the PCI bus is assumed to
be in little endian format. When the bit is set the swapper is active
and the data on the PCI bus is assumed to be in big endian format.
Note: This bit has no affect on the way descriptors are read from
and written to host memory.
3r/w0
SingleDmaMode: Is used for debugging only. In this mode the
BAC resets its BacDmaEn bit after completion of a DMA transfer.
2r/w0
PreferTxDmaReq: Controls the BAC’s arbitration algorithm. If
the bit is set, TxDmaReq has priority over RxDmaReq. If the bit is
cleared and PreferRxDmaReq is also cleared, they have equal
(round-robin) priority.
Note: The AIC-6915 implements an internal dynamically changing
control signal that can force PreferTxDmaReq to ‘1’. This control
signal is active when the transmit data falls bellow a programmable
threshold and there is a danger of FIFO underrun.
32 bit PCI Bus
LSB (Little Endian)
Byte Address[2:0]=0
W0
Internal Fifo
First Byte
Received/transmitte
d
System
Memory
Bit 0
Chip
W1
63
0
W0W1
Assembly Register
DataSwapMode=0
3 2 1 0
7 6 5 4
3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
63
0
W0W1