Technical information

7-23
Register Descriptions
PMCSR (Power Management Control/Status) Register
Type: R/W
Internal Registers Subgroup: PCI Functional Registers
Byte Address: 54h - 57h
18:16 r 1h
PMVersion
: This field indicates that there are 4 bytes of General
Purpose Power Management registers implemented as described in
revision 1.0 of the ‘PCI Bus Power Management Interface
Specification’.
15:8 r 00h
NextItemPtr:
This field provides an offset into the function’s PCI
configuration space pointing to the location of next item in the
function’s capability list. The AIC-6915 does not implement more
items in the list.
7:0 r 01h
PowerManagementId
: This ID indicates the start of the Power
Management Register Block
Table 7-32. Power Management Control Status Register
Bit(s) rw
Reset
Value Description/Function
31:29 r 0
PMData:
This function is not implemented. The AIC-6915 does not
provide information about the power it consumes.
23:16 r 0
Reserved:
Always read as 0.
15 r/w 0
PmeStatus:
This bit is set when the function would normally assert
the
PME_
signal independent of the state of the
P
ME
E
N
bit. Setting
this bit clears it and causes the function to stop asserting a
PME_
.
Clearing the bit has no effect.
14:13 r 0
DataScale:
This function is not implemented. The AIC-6915 does
not provide information about the power it consumes.
12:9 r 0
DataSelect:
This function is not implemented. The AIC-6915 does
not provide information about the power it consumes.
8r/w 0
PmeEn:
This bit enables the function to assert
PME_
. If this bit is
cleared assertion of
PME_
is disabled.
7:2 r 0
Reserved:
Always read as 0.
1:0 r/w
PowerState
: This 2-bit field determines the power state of the
AIC-6915
‘
00
’ - D0
‘
01
’ - D1
‘
10
’ - D2
‘
11
’ - D3
Reset Value:
In CardBus mode, (when the EPROM A0 pin is
sampled low at reset), the PowerState starts at D3. Otherwise, it
starts at D0.
Table 7-31. Power Management Register (Continued)
Bit(s) rw
Reset
Value Description/Function