Technical information

7-25
Register Descriptions
EEPROM Memory Definition
Table 7-35. EEPROM Memory Definition
Byte
Address Description/Function Value
0 Vendor ID [7:0] 04
1 Vendor ID [15:8] 90
2 Device ID [7:0] 15
3 Device ID [15:8] 69
4 SubClass [7:0] 00
5 Base Class [7:0] 02
6 SubSystem Vendor ID [7:0] 04
7 SubSystem Vendor ID [15:8] 90
8 SubSystem Device ID [7:0] 08 = 62011/TX Rev. 0
09 = 62011/TX Rev. 1
10 = 62022
28 = 62044
20 = 62020/FX
28 = 69011/TX
9 SubSystem Device ID [15:8] 00
10 Interrupt Pin [7:0] 01
11 Card Bus [7:0] 00
12 Card Bus [15:8] 00
13 Card Bus [23:16] 00
14 Card Bus [31:24] 00
15 MAC address [7:0] --> MAC Addr Byte 5
(LSB)
16 MAC address [7:0] --> MAC Addr Byte 4
17 MAC address [7:0] --> MAC Addr Byte 3
18 MAC address [7:0] --> MAC Addr Byte 2
19 MAC address [7:0] --> MAC Addr Byte 1
20 MAC address [7:0] --> MAC Addr Byte 0
(MSB)
21 Minimum Grant [7:0] 09
22 Maximum Latency [7:0] 05
23-124 Reserved FF
125 Adaptec Standard Format 00
126 Checksum [7:0] LSB
127 Checksum [15:8] MSB