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HYQVE1B16_DDR2-800G(CL=5)_2GB(128Mx8_Pb free) Rev.0 2009/02/12 Page 2 of 7

General Description

The ADATA’s HYQVE1B16 is a 256Mx64 bits 2GB DDR2-800(CL5) SDRAM over clocking memory module,

The SPD is programmed to JEDEC standard latency 800Mbps timing of 5-5-5-18 at 1.8V. The module is composed

of sixteen 128Mx8 bits CMOS DDR2 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TSSOP (TSOP)

package on a 240pin glass–epoxy printed circuit board.

The HYQVE1B16 is a Dual In-line Memory Module and intended for mounting onto 240-pins edge connector

sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are

possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow

the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Features

• Power supply(Normal): VDD & VDDQ = 1.8V ± 0.1V

• 1.8V (SSTL_18 compatible) I/O

• Timing Reference

- DDR2 800 CL5-5-5-18 at 1.8V

- DDR2 800 CL5-5-5-12 at 2.0V

• Burst Length: 4, 8

• Programmable Additive Latency: 0, 1, 2, 3, 4

• Bi-directional, differential data strobe (DQS and /DQS)

• Differential clock input (CK, /CK) operation

• DLL aligns DQ and DQS transition with CK transition

• Double-data-rate architecture.

• Auto & Self refresh

• Average Refresh period 7.8ȝs

• Off-Chip Driver (OCD) Impedance Adjustment

• On Die Termination (ODT)

• Lead-free products are RoHS compliant

• EEPROM VDDSPD=3.3V (Typical)

• PCB Height 30.00mm (1.181”), Double sided component

• Clock Cycle Time (tCK):

- DDR2-800 tCK=2.5ns

• Refresh to Active/Refresh Command Time (tRFC): 127.5ns

VE1B16

DDR2-800G(CL5) 240-Pin O.C. U-DIMM

2GB (256M x 64-bits)

Summary of content (6 pages)

PAGE 1
HYQVE1B16 DDR2-800G(CL5) 240-Pin O.C. U-DIMM 2GB (256M x 64-bits) General DescriptionΚ The ADATA’s HYQVE1B16 is a 256Mx64 bits 2GB DDR2-800(CL5) SDRAM over clocking memory module, The SPD is programmed to JEDEC standard latency 800Mbps timing of 5-5-5-18 at 1.8V. The module is composed of sixteen 128Mx8 bits CMOS DDR2 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TSSOP (TSOP) package on a 240pin glass–epoxy printed circuit board.
PAGE 2
Pin AssignmentΚ Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 VREF 41 VSS 81 DQ33 121 VSS 161 NC , CB4 201 VSS 2 VSS 42 NC , CB0 82 VSS 122 DQ4 162 NC , CB5 202 DM4 3 DQ0 43 NC , CB1 83 /DQS4 123 DQ5 163 VSS 203 NC 4 DQ1 44 VSS 84 DQS4 124 VSS 164 NC , DM8 204 VSS 5 VSS 45 NC , /DQS8 85 VSS 125 DM0 165 NC 205 DQ38 6 /DQS0 46 NC , DQS8 86 DQ34 126 NC 166 VSS 206 DQ39 7 DQS0 47 VSS 87 DQ35 127 VSS 167 NC
PAGE 3
Pin DescriptionΚ PIN NAME FUNCTION CK0~CK2, System Clock Active on the positive and negative edge to sample all inputs. /CK0~/CK2 Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at CKE0,CKE1 Clock Enable least on cycle prior new command. Disable input buffers for power down in standby Disables or Enables device operation by masking or enabling all input except CK, CKE and /S0, /S1 Chip Select L(U)DQM Row / Column address are multiplexed on the same pins.
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Block DiagramΚ HYQVE1B16_DDR2-800G(CL=5)_2GB(128Mx8_Pb free) Rev.
PAGE 5
Absolute Maximum RatingsΚ Parameter Symbol Value Unit Voltage on VDD supply relative to Vss VDD -1.0 ~ +2.3 V Voltage on VDDQ supply relative to Vss VDDQ -0.5 ~ +2.3 V Voltage on VDDL supply relative to Vss VDDQ -0.5 ~ +2.3 V VIN, Vout -0.5 ~ +2.3 V TSTG -55 ~ +100 к Voltage on any pin relative to Vss Storage temperature Note: DDR2 SDRAM component specification.
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Package DimensionsΚ HYQVE1B16_DDR2-800G(CL=5)_2GB(128Mx8_Pb free) Rev.