Specifications

SDI
SDO
R/W
1 0 A3 A2 A1 A0 X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
21 43 65 87 109 1211 1413 1615 1817 2019 2221 2423 25
SCLK
SCSb
ADC12D1000RF, ADC12D1600RF
www.ti.com SNAS519G –JULY 2011–REVISED APRIL 2013
Figure 6-2. Serial Data Protocol - Write Operation
6.3 FEATURES
The ADC12D1600/1000RF offers many features to make the device convenient to use in a wide variety of
applications. Table 6-4 is a summary of the features available, as well as details for the control mode
chosen. "N/A" means "Not Applicable."
Table 6-4. Features and Modes
Control Pin
Feature Non-ECM ECM Default ECM State
Active in ECM
Input Control and Adjust
AC/DC-coupled Mode Selected via V
CMO
Yes Not available N/A
Selection (Pin C2)
Selected via FSR Selected via the Config Reg
Input Full-scale Range Adjust No Mid FSR value
(Pin Y3) (Addr: 3h and Bh)
Selected via the Config Reg
Input Offset Adjust Setting Not available N/A Offset = 0 mV
(Addr: 2h and Ah)
DES / Non-DES Mode Selected via DES Selected via the DES Bit
No Non-DES Mode
Selection (Pin V5) (Addr: 0h; Bit: 7)
Selected via the DEQ, DIQ Bits
DES Mode Input Selection Not available N/A N/A
(Addr: 0h; Bits: 6:5)
Selected via the DCK Bit
DESCLKIQ Mode Not available N/A N/A
(Addr: Eh; Bit: 6)
Selected via the DES Timing
DES Timing Adjust Not available N/A Adjust Reg Mid skew offset
(Addr: 7h)
Selected via the Config Reg
Sampling Clock Phase Adjust Not available N/A t
AD
adjust disabled
(Addr: Ch and Dh)
Output Control and Adjust
Selected via DDRPh Selected via the DPS Bit
DDR Clock Phase Selection No 0° Mode
(Pin W4) (Addr: 0h; Bit: 14)
Selected via the SDR Bit
DDR / SDR DCLK Selection Not available N/A DDR Mode
(Addr: 0h; Bit: 2)
SDR Rising / Falling DCLK Selected via the DPS Bit
Not available N/A N/A
Selection (Addr: 0h; Bit: 14)
LVDS Differential Voltage Selected via the OVS Bit
Higher amplitude only N/A Higher amplitude
Amplitude Selection (Addr: 0h; Bit: 13)
LVDS Common-Mode Voltage Selected via V
BG
Yes Not available N/A
Amplitude Selection (Pin B1)
Selected via the 2SC Bit
Output Formatting Selection Offset Binary only N/A Offset Binary
(Addr: 0h; Bit: 4)
Copyright © 2011–2013, Texas Instruments Incorporated Functional Description 41
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