Specifications

ADC12D1000RF, ADC12D1600RF
www.ti.com SNAS519G –JULY 2011–REVISED APRIL 2013
6.3.1.4 DES/Non-DES Mode
The ADC12D1600/1000RF can operate in Dual-Edge Sampling (DES) or Non-DES Mode. The DES Mode
allows for a single analog input to be sampled by both I- and Q-channels. One channel samples the input
on the rising edge of the sampling clock and the other samples the same input signal on the falling edge
of the sampling clock. A single input is thus sampled twice per clock cycle, resulting in an overall sample
rate of twice the sampling clock frequency, e.g. 3.2/2.0 GSPS with a 1600/1000 MHz sampling clock.
Since DES Mode uses both I- and Q-channels to process the input signal, both channels must be
powered up for the DES Mode to function properly.
In Non-ECM, only the I-input may be used for the DES Mode input. See Dual Edge Sampling Pin (DES)
for information on how to select the DES Mode. In ECM, either the I- or Q-input may be selected by first
using the DES bit (Addr: 0h, Bit 7) to select the DES Mode. The DEQ Bit (Addr: 0h, Bit: 6) is used to
select the Q-input, but the I-input is used by default. Also, both I- and Q-inputs may be driven externally,
i.e. DESIQ Mode, by using the DIQ bit (Addr: 0h, Bit 5). See THE ANALOG INPUTS for more information
about how to drive the ADC in DES Mode.
In DESCLKIQ Mode, the I- and Q-channels sample their inputs 180° out-of-phase with respect to one
another, similar to the other DES Modes. DESCLKIQ Mode is similar to the DESIQ Mode, except that the
I- and Q-channels remain electrically separate internal to the ADC12D1600/1000RF. For this reason, both
I- and Q-inputs must be externally driven for the DESCLKIQ Mode. The DCK Bit (Addr: Eh, Bit: 6) is used
to select the 180° sampling clock mode.
The DESCLKIQ Mode results in the best bandwidth for the interleaved modes. In general, the bandwidth
decreases from Non-DES Mode to DES Mode (specifically, DESI or DESQ) because both channels are
sampling off the same input signal and non-ideal effects introduced by interleaving the two channels lower
the bandwidth. Driving both I- and Q-channels externally (DESIQ Mode and DESCLKIQ Mode) results in
better bandwidth because each channel is being driven, which reduces routing losses. The DESCLKIQ
Mode has better bandwidth than the DESIQ Mode because the routing internal to the ADC12D1600/1000
is simpler, which results in less insertion loss.
In the DES Mode, the outputs must be carefully interleaved in order to reconstruct the sampled signal. If
the device is programmed into the 1:4 Demux DES Mode, the data is effectively demultiplexed by 1:4. If
the sampling clock is 1600/1000 MHz, the effective sampling rate is doubled to 3.2/2.0 GSPS and each of
the 4 output buses has an output rate of 800/500 MSPS. All data is available in parallel. To properly
reconstruct the sampled waveform, the four bytes of parallel data that are output with each DCLK must be
correctly interleaved. The sampling order is as follows, from the earliest to the latest: DQd, DId, DQ, DI.
See Figure 4-5. If the device is programmed into the Non-Demux DES Mode, two bytes of parallel data
are output with each edge of the DCLK in the following sampling order, from the earliest to the latest: DQ,
DI. See Figure 4-6.
6.3.1.5 DES Timing Adjust
The performance of the ADC12D1600/1000RF in DES Mode depends on how well the two channels are
interleaved, i.e. that the clock samples either channel with precisely a 50% duty-cycle, each channel has
the same offset (nominally code 2047/2048), and each channel has the same full-scale range. The
ADC12D1600/1000RF includes an automatic clock phase background adjustment in DES Mode to
automatically and continuously adjust the clock phase of the I- and Q-channels. In addition to this, the
residual fixed timing skew offset may be further manually adjusted, and further reduce timing spurs for
specific applications. See the DES Timing Adjust (Addr: 7h). As the DES Timing Adjust is programmed
from 0d to 127d, the magnitude of the Fs/2-Fin timing interleaving spur will decrease to a local minimum
and then increase again. The default, nominal setting of 64d may or may not coincide with this local
minimum. The user may manually skew the global timing to achieve the lowest possible timing interleaving
spur.
Copyright © 2011–2013, Texas Instruments Incorporated Functional Description 43
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