Specifications

ADC12D1000RF, ADC12D1600RF
SNAS519G –JULY 2011–REVISED APRIL 2013 www.ti.com
6.3.2.6 Test Pattern Mode
The ADC12D1600/1000RF can provide a test pattern at the four output buses independently of the input
signal to aid in system debug. In Test Pattern Mode, the ADC is disengaged and a test pattern generator
is connected to the outputs, including ORI and ORQ. The test pattern output is the same in DES Mode or
Non-DES Mode. Each port is given a unique 12-bit word, alternating between 1's and 0's. When the part is
programmed into the Demux Mode, the test pattern’s order is described in Table 6-6. If the I- or Q-channel
is powered down, the test pattern will not be output for that channel.
Table 6-6. Test Pattern by Output Port in
Demux Mode
Time Qd Id Q I ORQ ORI Comments
T0 000h 004h 008h 010h 0b 0b
T1 FFFh FFBh FF7h FEFh 1b 1b
Pattern
T2 000h 004h 008h 010h 0b 0b Sequence
n
T3 FFFh FFBh FF7h FEFh 1b 1b
T4 000h 004h 008h 010h 0b 0b
T5 000h 004h 008h 010h 0b 0b
T6 FFFh FFBh FF7h FEFh 1b 1b
Pattern
T7 000h 004h 008h 010h 0b 0b Sequence
n+1
T8 FFFh FFBh FF7h FEFh 1b 1b
T9 000h 004h 008h 010h 0b 0b
T10 000h 004h 008h 010h 0b 0b
Pattern
T11 FFFh FFBh FF7h FEFh 1b 1b
Sequence
T12 000h 004h 008h 010h 0b 0b
n+2
T13 ... ... ... ... ... ...
When the part is programmed into the Non-Demux Mode, the test pattern’s order is described in Table 6-
7.
Table 6-7. Test Pattern by Output Port in
Non-Demux Mode
Time Q I ORQ ORI Comments
T0 000h 004h 0b 0b
T1 000h 004h 0b 0b
T2 FFFh FFBh 1b 1b
T3 FFFh FFBh 1b 1b
T4 000h 004h 0b 0b
Pattern Sequence
n
T5 FFFh FFBh 1b 1b
T6 000h 004h 0b 0b
T7 FFFh FFBh 1b 1b
T8 FFFh FFBh 1b 1b
T9 FFFh FFBh 1b 1b
T10 000h 004h 0b 0b
T11 000h 004h 0b 0b
Pattern Sequence
T12 FFFh FFBh 1b 1b
n+1
T13 FFFh FFBh 1b 1b
T14 ... ... ... ...
46 Functional Description Copyright © 2011–2013, Texas Instruments Incorporated
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