Specifications

ADC12D1000RF, ADC12D1600RF
www.ti.com SNAS519G –JULY 2011–REVISED APRIL 2013
6.3.2.7 Time Stamp
The Time Stamp feature enables the user to capture the timing of an external trigger event, relative to the
sampled signal. When enabled via the TSE Bit (Addr: 0h; Bit: 3), the LSB of the digital outputs (DQd, DQ,
DId, DI) captures the trigger information. In effect, the 12-bit converter becomes an 11-bit converter and
the LSB acts as a 1-bit converter with the same latency as the 11-bit converter. The trigger should be
applied to the DCLK_RST input. It may be asynchronous to the ADC sampling clock.
6.3.3 Calibration Feature
The ADC12D1600/1000RF calibration must be run to achieve specified performance. The calibration
procedure is exactly the same regardless of how it was initiated or when it is run. Calibration trims the
analog input differential termination resistors, the CLK input resistor, and sets internal bias currents which
affect the linearity of the converter. This minimizes full-scale error, offset error, DNL and INL, which results
in the maximum dynamic performance, as measured by: SNR, THD, SINAD (SNDR) and ENOB.
6.3.3.1 Calibration Control Pins and Bits
Table 6-8 is a summary of the pins and bits used for calibration. See Ball Descriptions and Equivalent
Circuits for complete pin information and Figure 4-8 for the timing diagram.
Table 6-8. Calibration Pins
Pin (Bit) Name Function
D6 CAL
Initiate calibration
(Addr: 0h; Bit 15) (Calibration)
CalDly
V4 Select power-on calibration delay
(Calibration Delay)
(Addr: 4h) Calibration Adjust Adjust calibration sequence
CalRun
B5 Indicates while calibration is running
(Calibration Running)
Rtrim+/- External resistor used to calibrate analog and
C1/D2
(Input termination trim resistor) CLK inputs
Rext+/- External resistor used to calibrate internal
C3/D3
(External Reference resistor) linearity
6.3.3.2 How to Execute a Calibration
Calibration may be initiated by holding the CAL pin low for at least t
CAL_L
clock cycles, and then holding it
high for at least another t
CAL_H
clock cycles, as defined in Converter Electrical Characteristics Calibration.
The minimum t
CAL_L
and t
CAL_H
input clock cycle sequences are required to ensure that random noise does
not cause a calibration to begin when it is not desired. The time taken by the calibration procedure is
specified as t
CAL
. The CAL Pin is active in both ECM and Non-ECM. However, in ECM, the CAL Pin is
logically OR'd with the CAL Bit, so both the pin and bit are required to be set low before executing another
calibration via either pin or bit.
6.3.3.3 Power-on Calibration
For standard operation, power-on calibration begins after a time delay following the application of power,
as determined by the setting of the CalDly Pin and measured by t
CalDly
(see Converter Electrical
Characteristics Calibration). This delay allows the power supply to come up and stabilize before the
power-on calibration takes place. The best setting (short or long) of the CalDly Pin depends upon the
settling time of the power supply.
It is strongly recommended to set CalDly Pin (to either logic-high or logic-low) before powering the device
on since this pin affects the power-on calibration timing. This may be accomplished by setting CalDly via
an external 1kΩ resistor connected to GND or V
A
. If the CalDly Pin is toggled while the device is powered-
on, it can execute a calibration even though the CAL Pin/Bit remains logic-low.
Copyright © 2011–2013, Texas Instruments Incorporated Functional Description 47
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