Specifications

ADC12D1000RF, ADC12D1600RF
www.ti.com SNAS519G –JULY 2011–REVISED APRIL 2013
5. Continue with normal operation.
To write calibration values to the SPI, do the following:
1. Set ADC to operating conditions at which Calibration Values were previously read.
2. Set SSC (Addr: 4h, Bit 7) to 1.
3. Write exactly 239 times the Calibration Values register (Addr: 5h). The registers should be written with
stored register values R1, R2... R239.
4. Make two additional dummy writes of 0000h.
5. Set SSC (Addr: 4h, Bit 7) to 0.
6. Continue with normal operation.
6.3.3.7 Calibration and Power-Down
If PDI and PDQ are simultaneously asserted during a calibration cycle, the ADC12D1600/1000RF will
immediately power down. The calibration cycle will continue when either or both channels are powered
back up, but the calibration will be compromised due to the incomplete settling of bias currents directly
after power up. Therefore, a new calibration should be executed upon powering the ADC12D1600/1000RF
back up. In general, the ADC12D1600/1000RF should be recalibrated when either or both channels are
powered back up, or after one channel is powered down. For best results, this should be done after the
device has stabilized to its operating temperature.
6.3.3.8 Calibration and the Digital Outputs
During calibration, the digital outputs (including DI, DId, DQ, DQd and OR) are set logic-low, to reduce
noise. The DCLK runs continuously during calibration. After the calibration is completed and the CalRun
signal is logic-low, it takes an additional 60 Sampling Clock cycles before the output of the
ADC12D1600/1000RF is valid converted data from the analog inputs. This is the time it takes for the
pipeline to flush, as well as for other internal processes.
6.3.4 Power Down
On the ADC12D1600/1000RF, the I- and Q-channels may be powered down individually. This may be
accomplished via the control pins, PDI and PDQ, or via ECM. In ECM, the PDI and PDQ pins are logically
OR'd with the Control Register setting. See Power Down I-channel Pin (PDI) and Power Down Q-channel
Pin (PDQ) for more information.
6.4 Applications Information
6.4.1 THE ANALOG INPUTS
The ADC12D1600/1000RF will continuously convert any signal which is present at the analog inputs, as
long as a CLK signal is also provided to the device. This section covers important aspects related to the
analog inputs including: acquiring the input, driving the ADC in DES Mode, the reference voltage and
FSR, out-of-range indication, AC/DC-coupled signals, and single-ended input signals.
6.4.1.1 Acquiring the Input
The Aperture Delay, t
AD
, is the amount of delay, measured from the sampling edge of the clock input, after
which signal present at the input pin is sampled inside the device. Data is acquired at the rising edge of
CLK+ in Non-DES Mode and both the falling and rising edges of CLK+ in DES Mode. In Non-DES Mode,
the I- and Q-channels always sample data on the rising edge of CLK+. In DES Mode, i.e. DESI, DESQ,
DESIQ, and DESCLKIQ, the I-channel samples data on the rising edge of CLK+ and the Q-channel
Copyright © 2011–2013, Texas Instruments Incorporated Functional Description 49
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