TMS320x2833x Analog-to-Digital Converter (ADC) Module Reference Guide Literature Number: SPRU812A September 2007 – Revised October 2007
SPRU812A – September 2007 – Revised October 2007 Submit Documentation Feedback
Contents Preface ............................................................................................................................... 7 1 Analog-to-Digital Converter (ADC) Features ............................................................................................................ 10 1.2 Autoconversion Sequencer Principle of Operation 1.3 ........................................................... 1.2.1 Sequential Sampling Mode .......................................................
List of Figures 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 4 Block Diagram of the ADC Module ...................................................................................... Sequential Sampling Mode (SMODE = 0) .............................................................................. Simultaneous Sampling Mode (SMODE=1) ............................................................................
List of Tables 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 ADC Registers .............................................................................................................. Comparison of Single and Cascaded Operating Modes ............................................................. Values for ADCCHSELSEQn Registers (MAX_CONV1 Set to 6) ................................................... Values for ADCCHSELSEQn (MAX_CONV1 set to 2) .............................
List of Tables SPRU812A – September 2007 – Revised October 2007 Submit Documentation Feedback
Preface SPRU812A – September 2007 – Revised October 2007 Read This First Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h or with a leading 0x. For example, the following number is 40 hexadecimal (decimal 64): 40h or 0x40. • Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent the fields of the register.
www.ti.com Related Documents From Texas Instruments SPRU791— TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide describes the main areas of the enhanced pulse width modulator that include digital motor control, switch mode power supply control, UPS (uninterruptible power supplies), and other forms of power conversion.
Chapter 1 SPRU812A – September 2007 – Revised October 2007 Analog-to-Digital Converter (ADC) The TMS320x2833x ADC module is a 12-bit pipelined analog-to-digital converter (ADC). The analog circuits of this converter, referred to as the core in this document, include the front-end analog multiplexers (MUXs), sample-and-hold (S/H) circuits, the conversion core, voltage regulators, and other analog supporting circuits.
www.ti.com Features 1.1 Features The ADC module has 16 channels, configurable as two independent 8-channel modules to service the ePWM modules. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 1-1 shows the block diagram of the ADC module.
www.ti.com Features Figure 1-1. Block Diagram of the ADC Module ADCENCLK SYSCLKOUT High-speed prescaler System control block C28x HSPCLK HALT Analog MUX Result Registers Result Reg 0 ADCINA0 70A8h Result Reg 1 S/H-A ADCINA7 12-Bit ADC module Result Reg 7 70AFh Result Reg 8 70B0h Result Reg 15 70B7h ADCINB0 S/H-B ADCINB7 ADC Control Registers S/W ePWMx SOCA SOC Sequencer 1 S/W Sequencer 2 SOC ePWMx SOCB GPIO/XINT2_ ADCSOC Table 1-1.
www.ti.com Autoconversion Sequencer Principle of Operation Table 1-1.
www.ti.com Autoconversion Sequencer Principle of Operation sampling mode, the MSB of the CONVxx register is discarded. Each sample and hold buffer samples the associated pin given by the offset provided in the three LSBs of the CONVxx register. For instance, if the CONVxx register contains the value 0110b, ADCINA6 is sampled by S/H-A and ADCINB6 is sampled by S/H-B. If the value is 1001b, ADCINA1 is sampled by S/H-A and ADCINB1 is sampled by S/H-B.
www.ti.com Autoconversion Sequencer Principle of Operation 1.2.2 Simultaneous Sampling Mode Figure 1-3 describes the timing of simultaneous sampling mode. In this example, the ACQ_PS bits are set to 0001b. Figure 1-3.
www.ti.com Autoconversion Sequencer Principle of Operation Figure 1-4.
www.ti.com Autoconversion Sequencer Principle of Operation Figure 1-5.
www.ti.com Autoconversion Sequencer Principle of Operation Table 1-2. Comparison of Single and Cascaded Operating Modes Feature Start-of-conversion (SOC) triggers Single 8-state sequencer #1 (SEQ1) Single 8-state sequencer #2 (SEQ2) Cascaded 16-state sequencer (SEQ) ePWMx SOCA, software, external pin ePWMx SOCB, software ePWMx SOCA, ePWMx SOCB, software, external pin 8 8 16 Yes Yes Yes Maximum number of autoconversions (i.e.
www.ti.com Autoconversion Sequencer Principle of Operation Example 1-1. Simultaneous Sampling Dual Sequencer Mode Example Example initialization: AdcRegs.ADCTRL3.bit.SMODE_SEL = AdcRegs.ADCMAXCONV.all = 0x1; 0x0033; // Setup simultaneous sampling mode // 4 double conv's each sequencer (8 total) AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup conv from ADCINA0 & ADCINB0 AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup conv from ADCINA1 & ADCINB1 AdcRegs.ADCCHSELSEQ1.bit.
www.ti.com Uninterrupted Autosequenced Mode Example 1-2. Simultaneous Sampling Cascaded Sequencer Mode Example AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x1; // Setup simultaneous sampling mode 0x1; // Setup cascaded sequencer mode AdcRegs.ADCTRL1.bit.SEQ_CASC = AdcRegs.ADCMAXCONV.all = 0x0007; // 8 double conv's (16 total) AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup conv from ADCINA0 & ADCINB0 AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup conv from ADCINA1 & ADCINB1 AdcRegs.
www.ti.com Uninterrupted Autosequenced Mode Example 1-3. Conversion in Dual-Sequencer Mode Using SEQ1 Suppose seven conversions are desired from SEQ1 (i.e., inputs ADCINA2 and ADCINA3 twice, then ADCINA6, ADCINA7, and ADCINB4 must be converted as part of the autosequenced session), then MAX_CONV1 should be set to 6 and the ADCCHSELSEQn registers should be set to the values shown in Table 1-3. Conversion begins once the start-of-conversion (SOC) trigger is received by the sequencer.
www.ti.com Uninterrupted Autosequenced Mode Figure 1-6. Flow Chart for Uninterrupted Autosequenced Mode Initialize the ADC registers SOC trigger arrives MAX_CONVn value gets loaded into SEQ_CNTR bits in ADCASEQSR register Conversion begins. SEQ_CNTR bits are decremented by one for every conversion Current conversion complete.
www.ti.com Uninterrupted Autosequenced Mode Example 1-4. Sequencer Start/Stop Operation Requirement: To start three autoconversions (e.g., I1,I2,I3) off trigger 1 (underflow) and three autoconversions (e.g., V1,V2,V3) off trigger 2 (period). Triggers 1 and 2 are separated in time by 25 µs and are provided by an ePWM. See Figure 1-7. Only SEQ1 is used in this case. Note: Triggers 1 and 2 may be an SOC signal from ePWM, external pin, or software.
www.ti.com Uninterrupted Autosequenced Mode Table 1-4. Values for ADCCHSELSEQn (MAX_CONV1 set to 2) Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0 70A3h V1 I3 I2 I1 ADCCHSELSEQ1 70A4h x x V3 V2 ADCCHSELSEQ2 70A5h x x x x ADCCHSELSEQ3 70A6h x x x x ADCCHSELSEQ4 Table 1-5.
www.ti.com Uninterrupted Autosequenced Mode Notes: • • • • An SOC trigger can initiate an autoconversion sequence whenever a sequencer is in an idle state. An idle state is either CONV00 prior to receiving a trigger, or any state which the sequencer lands on at the completion of a conversion sequence, i.e., when SEQ_CNTR has reached a count of zero.
www.ti.com Uninterrupted Autosequenced Mode Figure 1-8.
www.ti.com ADC Clock Prescaler 1.4 ADC Clock Prescaler The peripheral clock HSPCLK is divided down by the ADCCLKPS[3:0] bits of the ADCTRL3 register. An extra divide-by-two is provided via the CPS bit of the ADCTRL1 register. In addition, the ADC can be tailored to accommodate variations in source impedances by widening the sampling/acquisition period. This is controlled by the ACQ_PS[3:0] bits in the ADCTRL1 register.
www.ti.com Power-up Sequence Table 1-8. Power Options Power Level 1.6 ADCBGRFDN1 ADCBGRFDN0 ADCPWDN ADC power-up 1 1 1 ADC power-down 1 1 0 ADC off 0 0 0 Reserved 1 0 X Reserved 0 1 X Power-up Sequence The ADC resets to the ADC off state. When powering up the ADC, use the following sequence: 1. If external reference is desired, enable this mode using bits 15-14 in the ADCREFSEL Register. This mode must be enabled before band gap is powered. 2.
www.ti.com ADC Calibration Recommendations and caution on sequencer override feature: • After reset, SEQ_OVRD bit will be 0; therefore the sequencer override feature remains disabled. • When SEQ _OVRD bit is set for all nonzero values of MAX_CONVn, the related interrupt flag bit will be set for every MAX_CONVn count of result register update. • For example, if ADCMAXCONV is set to 3, then the interrupt flag for the selected sequencer will be set every four result register updates.
www.ti.com ADC Calibration 1.8.1 ADC_Cal Assembly Routine Method The following three steps describe how to call the ADC_cal routine from an application: Step 1. Add the ADC_cal assembly function to your project. The source is included with the C2833x C/C++ Header Files and Peripheral Examples (SPRC530). The following code shows the contents of the ADC_cal function. The values 0xAAAA and 0xBBBB are place holders. The actual values programmed by TI are device specific.
www.ti.com Internal/External Reference Voltage Selection 1.9 Internal/External Reference Voltage Selection By default, an internally generated bandgap voltage reference is selected to supply the ADC logic. Based on customer application requirements, the ADC logic may be supplied by an external voltage reference. The ADC will accept 2.048 V, 1.5 V, or 1.024 V on the ADCREFIN pin. The value of the ADCREFSEL register determines the reference source selected.
www.ti.com Offset Error Correction 1.10 Offset Error Correction The 2833x ADC supports offset correction via a 9-bit field in the ADC Offset Trim Register(ADCOFFTRIM). The value contained in this register will be added/subtracted before the results are available in the ADC result registers. This operation is contained in the ADC module, so timing for results will not be affected.
www.ti.com ADC to DMA Interface Figure 1-13. Ideal Code Distribution of Sampled 0-V Reference Hits per code 0 1 2 3 ADC output code 4095 1.11 ADC to DMA Interface The ADC result registers located in peripheral frame 0 (0x0B00 – 0x0B0F) are accessible by the DMA unit on the F2833x. These registers can also be accessed by the CPU at the same time as the DMA without bus contention. The result registers in peripheral frame 2 (0x7108 – 0x710F) are not accessible by the DMA.
Chapter 2 SPRU812A – September 2007 – Revised October 2007 ADC Registers This chapter contains the ADC registers and bit definitions, with the registers grouped by function. Topic 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 .................................................................................................. ADC Control Registers .............................................................. Maximum Conversion Channels Register (ADCMAXCONV) ........... Autosequence Status Register (ADCASEQSR) .........
www.ti.com ADC Control Registers 2.1 ADC Control Registers Figure 2-1. ADC Control Register 1 (ADCTRL1) (Address Offset 00h) 15 14 Reserved RESET 13 SUSMOD 12 11 ACQ_PS 8 R-0 R/W-0 R/W-0 R/W-0 7 6 5 4 CPS CONT_RUN SEQ_OVRD SEQ_CASC 3 Reserved 0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 2-1. ADC Control Register 1 (ADCTRL1) Field Descriptions Bit(s) Name Value Description 15 Reserved Reads return a zero.
www.ti.com ADC Control Registers Table 2-1. ADC Control Register 1 (ADCTRL1) Field Descriptions (continued) Bit(s) 5 4 3-0 Name Value Description 0 Start-stop mode. Sequencer stops after reaching EOS. On the next SOC, the sequencer starts from the state where it ended unless a sequencer reset is performed. 1 Continuous conversion mode. After reaching EOS, the behavior of the sequencer depends on the state of the SEQ_OVRD bit.
www.ti.com ADC Control Registers Table 2-2. ADC Control Register 2 (ADCTRL2) Field Descriptions (continued) Bit(s) Name 13 Value SOC_SEQ1 Description Start-of-conversion (SOC) trigger for Sequencer 1 (SEQ1) or the cascaded sequencer. This bit can be set by the following triggers: • S/W - Software writing a 1 to this bit • ePWM SOCA • ePWM SOCB (only in cascaded mode) • EXT - External pin (i.e., GPIO Port A pin (GPIO31-0) configured as XINT2 in the GPIOxINT2SEL register.
www.ti.com ADC Control Registers Table 2-2. ADC Control Register 2 (ADCTRL2) Field Descriptions (continued) Bit(s) Name 5 Value SOC_SEQ2 Description Start of conversion trigger for sequencer 2 (SEQ2). (Only applicable in dual-sequencer mode; ignored in cascaded mode.
www.ti.com Maximum Conversion Channels Register (ADCMAXCONV) Table 2-3. ADC Control Register 3 (ADCTRL3) Field Descriptions (continued) Bit(s) Name 4-1 Value Description 0 All analog circuitry inside the core except the bandgap and reference circuitry is powered down. 1 The analog circuitry inside the core is powered up. ADCCLKPS [3:0] Core clock divider. 28x peripheral clock, HSPCLK, is divided by 2*ADCCLKPS[3-0], except when ADCCLKPS[3-0] is 0000, in which case HSPCLK is directly passed on.
www.ti.com Maximum Conversion Channels Register (ADCMAXCONV) Table 2-4. Maximum Conversion Channels Register (ADCMAXCONV) Field Descriptions Bit(s) Name Description 15-7 Reserved Reads return a zero. Writes have no effect. 6-0 MAX_CONVn MAX_CONVn bit field defines the maximum number of conversions executed in an autoconversion session. The bit fields and their operation vary according to the sequencer modes (dual/cascaded). For SEQ1 operation, bits MAX_CONV1[2:0] are used.
www.ti.com Autosequence Status Register (ADCASEQSR) 2.3 Autosequence Status Register (ADCASEQSR) Figure 2-5. Autosequence Status Register (ADCASEQSR) (Address Offset 07h) 15 12 7 11 8 Reserved SEQ_CNTR R-0 R-0 6 4 3 0 Reserved SEQ2_STATE SEQ1_STATE R-0 R-0 R-0 LEGEND: R/W = Read/Write; R =Read only; x = undefined, -n = value after reset Table 2-6. Autosequence Status Register (ADCASEQSR) Field Descriptions Bit(s) Name Description 15-12 Reserved Reads return a zero.
www.ti.com ADC Status and Flag Register (ADCST) 2.4 ADC Status and Flag Register (ADCST) Figure 2-6. ADC Status and Flag Register (ADCST) (Address Offset 19h) 15 8 Reserved R-0 7 6 5 4 3 2 1 0 EOS_BUF2 EOS_BUF1 INT_SEQ2_CLR INT_SEQ1_CLR SEQ2_BSY SEQ1_BSY INT_SEQ2 INT_SEQ1 R-0 R-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset This register is a dedicated status and flag register.
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www.ti.com ADC Reference Select Register (ADCREFSEL) 2.5 ADC Reference Select Register (ADCREFSEL) Figure 2-7. ADC Reference Select Register (ADCREFSEL) (Address Offset 1Ch) 15 14 13 0 REF_SEL Reserved R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 2-9. ADC Reference Select Register (ADCREFSEL) Field Descriptions Bit(s) Name 15-14 REF_SEL[1:0] 13-0 2.
www.ti.com ADC Input Channel Select Sequencing Control Registers 2.7 ADC Input Channel Select Sequencing Control Registers Figure 2-9. ADC Input Channel Select Sequencing Control Registers (ADCCHSELSEQ1) (Address Offset 03h) 15 12 11 8 7 4 3 0 CONV03 CONV02 CONV01 CONV00 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Figure 2-10.
www.ti.com ADC Conversion Result Buffer Registers (ADCRESULTn) Table 2-11. CONVnn Bit Values and the ADC Input Channels Selected (continued) 2.8 CONVnn Value ADC Input Channel Selected 1101 ADCINB5 1110 ADCINB6 1111 ADCINB7 ADC Conversion Result Buffer Registers (ADCRESULTn) In the cascaded sequencer mode, registers ADCRESULT8 through ADCRESULT15 holds the results of the ninth through sixteenth conversions.
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