Specifications
t
OD
t
AD
Sample N
DI
Sample N+1
DI
Sample N-1
V
IN
Q+/-
CLK+
DCLKQ+/-
(0° Phase)
DQ, DI Sample N-35.5, N-35
t
OSK
Sample N-34.5, N-34 Sample N-33.5, N-33
Sample N-36.5, N-36Sample N-37.5, N-37
Sample N + 0.5
Sample N - 0.5
DQ
DQ
c
t
OD
t
AD
Sample N
DI
Sample N+1
DId
Sample N-1
V
IN
Q+/-
CLK+/-
DCLKQ+/-
(0° Phase)
DQd, DId,
DQ, DI
Sample N-35.5, N-35,
N-34.5, N-34
Sample N-37.5, N-37,
N-36.5, N-36
Sample N-39.5, N-39,
N-38.5, N-38
t
OSK
t
SU
t
H
DCLKQ+/-
(90° Phase)
c
c
c
c
Sample N-0.5
Sample
N-1.5
DQ
DQd
c
ADC12D1800RF
SNAS518I –JULY 2011–REVISED JANUARY 2014
www.ti.com
Figure 4-5. Clocking in 1:4 Demux DES Mode*
Figure 4-6. Clocking in Non-Demux Mode DES Mode*
NOTE
*The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-
inputs may be used. For this case, the I-channel functions precisely the same as the Q-
channel, with VinI, DCLKI, DId and DI instead of VinQ, DCLKQ, DQd and DQ. Both I- and Q-
channel use the same CLK.
34 Specification Definitions Copyright © 2011–2014, Texas Instruments Incorporated
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