Specifications

SCLK
1
8 9
24
Single Register Access
SCS
SDI
Command Field
MSB
LSB
Data Field
t
SSU
t
SH
t
SCS
t
HCS
t
HCS
SDO
read mode)
MSB
LSB
Data Field
t
BSU
High Z High Z
CalRun
POWER
SUPPLY
CAL
t
CAL
t
CAL
Calibration Delay
determined by
CalDly (Pin V4)
t
CalDly
t
CAL_L
t
CAL_H
CLK
Synchronizing Edge
DCLKI+
DCLKQ+
t
HR
DCLK_RST-
t
PWR
t
SR
DCLK_RST+
t
OD
t
SYNC_DLY
ADC12D1800RF
www.ti.com SNAS518I –JULY 2011–REVISED JANUARY 2014
Figure 4-7. Data Clock Reset Timing (Demux Mode)
Figure 4-8. Power-on and On-Command Calibration Timing
Figure 4-9. Serial Interface Timing
Copyright © 2011–2014, Texas Instruments Incorporated Specification Definitions 35
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