Specifications

ADC12D1800RF
SNAS518I –JULY 2011–REVISED JANUARY 2014 www.ti.com
Table 6-28. Aperture Delay Fine Adjust
(1)
Addr: Dh (1101b) POR state: 0000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FAM(5:0) Res Res
POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(1) This feature functionality is not tested in production test; performance is tested in the specified / default mode only.
Aperture Delay Adjust feature cannot be used in DES mode (DESI, DESQ, DESIQ or DESCLKIQ) for CLK
frequencies above 1600 MHz.
Using the t
AD
Adjust feature at its maximum setting, for the maximum sampling clock rate, may affect the
integrity of the sampling clock on chip. Therefore, it is not recommended to do so. The maximum setting
for the coarse adjust is 825ps. The period for the maximum sampling clock rate of is 555ps, so it should
not be necessary to exceed this value in any case.
Bits 15:10 FAM(5:0): Fine Aperture Adjust Magnitude. This 6-bit value determines the amount of additional delay that will be applied to
the input CLK when the Clock Phase Adjust feature is enabled via STA (Addr: Ch, Bit 3). The range is straight binary from 0 ps
delay for FAM(5:0) = 0d to 2.3 ps delay for FAM(5:0) = 63d (±300 fs due to PVT variation) in steps of ~36 fs.
Bits 9:0 Reserved. Must be set as shown.
Table 6-29. AutoSync
Addr: Eh (1110b) POR state: 0003h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DRC(8:0) DCK Res SP(1:0) ES DOC DR
POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bits 15:7 DRC(8:0): Delay Reference Clock (9:0). These bits may be used to increase the delay on the input reference clock when
synchronizing multiple ADCs. The minimum delay is 0s (0d) to 1200 ps (319d). The delay remains the maximum of 1200 ps for
any codes above or equal to 639d. See SYNCHRONIZING MULTIPLE ADC12D1800RFS IN A SYSTEM for more information.
Bit 6 DCK: DESCLKIQ Mode. Set this bit to 1b to enable Dual-Edge Sampling, in which the Sampling Clock samples the I- and Q-
channels 180° out of phase with respect to one another, i.e. the DESCLKIQ Mode. To select the DESCLKIQ Mode, Addr: 0 h,
Bits<7:5> must also be set to 000b. See DES/Non-DES Mode for more information.
Bit 5 Reserved. Must be set as shown.
Bits 4:3 SP(1:0): Select Phase. These bits select the phase of the reference clock which is latched. The codes correspond to the
following phase shift:
00 = 0°
01 = 90°
10 = 180°
11 = 270°
Bit 2 ES: Enable Slave. Set this bit to 1b to enable the Slave Mode of operation. In this mode, the internal divided clocks are
synchronized with the reference clock coming from the master ADC. The master clock is applied on the input pins RCLK. If this
bit is set to 0b, then the device is in Master Mode.
Bit 1 DOC: Disable Output reference Clocks. Setting this bit to 0b sends a CLK/4 signal on RCOut1 and RCOut2. The default
setting of 1b disables these output drivers. This bit functions as described, regardless of whether the device is operating in
Master or Slave Mode, as determined by ES (Bit 2).
Bit 0 DR: Disable Reset. The default setting of 1b leaves the DCLK_RST functionality disabled. Set this bit to 0b to enable
DCLK_RST functionality.
74 Functional Description Copyright © 2011–2014, Texas Instruments Incorporated
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