Specifications

ManualsBrandsADC ManualsBlood Pressure Monitor6015

dsPIC30F6010A/6015

The dsPIC30F6010A/6015 (Rev. A2/A3) samples that

you have received were found to conform to the

specifications and functionality described in the

following documents:

• DS70157 – “dsPIC30F/33F Programmer’s

Reference Manual”

• DS70150 – “dsPIC30F6010A/6015 Data Sheet”

• DS70046 – “dsPIC30F Family Reference Manual”

The exceptions to the specifications in the documents

listed above are described in this section. These

exceptions are described for the specific devices listed

below:

• dsPIC30F6010A

• dsPIC30F6015

These devices may be identified by the following

message that appears in the MPLAB

ICD 2 Output

Window under MPLAB IDE, when a “Reset and

Connect” operation is performed within MPLAB IDE:

Setting Vdd source to target

Target Device dsPIC30F6010A found,

revision = Rev A2

...Reading ICD Product ID

Running ICD Self Test

...Passed

MPLAB ICD 2 Ready

The errata described in this section will be addressed

in future revisions of dsPIC30F6010A and

dsPIC30F6015 devices.

Silicon Errata Summary

The following list summarizes the errata described in

this document:

1. DISI Instruction

The DISI instruction will not disable interrupts if

DISI instruction is executed in the same

instruction cycle that the DISI counter

decrements to zero.

2. Output Compare Module

The output compare module will produce a glitch

on the output when an I/O pin is initially set high

and the module is configured to drive the pin low at

a specified time.

3. Output Compare Module in PWM Mode

Output compare will produce a glitch when

loading 0% duty cycle in PWM mode. It will also

miss the next compare after the glitch.

4. Quadrature Encoder Interface Module

The Index Pulse Reset mode of the QEI does not

work properly when used along with count error

detection. When counting upwards, the POSCNT

index pulse is received. The extra count will

generate a false count error interrupt.

5. INT0, ADC and Sleep Mode

ADC event triggers from the INT0 pin will not

wake-up the device from Sleep mode if the SMPI

bits are non-zero.

6. 10-bit ADC: Sampling Rate

The 10-bit Analog-to-Digital Converter (ADC) has

a maximum sampling rate of 750 ksps.

7. Quadrature Encoder Interface (QEI) Module

The QEI module does not generate an interrupt in

a particular overflow condition.

8. Sleep Mode

Execution of the Sleep instruction (PWRSAV #0)

may cause incorrect program operation after the

device wakes up from Sleep. The current con-

sumption during Sleep may also increase beyond

the specifications listed in the device data sheet.

9. I

C™ Module

The I

C module loses incoming data bytes when

operating as an I

C slave.

dsPIC30F6010A/6015 Rev. A2/A3 Silicon Errata

Summary of content (14 pages)

PAGE 1
dsPIC30F6010A/6015 dsPIC30F6010A/6015 Rev. A2/A3 Silicon Errata The dsPIC30F6010A/6015 (Rev. A2/A3) samples that you have received were found to conform to the specifications and functionality described in the following documents: Silicon Errata Summary • DS70157 – “dsPIC30F/33F Programmer’s Reference Manual” • DS70150 – “dsPIC30F6010A/6015 Data Sheet” • DS70046 – “dsPIC30F Family Reference Manual” 1. The exceptions to the specifications in the documents listed above are described in this section.
PAGE 2
dsPIC30F6010A/6015 10. Motor Control PWM – PWM Counter Register PTMR does not continue counting down after halting code execution in Debug mode. 11. I/O Port – Port Pin Multiplexed with IC1 The port I/O pin multiplexed with the Input Capture 1 (IC1) function cannot be used as a digital input pin when the UART auto-baud feature is enabled. 12.
PAGE 3
dsPIC30F6010A/6015 1. Module: DISI Instruction When a user executes a DISI #7, for example, this will disable interrupts for 7 + 1 cycles (7 + the DISI instruction itself). In this case, the DISI instruction uses a counter which counts down from 7 to 0. The counter is loaded with 7 at the end of the DISI instruction.
PAGE 4
dsPIC30F6010A/6015 4. Module: Quadrature Encoder Interface The Index Pulse Reset mode of the QEI does not work properly when used along with count error detection. When counting upwards, the POSCNT register will increment one extra count after the index pulse is received. The extra count will generate a false count error interrupt. Work around There are multiple work arounds for this issue, depending on the specific requirements of the application: 1.
PAGE 5
dsPIC30F6010A/6015 6. Module: 10-bit ADC: Sampling Rate The maximum sampling rate for the 10-bit Analog-to-Digital Conversion module is 750 ksps. This rate is only achievable when one A/D pin is being used. Configuring the ADC module to use multiple sample-and-hold circuits (see device data sheet), will not improve the conversion speed of the module. Table 1 shows the maximum ADC conversion rates possible using the 10-bit ADC module and the corresponding module configuration and operating conditions.
PAGE 6
dsPIC30F6010A/6015 7. Module: QEI Interrupt Generation Work around The Quadrature Encoder Interface (QEI) module does not generate an interrupt when MAXCNT is set to 0xFFFF and the following events occur: To prevent this condition from occurring, set MAXCNT to 0x7FFF, which will cause an interrupt to be generated by the QEI module. 1. POSCNT underflows from 0x0000 to 0xFFFF. 2. POSCNT stops. 3. POSCNT overflows from 0xFFFF to 0x0000.
PAGE 7
dsPIC30F6010A/6015 8. Module: Sleep Mode Execution of the Sleep instruction (PWRSAV #0) may cause incorrect program operation after the device wakes up from Sleep. The current consumption during Sleep may also increase beyond the specifications listed in the device data sheet. Work arounds To avoid this issue, any of the following three work arounds can be implemented, depending on the application requirements.
PAGE 8
dsPIC30F6010A/6015 Work around 2: Work around 3: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 512 kHz Low-Power RC (LPRC) Oscillator with a 64:1 postscaler mode. This enables the device to operate at 0.002 MIPS, thereby significantly reducing the current consumption of the device.
PAGE 9
dsPIC30F6010A/6015 9. Module: I2C Work around 2: When the I2C module is configured as a slave, either in single-master or multi-master mode, the I2C receiver buffer is filled whether a valid slave address is detected or not. Therefore, an I2C receiver overflow condition occurs and this condition is indicated by the I2COV flag in the I2CSTAT register. Use this work around for applications in which the I2C receiver interrupt is required.
PAGE 10
dsPIC30F6010A/6015 11. Module: I/O Port – Port Pin Multiplexed with IC1 If the user application enables the auto-baud feature in the UART module, the I/O pin multiplexed with the IC1 (Input Capture) pin cannot be used as a digital input. Work around None. 15. Module: PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of an PSV page. This only occurs when using the following addressing modes: • MOV.
PAGE 11
dsPIC30F6010A/6015 18. Module: I2C When the I2C module is enabled by setting the I2CEN bit in the I2CCON register, the dsPIC DSC device generates a glitch on the SDA and SCL pins. This glitch falsely indicates “Communication Start” to all devices on the I2C bus, and can cause a bus collision in a multi-master configuration. Additionally, when the I2CEN bit is set, the S and P bits of the I2C module are set to values ‘1’ and ‘0’, respectively, which indicate a “Communication Start” condition.
PAGE 12
dsPIC30F6010A/6015 APPENDIX A: REVISION HISTORY Revision A (01/2006) Original version of the document. Revision B (9/2006) Added silicon issues 1 and 6. Revision C (3/2007) Added silicon issue 7. Revision D (9/2007) Added silicon issue 8 (QEI Interrupt Generation) and 9 (Sleep Mode). Revision E (12/2007) Added silicon issues 10 and 11 (I2C), 12 (Motor Control PWM – PWM Counter Register), and 13 (I/O Port – Port Pin Multiplexed with IC1).
PAGE 13
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 14
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.