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MYXPM6021*

Revision 1.1 - 10/21/14

*Advanced information. Subject to change without notice.

MYXPM6021*

Form #: CSI-D-685 Document 011

Power Management IC (PMIC)

Features

• Intel

AtomBayTrailPMIC

• Tin-leadballmetallurgy

• PartnumberMYXPM6021

• Twohighefciencybuckconverterswithintegrated

SVIDinterfacerunningIMVP-7protocol.Thesetwo

quadphaseDC/DCregulatorsgeneratethevoltagesfor

CPUandgraphiccores

• Onedualphasebuckregulatorformemorysupply

supportingDDR3-Land-LPmemorytypes

• 3singlephasebuckregulatorssupplying1.0V,1.05V

and1.8Vtowardstheplatform

• 2buck-boostconvertersgenerating2.85Vand3.3Vfor

theplatformeveniftheinputsupplyisdownto2.7V

• Boostconverterproviding5VfortheUSBcomponents

• 3LDOswithxedoutputvoltage

• 2LDOswithprogrammableoutputvoltage

• 1push-pullLDOusedforDDR3addresslinetermination

• 11integratedpowerrailswitchingdevices

• 9externalpowerrailswitchingdevices

• UltraexiblepowersequencerprogrammableviaOTP/

EEPROMandregister

• I2CcommunicationinterfaceforSoCaccess

• EEPROMinterfaceforoptionalOTPover-writing

• 16generalpurposeI/Oswithalternatefunctions

• 16channel10-bitADCincludingconditioningcircuits

andprogrammableexiblesequencingforautomatic

andmanualmeasurements

• Systemvoltageandtemperaturemonitoring,supervising

• ProgrammableIRQcontroller

• 1-wiredigitalbatteryinterfaceincluding2-wire

conversion

• 3channelPWMsignalgeneration,exiblefrequencyand

dutycycleprogrammable

• Inputpowersourcedetection,includedwithcharger

control

• 325ballFCBGA11mmx6mm,0.4mmpitchpackage

• OperatingTempRange:-30C-+85C

PleasecontactaMicrosssalesrepresentativeforIBISor

thermalmodelsatsales@micross.com.

Summary of content (113 pages)

PAGE 1
MYXPM6021* *Advanced information. Subject to change without notice. Power Management IC (PMIC) Features • 3 channel PWM signal generation, flexible frequency and duty cycle programmable • Intel® Atom Bay Trail PMIC • Tin-lead ball metallurgy • Input power source detection, included with charger control • Part number MYXPM6021 • Two high efficiency buck converters with integrated SVID interface running IMVP-7 protocol.
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MYXPM6021* *Advanced information. Subject to change without notice. 1 General Description The MYXPM6021 PMIC is a monolithic single chip power management IC for the next generation Intel® Atom™ processor. It provides all power supplies for tablet PC’s and can also be used in multiple embedded applications as well as Netbooks and Nettops. It is designed to support platforms based on Intel’s new Atom processor series, including DDR3 memory and various peripherals.
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MYXPM6021* *Advanced information. Subject to change without notice. 2 Key Features • Two high efficiency buck converters with integrated SVID interface running IMVP-7 protocol. These two quad phase DC/DC regulators generate the voltages for CPU and graphic cores. • One dual phase buck regulator for memory supply supporting DDR3-L and -LP memory types • 3 single phase buck regulators supplying 1.0V, 1.05V and 1.8V towards the platform • 2 buck-boost converters generating 2.85V and 3.
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MYXPM6021* *Advanced information. Subject to change without notice. 3 Overview MYXPM6021 features: • Power Sequencer & System Control: MYXPM6021 includes an ultra-flexible power sequencer programmable via OTP during manufacturing process and modifiable via external EEPROM data.
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MYXPM6021* *Advanced information. Subject to change without notice. • Display Control: • BCU: Battery controller unit, supervising peripherals based on system voltage. • PWM: The MYXPM6021 can generate up to 3 PWM signals with programmable duty-cycle and frequency to accommodate some external functionality. • GPIOs: 16 general purpose I/O with alternate functions. MYXPM6021* Revision 1.
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MYXPM6021* *Advanced information. Subject to change without notice. 4 Block Diagram Figure 1: Overview Diagram MYXPM6021* Revision 1.
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MYXPM6021* *Advanced information. Subject to change without notice. Figure 2: Detailed Block Diagram MYXPM6021 MYXPM6021* Revision 1.
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MYXPM6021* *Advanced information. Subject to change without notice. 5 Operating Conditions All voltages are referenced to VSS unless otherwise stated. Currents flowing into MYXPM6021 are deemed positive, currents flowing out are deemed negative. All parameters are valid over the full operating temperature range and power supply range unless otherwise noted. Please note that the power dissipation must be limited to avoid overheating of MYXPM6021.
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MYXPM6021* *Advanced information. Subject to change without notice. 6 Pinning Information The “_B” symbol at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage level (active low). When the “_B” is not present after the signal name the signal is asserted when the signal is at a high voltage level.
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MYXPM6021* *Advanced information. Subject to change without notice.
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MYXPM6021* *Advanced information. Subject to change without notice.
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MYXPM6021* *Advanced information. Subject to change without notice.
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MYXPM6021* *Advanced information. Subject to change without notice.
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MYXPM6021* *Advanced information. Subject to change without notice.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 3: Pin Description (continued) Pin Name Pins Power Domain Description Type DEBUG_I2C_CLK 1 V1P8S I2C clock debug channel I DEBUG_I2C_DATA 1 V1P8A I2C data debug channel IO Table 4: Pin Type Definition Pin Type Description Pin Type Description I Input D Digital O Output P Power A Analog MYXPM6021* Revision 1.
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MYXPM6021* *Advanced information. Subject to change without notice. 7 Operating Conditions 7.1 System Control Signals 7.1.1 VDCIN_SENSE Input voltage is limited to the maximum input voltage via the resistor divider of the AC/DC adapter. 7.1.2 ACPRESENT ACPRESENT is an active high dedicated output signal that indicates the AC/DC adapter or USB DCP/CDP/ACA (CHGDET_B=0) is connected to a valid voltage. 7.1.3 VBUS_SENSE USB input voltage detection. 7.1.
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MYXPM6021* *Advanced information. Subject to change without notice. 7.1.10 IRQ IRQ is an active high dedicated output signal that generates interrupts to the SOC. It is asserted when at least one unmasked interrupt bit is set in the 1st level interrupt register. It is valid when RSMRST_B=1 (de-asserted). The maximum latency from the IRQ detection to the assertion of the IRQ line is 1ms. 7.1.11 I2CM_CLK I2C clock signal from MYXPM6021 to external I2C EEPROM. 7.1.
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MYXPM6021* *Advanced information. Subject to change without notice. 7.1.18 SLP_S4_B SLP_S4_B is an active low dedicated input signal from the SOC that indicates S4 state entry upon assertion (SLP_S4_ B=LOW) and exit upon de-assertion (SLP_S4_B=HIGH). The assertion/de-assertion of the SLP_S4_B signal from the SOC launches SOC_S4 state entry/exit sequence. It is valid only when RSMRST_B=1. 7.1.19 RSMRST_B RSMRST_B is an active low dedicated output signal. RSMRST_B asserts when voltage rail V3P3A is enabled.
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MYXPM6021* *Advanced information. Subject to change without notice. 7.1.25 SUSCLK SUSCLK is the 32.768kHz RTC clock that is supplied from the SoC. It is available to MYXPM6021 about 100ms after RSMRST_B is de-asserted and continue to be available in S0, S0iX, S3 and S4 state. It is not available if the platform will be in G3 mode when the suspend voltage rails are disabled. 7.1.26 THERMTRIP_B THERMTRIP_B is an active low dedicated input signal that notifies the PMIC of a SOC thermal event.
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MYXPM6021* *Advanced information. Subject to change without notice. catastrophic shutdown condition which would normally bypass a Cold Off Task List being run, the SDWN_B pin must be asserted a minimum of 900us prior to this catastrophic shutdown commencing. The nominal voltage of SDWN_B is 0V when asserted, 1.8V when de-asserted. 7.1.32 USBRST_B USBRST_B is an active low dedicated output signal to reset the USB PHY. The minimum pulse is 100μs when asserted.
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MYXPM6021* *Advanced information. Subject to change without notice. 7.1.34.2 BCUDISB Burst controller unit warning zone B. output signal to disable peripherals (functions). 7.1.34.3 BCUDISCRIT Burst controller unit critical zone. Output signal to disable peripherals (functions). 7.1.35 PWM[2:0] Pulse width modulated output control signals. 7.1.36 DISPLAY 7.1.36.1 BACKLIGHT_EN Output signal to control the display backlight. 7.1.36.2 PANEL_EN Output signal to enable the display. 7.1.37 ADC 7.1.37.
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MYXPM6021* *Advanced information. Subject to change without notice. 7.2 MYXPM6021 Power States Following is a brief description of these states: • OFF: No power at all. The platform coin cell has no valid power. • COIN: COIN domain is powered and not under reset. Coin domain refers to a small logic portion inside MYXPM6021, which gets a reset signal and supply from the coin cell or a supercap. These logic registers retain data when MYXPM6021 supply fails or PMIC goes under the POR.
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MYXPM6021* *Advanced information. Subject to change without notice. 7.3 Register File and Address Range There are 5 register blocks, one for VNN, one for VCC, one for test purpose, one for Intel and another block controlling the power sequence. These blocks can either be accessed via the SVID or I2C interface, via OTP or the external EEPROM, see picture blow. Figure 4: Address Range and Pages The power sequence is located in the page 0 of the register map and shall not be modified by customer.
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MYXPM6021* *Advanced information. Subject to change without notice. 8 Power Controller State Machine 8.1 Overview The power controller state machine is the main state machine of the MYXPM6021. It is comprised of two phases. The first phase impliments the power up sequence. It evaluates all of the conditions for a safe boot up and the configuration data is also read out of the OTP/EEPROM.
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MYXPM6021* *Advanced information. Subject to change without notice. 8.2.1 Sequencing Each PMIC component (such as a DC/DC converter, LDO, internal or external power switch … ) can be configured with great flexibility to control the power sequencing, including the independent enabling and disabling of each component during power-up and power-down. The sequencing is defined by the Intel processor specification, with the implementation accordingly.
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MYXPM6021* *Advanced information. Subject to change without notice. 9 Platform Power Domains 9.1 Power Domains Summary The power supply part of MYXPM6021 consists of various power supplies modules: Table 5: Power Domains Power Supply Module MYXPM6021 Supplied Pins Supplied Voltage Supplied Current Notes BUCK_CORE VCC 0.5 – 1.2V ±2% accuracy (DC & ripple) Default: 1.0V ±1.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 5: Power Domains (continued) Power Supply Module MYXPM6021 Supplied Pins Supplied Voltage Supplied Current Notes LDO_VDDQ_VTT VDDQ_VTT ½ VDDQ ±2% accuracy (DC) 325mA Push-pull LDO for DDR3 address line termination. LDO_V1P2A V1P2A 1.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 5: Power Domains (continued) 9.
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MYXPM6021* *Advanced information. Subject to change without notice.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 7: PMIC Current Consumption (continued) Power State 9.4 Min Typ. [mA] SOC_G3 0.069 G3 0.056 Max Voltage Rail Control Mechanism Proper power-up/down sequencing is mandatory to prevent damages. There are several methods controlling the power rails.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 9: SVID DC Electrical Characteristics Symbol Parameter Min Typ Max Unit 0.95 1.00 1.05 V 0.45* V1P0S V 1 1 V1P0S SVID IO voltage VIL Input low voltage VIH Input high voltage 0.65* V1P0S V VHYS Hysteresis voltage 0.05 V VOH Output high voltage RON Buffer on resistance (data line & alert# line) V1P0S Notes V 1 10 20 Ω 2 -100 100 uA 3 4 IL Leakage current CPAD Pad capacitance 4.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 10: SVID buffer AC Electrical Parameters Symbol Max Unit -1.00 3.30 V SR Fall Data/Alert 1.20 3.50 V/ns Load: Rpu=64.9Ω SR Rise Data/Alert 1.20 3.50 V/ns Load: Rpu=64.9Ω Vmax Parameter VDS max open drain buffer to accommodate bus ringing Min Typ Notes Slew Rate (SR) is measured between 0.7*V1P0S and 0.3*V1P0S.
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MYXPM6021* *Advanced information. Subject to change without notice. Figure 7: Measurement Points for VCLK 9.6 Power Supplies 9.6.1 DC/DC Buck Regulator VCC The BUCK_CORE converter is a high efficiency synchronous quad phase step down regulator operating at a high frequency (3 MHz) supplying a voltage (VCC) of 0.5 … 1.2V at maximum 8000mA. This buck regulator has the ability to dynamically change its output voltage setting to comply with the SoC’s frequency-power requirements.
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MYXPM6021* *Advanced information. Subject to change without notice. 9.6.1.1 Electrical Characteristics VCC Table 12: Electrical Parameters for BUCK_VCC Parameter Test Conditions Min VCC_IN Input Voltage Typ 2.7 Max Unit 4.5 V Cin at VCC_IN 4 x 4.7 μF Cout 6 x 47 μF ESR of output capacitor 6 @ 47μF mΩ ESL of output capacitor 1.6 @ 3MHz nH L_BUCK inductor value -20% 4x0.47 L_R inductor DC resistance VCC Output Voltage IOUT= Imax 0.50 VCC Output Accuracy +20% μH 48 mΩ 1.
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MYXPM6021* *Advanced information. Subject to change without notice. Notes: 1. Including DC accuracy, ripple and load regulation 2. Including DC accuracy, ripple and load regulation 3. RDSON measurement on ATE Figure 9: VCC Efficiency 9.6.2 DC/DC Buck Regulator VNN The BUCK_VNN converter is a high efficiency synchronous step down regulator operating at a high frequency (3 MHz) supplying a voltage (VNN) of 0.5 … 1.2V at maximum 8000mA.
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MYXPM6021* *Advanced information. Subject to change without notice. 9.6.2.2 Electrical Characteristics VNN Table 13: Electrical Parameters for BUCK_VNN Parameter Test Conditions Min VCC_IN Input Voltage Typ 2.7 Cin at VCC_IN Max Unit 4.5 V 4 x 4.7 Cout μF 6 x 22 μF ESR of output capacitor 6 @ 22μF mΩ ESL of output capacitor 1.6 @ 3MHz nH L_BUCK inductor value -20% 4x0.47 L_DCR inductor DC resistance VNN Output Voltage IOUT= Imax 0.50 VNN Output Accuracy +20% μH 48 mΩ 1.
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MYXPM6021* *Advanced information. Subject to change without notice. Notes: 1. Including DC accuracy, ripple and load regulation 2. Including DC accuracy, ripple and load regulation 3. RDSON measurement on ATE Figure 11: VNN Efficiency 9.6.3 DC/DC Buck Regulator V1P0A The high efficiency buck regulator supplies the USB sus, clock, CFIO and the V1P0S power rails of the SoC. The power rail is also capable of supplying the pass device of the push pull source for the DDR3 address line termination.
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MYXPM6021* *Advanced information. Subject to change without notice. Figure 12: V1P0A Power Rail Block Diagram To allow for voltage drops on the PCB, it is possible to program the output voltage to either 1.01V or 1.05V. See register below. The maximum output current of the 1P0A buck regulator is 1900mA. 9.6.3.1 Electrical Characteristics V1P0A Table 14: Electrical Parameter for BUCK_V1P0A Parameter Description V1P0A_VIN Input Voltage Cin At VCC_IN 2 x 4.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 14: Electrical Parameter for BUCK_V1P0A (continued) Parameter Description Test Conditions Min Typ Max Unit Transient load current profile 5-250mA 200 Transient droop1 75-1820mA 5-250mA 40 mV Transient overshoot2 1820-75mA 250-5mA 40 mV 2 ms ns Ton Turn on time Rpd Discharge impedance Vout ..
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MYXPM6021* *Advanced information. Subject to change without notice. Figure 13: V1P0A Efficiency 9.6.3.2 V1P0A Subsystem V1P0S: This voltage rail powers the SoC graphic, display & DDR3 I/O, MIPI, clock and further functions. The current requirement of this voltage rail is 410mA and requests an external switch providing this power rail to the SoC. MYXPM6021 provides a control signal named V1P0S_EN supplied by V5P0S.
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MYXPM6021* *Advanced information. Subject to change without notice. V1P0SX external N-channel power switch parameters: Rdson (Vgs=4V) 10-22mohm Input capacitance, Ciss 750-2640pF Output capacitance, Coss 150-530pF Reverse transfer capacitance, Crss 85-465pF VDDQ_VTT: The VDDQ_VTT power rail is a push-pull LDO capable to source and sink maximum 325mA. VDDQ_VTT is ½ of VDDQ and its pass device is sourced by V1P0_A in order to reduce the overall power dissipation in the system.
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MYXPM6021* *Advanced information. Subject to change without notice. 9.6.4 DC/DC Buck Regulator V1P05S This high efficiency buck regulator is the supply for the L2 SRAM of the SoC. The maximum output current of the 1P05S buck regulator is 474mA. Figure 14: Buck V1P05S Block Diagram 9.6.4.1 Electrical Characteristics Table 16: Electrical Parameter for BUCK_V1P05S Parameter Description V1P05S_VIN Input Voltage Cin At V1P05S_IN Test Conditions Min Typ 2.7 Max Unit 4.5 V 4.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 16: Electrical Parameter for BUCK_V1P0A (continued) Parameter Description Test Conditions Min Typ Max Unit Normal Mode – Synchronous Rectification (PWM) Maximum Output Current (Imax) ILIMIT Current limitation Cycle by cycle Efficiency at VSYS = 3.7V & Tamb=60°C with proposed external components and PCB layout 475 mA 900 mA See Figure 15 Sleep Mode – Pulse Skipping (PSK) Efficiency at VSYS = 3.
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MYXPM6021* *Advanced information. Subject to change without notice. 9.6.5 DC/DC Buck Regulator V1P8_A This high efficiency buck regulator is the supply for the 1.8V I/Os, USB, V1P8U, V1P8S and V1P8SX.The maximum output current of the 1P8A buck regulator is 1627mA 9.6.5.1 Power States Figure 16: Buck V1P8A Power Rail Block Diagram 9.6.5.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 17: Electrical Parameter for BUCK_V1P8A (continued) Parameter Description L_DCR Inductor resistance V1P0A Output v Frequency of Operation oltage F_BUCK Frequency of operation Test Conditions Min IOUT= Imax Typ Max Unit 48 mΩ 1.
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MYXPM6021* *Advanced information. Subject to change without notice. Figure 17: V1P8A Efficiency 9.6.5.3 V1P8A Subsystems V1P8U: This power rail is primarily to supply LPDDR2 or LPDDR3 RAMs. MYXPM6021 provides a control signal V1P8U_EN_B supplied by VSYS and derived from SLP_S4_B sent out by the SoC. When V1P8U_EN_B is asserted low, the signal slew rate is controlled to limit the inrush current when the external P-channel FET is turned on. The current of this power rail is a maximum 355mA.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 18: V1P8S Power Switch Specification Description Value [max, mΩ] Input power path board resistance 10 Output power path board resistance 20 Input, output rails wirebond & internal FET RDS-ON 242 V1P8SX: This power rail is used to source platform devices such as eMMC, camera, audio codecs … The maximum allowed output current is 240mA.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 20: Electrical Parameter for V1P2A (continued) Symbol Parameter Min PSRR Power supply rejection ratio 50 Vnoise Output Noise 50 Typ Max Unit dB Notes / Condition Noise = 0.
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MYXPM6021* *Advanced information. Subject to change without notice. Figure 18: VDDQ Power Domain Block Diagram 9.6.6.1 Electrical Characteristics VDDQ Table 22: Electrical Parameter for BUCK_VDDQ Parameter Description VDDQ_VIN Input voltage Cin At VDDQ_IN Test Conditions Min Typ 2.7 Max Unit 4.5 V 2 x 4.7 μF Cout 2 x 47 or 4 x 22 μF ESR of output capacitor 6 @ 22/47μF mΩ ESL of output capacitor 1.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 22: Electrical Parameter for BUCK_V1P8A (continued) Parameter Description Test Conditions Min Typ Max Unit Normal Mode – Synchronous Rectification (PWM) Maximum Output Current (Imax) ILIMIT Current limitation Cycle by cycle Efficiency at VSYS = 3.7V & Tamb=60°C with proposed external components and PCB layout 2800 mA 1.3*Imax mA See Figure 19 Sleep Mode – Pulse Skipping (PSK) Efficiency at VSYS = 3.
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MYXPM6021* *Advanced information. Subject to change without notice. 9.6.6.2 VDDQ Subsystems V1P2S: This voltage rail is used to supply mainly the MIP interface. In case of 1.24V DDR3 memory the input voltage of this power domain is VDDQ and it acts as a power switch. For all other types of DDR3 memories the input voltage is V1P8A and V1P2S is generated via a small LDO.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 25: V1P2S Truth Table V1P2S_CTRL. V1P2S_SEL V1P2S_EN SLP_S3_B V1P2S 1 0 1 Off 1 1 1 On x x 0 Off V1P2SX: This voltage rail is used to supply the SoC SFR via an internal switch from VDDQ.
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MYXPM6021* *Advanced information. Subject to change without notice. MYXPM6021 provides an enable signal VSYSSX_EN_B, supplied by VSYS, driving the gate of the external FET. The MYXPM6021 also provides a feedback input signal VSYSSX_FB to control the slew rate and limit the inrush current. VSYS_SX external P-channel powe switch parameters: Rdson (Vgs=4V) 15-35mohm Input capacitance, Ciss 750-2315pF Output capacitance, Coss 265-900pF Reverse transfer capacitance, Crss 240-800pF 9.6.
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MYXPM6021* *Advanced information. Subject to change without notice. 9.6.10.1 Electrical Characteristics V2P85S Parameter Description V2P85S_VIN Input voltage Cin At V2P85S_IN Test Conditions Min Typ 2.7 Max Unit 4.5 V 4.7 μF Cout 2 x 22 μF ESR of output capacitor 6 @ 22μF mΩ ESL of output capacitor 1.6 @ 3MHz nH L_BUCK Inductor value L_DCR Inductor resistance V2P85S Output Voltage F_BUCK/BOOST Frequency of operation -20% IOUT= Imax 0.47 +20% μH 48 mΩ 1.24/1.
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MYXPM6021* *Advanced information. Subject to change without notice. Figure 21: V2P85S Efficiency 9.6.10.2 V2P85S Subsystems V2P85SX: The main purpose of this voltage rail is to provide power for cameras. The control of this power rail is derived from the SoC SLP_S0ix_B signal. The maximum current is 250mA. The internal switch has a RDSon of 460mΩ.
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MYXPM6021* *Advanced information. Subject to change without notice. Figure 22: V3P3A Power Domain Block Diagram 9.6.11.1 Electrical Characteristics V3P3A Table 29: Electrical Parameter for BUCKBOOST_V3P3A Parameter Description V3P3A_VIN Input Voltage Input voltage Cin at V3P3A_IN Test Conditions Min Typ 2.7 Max Unit 4.5 V 4.7 μF Cout 2 x 47 μF ESR of output capacitor 6 @ 22μF mΩ ESL of output capacitor 1.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 29: Electrical Parameter for BUCKBOOST_V3P3A (continued) Parameter Description IQ_ON Quiescent current in on mode Rpd Discharge impedance Test Conditions Min Typ V2P85S .. 0V Max Unit 50 μA 20 Ω Normal Mode – Synchronous Rectification (PWM) Maximum Output Current (Imax) ILIMIT Current limitation Cycle by cycle 1570 mA 1.3*Imax mA Efficiency at VSYS = 3.
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MYXPM6021* *Advanced information. Subject to change without notice. 9.6.11.2 V3P3A Subsystems V3P3U: V3P3U is the voltage rail which is sourced by V3P3A and switched by an external P-channel FET. This voltage rail is primarily for Wi-Fi and Bluetooth support. The MYXPM6021 provides a control signal V3P3_U_EN supplied by V3P3A and derived from SoC’s SLP_S4_B signal. The maximum current for this power rail is 700mA. V3P3U external P-channel power switch parameters: Rdson (Vgs=4V) 35-62.
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MYXPM6021* *Advanced information. Subject to change without notice. VSDIO: This voltage rail supplies power to the SDIO/MMC subsystem. The voltage rail is either supplied by 1.8V via V1P8_A buck converter or by V3P3_A. In case of a 3.3V supply, the internal switch has a RDSon of 200mΩ, in case of 1.8V the RDSon is 80mΩ. The maximum current is 200mA.
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MYXPM6021* *Advanced information. Subject to change without notice. Figure 24: V5P0S Power Domain Block Diagram 9.6.12.1 Electrical Characteristics V5P0S Table 33: Electrical Parameter for BOOST_V5P0S Parameter Description V5P0S_VIN Input Voltage Cin At V5P0S_IN Test Conditions Min Typ 2.7 Max Unit 4.5 V 2 x 22 μF Cout 2 x 10 μF ESR of output capacitor 6 @ 22μF mΩ ESL of output capacitor 1.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 33: Electrical Parameter for BOOST_V5P0S (continued) Parameter Description ILIMIT Current limitation Test Conditions Cycle by cycle Min Typ 1.3*Imax Efficiency at VSYS = 3.7V & Tamb=60°C with proposed external components and PCB layout Max Unit mA See Figure 25 Sleep Mode – Pulse Skipping (PSK) Efficiency at VSYS = 3.7V & Tamb=60°C with proposed external components and PCB layout See Figure 25 Notes: 1.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 34: VHOST external power switch driver capability Parameter Value V_IL >0.66V V_IH <1.1V I_EN >0.5μA VBUS: VBUS is the power rail supplying the VBUS of USB2/3 OTG through an external power switch. The maximum current of this power domain is 900mA. Table 35: VBUS external switch driver capability Parameter Value V_IL >0.66V V_IH <1.1V I_EN >0.
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MYXPM6021* *Advanced information. Subject to change without notice. Electrical Characteristics (Ta = -40 to +85 ºC) VSUP = 2.7 to 4.5V. Table 37: Electrical Parameter for LDO_LP Parameter Description VSYS1 / VSYS2 Input Voltage VLP Output Voltage Accuracy 9.7 Test Conditions Min Typ 2.7 IOUT= Imax 2.45 2.5 Room temperature Cstab Stabilization Capacitor Tolerance of ± 35% 2.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 38: Current Measurement Resolution Voltage Rail Resolution Tolerance VCC 20mA/LSB ±5% VNN 20mA/LSB ±5% V1P0A 5mA/LSB ±5% V1P05S 2.5mA/LSB ±5% VDDQ 5mA/LSB ±5% MYXPM6021* Revision 1.
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MYXPM6021* *Advanced information. Subject to change without notice. 10 I2C Interface 10.1 Overview The MYXPM6021 is a slave-only device that is mastered by the SoC. It resides off the SoC’s I2C. The slave device implemented on MYXPM6021 side is an asynchronous implementation and will support the high speed mode (3.4MHz). Some of the main features for the I2C slave are: • MYXPM6021 is accessed using a 7-bit addressing scheme.
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MYXPM6021* *Advanced information. Subject to change without notice. Figure 27: I2C Fast Speed Write Figure 28: I2C Fast Speed Read Figure 29: High Speed Write Figure 30: High Speed Read MYXPM6021* Revision 1.
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MYXPM6021* *Advanced information. Subject to change without notice. 10.4 Electrical Requirements Table 40: I2C Signal Electrical Specification Parameter Min Nom Max Units Notes Voltage (VDD) 1.71 1.8 1.89 V At pin 0.3*VDD V Vil Vih 0.7*VDD V Vhys 0.1 V Vol 0.2*VDD V Cpin 2 5 pF Tfall_hs 10 40 ns 3.33 Mb/s Operation Tfall_fs 20 300 ns 400 Kb/s Operation Tr/Tf 30 70 % Measurement Points MYXPM6021* Revision 1.
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MYXPM6021* *Advanced information. Subject to change without notice. 11 External EEPROM Controller 11.1 Overview During the initial power-on sequence the content of the OTP is copied into the sequencer execution registers. Since the OTP registers can only be programmed during the manufacturing & testing process, the EEPROM controller function provides the possibility of overwriting the sequencer execution registers in the field and/or as backup.
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MYXPM6021* *Advanced information. Subject to change without notice. • In the case where the EEPROM is connected and data at initial address SIGN_ADDR is correct, EEPROM content from SIGN_ADDR + 1 to end address STOP_ADDR will be copied to the registers starting at address register SIGN_ADDR = SIGN_ADDR + 1. • There is a status register in MYXPM6021 implemented to indicate the status of EEPROM connection, the signature matching and data copying. MYXPM6021* Revision 1.
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MYXPM6021* *Advanced information. Subject to change without notice. 12 Power Source Detection 12.1 Overview There are three input supply sources that can be detected by MYXPM6021: VBAT, VDCIN_SENSE and VBUS_SENSE referring to the battery, AC adapter and USB connector, respectfully. For all power sources dedicated comparators are used for the power detection. All detectors include de-bounce logic with a nominal time period of 100ms which can be disabled by software. 12.
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MYXPM6021* *Advanced information. Subject to change without notice. points. Note that when using the BATID comparator to sense battery insertion / removal, there are separate debounce times for insertion and removal. This is to allow for sufficient power-up sequencing of USB PHY related components on insertion, and also allow for quick detection of battery removal for SIM card early warning (via SDWN_B).
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MYXPM6021* *Advanced information. Subject to change without notice. Figure 32: Battery Single Wire Block Diagram for Analog Sensing, Digital Communication Table 44: BATID Electrical Specification Parameter Min Frequency 3.268 Voltage 1.71 Nom 1.8 Vil Max Units Notes 250 kHz Digital communication 1.89 V 0.35 V Vih 0.9 V Vhys 0.05 V Vol 0.01 V 1mA source current Cload 380 pF Trise 500 ns 0V to Vih(min) Tfall 500 ns Vpu to Vil(max) 12.2.
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MYXPM6021* *Advanced information. Subject to change without notice. last known BATID line voltage value in order to ensure that no false battery removal events are reported. 12.2.4 BSI Sensing MYXPM6021 is able to detect the presence of the RBSI resistor as shown. The RBSI is a 1% resistor and can range anywhere from 0 to 130kΩ. MYXPM6021 is able to differentiate between different ID resistances (assuming standard 1% values over the aforementioned range). 12.2.
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MYXPM6021* *Advanced information. Subject to change without notice. Figure 33: VSYS Valid Input Power Detection Table 46: VSYSREF Definition Parameter Min Typ Max Unit VSYSREFH VSYS Rising Threshold (VSYS: L->H) 2.975 3.0 3.035 V VSYSREFL VSYS Falling Threshold (VSYS: H->L) 2.675 2.70 2.725 V 90 100 110 ms tDEBOUNCE 12.
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MYXPM6021* *Advanced information. Subject to change without notice. the full 100ms de-bounce time before the SVBUSDET bit in the SPWRSRCIRQ register is cleared, indicating charger disconnection. If VBUSDBEN is cleared, SVBUSDET is cleared immediately upon VBUS becoming invalid. On any change in the SVBUSDET bit in the SPWRSRCIRQ register (set or clear), the corresponding interrupt flag, VBUSDET, is set in the PWRSRCIRQ 2nd-level interrupt register.
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MYXPM6021* *Advanced information. Subject to change without notice. VDCIN Falling (Disconnection Event) When the VDCIN level at the comparator becomes lower than the reference voltage (including falling edge hysteresis), VDCIN is considered invalid. If the VDCINDBEN bit is set in the VDCINDETCTRL register, VDCIN must be sensed as invalid for the full 100ms de-bounce time before the SDCINDET bit in the SPWRSRCIRQ register is cleared, indicating charger disconnection.
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MYXPM6021* *Advanced information. Subject to change without notice. an appropriate threshold the PMIC will assert the BATLOW pin, the processor will then take action. All thresholds are preprogrammed in OTP and can be overwritten by software. 12.6 Power Source Detection Events The events generated from the Power Source Detection Logic and driven into the event interface are: • Battery Insertion Event. • Battery Removal Event. • USB Insertion Event. • USB Removal Event. • DCIN Insertion Event.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 49: System Wake-Up Condition (continued) Events Battery Becomes Valid Power Button 12.8 Condition to be Fulfilled Comments BATLOW_B = 1 ADPWAKEEN = 1 Battery present. AC/DC insertion event (DCBOOT = 0). The wakeup is only delayed till battery is charged enough (VBAT > BATLOW). BATLOW_B = 1 USBWAKEEN = 1 Battery present. USB insertion event. The wakeup is only delayed till battery is charged enough.
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MYXPM6021* *Advanced information. Subject to change without notice. • VBATRM – MYXPM6021 detects that a battery was removed from the system by VBAT comparator when the bit BATRMSRC in the PSDETCTRL register is cleared (=0). Critical events are: • IDBATRM – MYXPM6021 detects that a battery was removed from the system by BATID presence comparator when the bit BATRMSRC in the PSDETCTRL register is set (=1). All VRs are shut down in sequenced order but without waiting for SLP_S*_B from SOC.
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MYXPM6021* *Advanced information. Subject to change without notice. 13 Analog–to–Digital Converter A general purpose analog-to-digital converter (GPADC) provides measurements of various voltages, currents and temperatures within the device. There is one 10-bit ADC which is time-division multiplexed to perform the measurements of the various parameters. The GPADC contains the 10-bit ADC, the analog input channel multiplexer and some additional analog functions. 13.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 50: ADC Electrical Charakteristics (continued) Parameter Test Conditions Min Max Unit ADC_IN1÷3 Voltage Range / channels A1, A2, A3 / ADC=[VIN / 2.5] x 1023 gain = 1.0 0 2.5 V Internal Temp. Sensor Voltage / channel A4 / ADC=[1 – 1.2 x VTJ] x 1023 gain = 3.0 0 0.833 V VBBAT Voltage Range / channel A5 / ADC=[1 - 0.2 x VBBAT] x 1023 gain = 0.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 51: ADC Channel Overview (continued) CH Description Signal Name Measurement Range Condition Comment Gain Vin/VREF T*1023 1 6 System Temp 1 (Pin: SYSTHERM1) ADCIN5 0.0V .. VLP No 7 System Temp 2 (Pin: SYSTHERM2) ADCIN6 0.0V .. VLP No Vin/VREF T*1023 1 8 VSYS (Pin: VSYS) VSYS 2.5V .. 5.5V Yes 0.8*(VSYS VLP)/VLP* 1023 0.8 9 Averaging Output Current ADCIN7 0.0V ..
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MYXPM6021* *Advanced information. Subject to change without notice. 14 System Voltage & Temperature Monitoring 14.1 Overview The system voltage and temperature monitoring allows high power, high temperature events as well as the system voltage monitoring. These functions allow several system conditions to be monitored by MYXPM6021, taking autonomous action and informing the SoC on system voltage and temperature events.
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MYXPM6021* *Advanced information. Subject to change without notice. 14.3 Backup Battery Management Configuration and status registers of MYXPM6021, and timekeeping logic (powered by a platform voltage rail VRTC) in the SOC are backed-up by a super capacitor or coin cell battery in case of SOC power loss (e.g., main battery changed). The VRTC is supplied usually through a diode by either V3P3A or VBATBKUP with V3P3A taking priority whenever it is available.
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MYXPM6021* *Advanced information. Subject to change without notice. 15 General Purpose IOs 15.1 Overview The MYXPM6021 provides 16 GPIO pins under the control of the SoC. The majority of these GPIO pins have a default configuration as CMOS inputs with weak (50 KOhm) pull downs enabled. The GPIO buffers support operation as opendrain or push pull outputs. They are split into 2 groups, each with a different fixed supply: • GPIO0P0 – GPIO0P7 support a level of 1.8V • GPIO1P0 – GPIO1P7 support 3.
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MYXPM6021* *Advanced information. Subject to change without notice. As shown in Figure 38 above, there are 5 signals which control the analog behavior of the GPIO pin. Note that EN is generated from the analog pad block itself. The following tables show the coding for configuring the GPIO pads.
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MYXPM6021* *Advanced information. Subject to change without notice. 16 External Battery Charger Control 16.1 Overview The PMIC has the ability to control an external battery charger IC. In order to determine the appropriate input current limit for the charger during certain scenarios, the CHGDET_B pin is asserted or de-asserted by the USB PHY on the platform depending on output current capability of the USB charger detected.
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MYXPM6021* *Advanced information. Subject to change without notice. 17 Interrupt Controller 17.1 Overview The interrupt control unit maintains the state of the First Level IRQ tree and is responsible for asserting and deasserting the MYXPM6021’s IRQ to the application SoC. It contains status bits for interrupts from all the second-level sub-blocks. If unmasked, the second-level interrupts will propagate to the appropriate first-level interrupt bit, as assigned below.
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MYXPM6021* *Advanced information. Subject to change without notice. Figure 39: 1st Level Interrupt 17.3 Second Level Interrupt While First-Level Interrupt bits inform the interrupt handler of which sub-block interrupted, second-level interrupt registers/ bits provide the interrupt handler with the specific nature of the block‘s interrupt event.
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MYXPM6021* *Advanced information. Subject to change without notice.
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MYXPM6021* *Advanced information. Subject to change without notice.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 56: Second Level Interrupt (continued) First-Level Interrupt Interrupt Name Register Source CHRG CHGRIRQ Charger Control Unit CHGR GPIOxPx GPIOIRQ GPIO GPIO VHDMIOCP VHDMIIRQ VHDMI VHDMIOCP MYXPM6021* Revision 1.1 - 10/21/14 Related Status Bit Description Triggered when an interrupt input from the external discrete charger is generated.
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MYXPM6021* *Advanced information. Subject to change without notice. 18 Power Button & Utility Button 18.1 Overview The system has two buttons that can be used together to trigger the system to power “on” or “off” in different ways. The main power button (PWRBTNIN_B) is an active-low input with an internal pull-up resistor to VSYS. The second button is the Utility button or user interface button (UI button, UIBTN_B).
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MYXPM6021* *Advanced information. Subject to change without notice. 18.3 PWRBTNIN_B Electrical Parameters Table 57: PWRBTNIN_B Pad Thresholds L->H Vth, high H->L Vth, low Vhyst [mV] [mV] [mV] Min 672.5 577.5 95 Typ 927.5 732.5 195 Max 1158.5 860.5 298 MYXPM6021* Revision 1.
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MYXPM6021* *Advanced information. Subject to change without notice. 19 Pulse Width Modulation Generation 19.1 Overview The PWM block is used to generate up to three PWM signals on three dedicated output pins. Mainly they are used to drive display backlight circuits. All the PWM outputs can be enabled on demand. 19.2 Functional Description Each of the PWM outputs are able to generate output frequencies from ~23.44 KHz down to ~183Hz in 128 steps.
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MYXPM6021* *Advanced information. Subject to change without notice. 20 Panel Control 20.1 Overview The MYXPM6021 provides two pins for display panel control, BACKLIGHT_EN to enable the display backlight circuit and PANEL_EN to enable the display panel electronics. The buffers driving these pins are slew-rate controlled push-pull output buffers similar to the GPIOs, each capable of high-voltage (3.3V) operation. MYXPM6021* Revision 1.
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MYXPM6021* *Advanced information. Subject to change without notice. 21 Debug Ports There are 2 debug ports, one for the SVID and another one for the I2C interface. 21.1 SVID Debug Port When in SVID debug mode, the PMIC SVID buffers connected to the SOC/CPU will be disabled and communication is redirected to an external bus master using a secondary set of pins. This will enable external control of the PMIC interface without any SOC/CPU bus contention.
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MYXPM6021* *Advanced information. Subject to change without notice. 21.2 I2C Debug port When in I2C debug mode, the MYXPM6021 I2C buffers connected to the SOC will be disabled and communication is redirected to an external bus master using a secondary set of pins. This will enable external control of the MYXPM6021 interface without any SOC/CPU bus contention. In addition, the debug channel enables a point to point bus topology with the external bus master, thereby providing clean signal integrity.
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MYXPM6021* *Advanced information. Subject to change without notice. 22 Package Information 22.1 MYXPM6021 Package Details 22.1.1 Pin Description, Pin Out Below is the pin description list of MYXPM6021. In the type column the following abbreviations are used: • PS, VSS Power Supply • DI, DO, DIO Digital Input, Digital Output, Digital Input/Output • AI, AO, AIO Analog Input, Analog Output, Analog Input/Output • OD Open-Drain Output 22.1.
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MYXPM6021* *Advanced information. Subject to change without notice.
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MYXPM6021* *Advanced information. Subject to change without notice. Table 59: MYXPM6021 Ball Order (continued) Ball Name Type Description L9 V1P05S_GND VSS Ground L10 VDDQ_VTT_GND VSS Ground L11 VLP_GND VSS Ground L12 SYSTHERM1 AI System thermistor 1 input L13 V1P0SX_FB AI V1P0SX sense line L14 VBAT_SENSE AI Battery voltage sense input signal L15 VREF0P9 AO 0.
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MYXPM6021* *Advanced information. Subject to change without notice. 22.2 MYXPM6021 325 Pin FCBGA Package Map of ball allocations as seen from above the package. MYXPM6021* Revision 1.
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MYXPM6021* *Advanced information. Subject to change without notice. 22.3 Package Outline (325 pin, FCBGA 11x6mm, 0.4mm pitch ) Symbol MYXPM6021* Revision 1.1 - 10/21/14 Dimension in mm Dimension in inches Min Nom Max Min Nom Max A 0.89 0.99 1.09 0.035 0.039 0.043 A1 0.11 0.16 0.21 0.004 0.006 0.008 A2 0.78 0.83 0.88 0.031 0.033 0.035 c 0.27 0.30 0.33 0.011 0.012 0.013 D 10.93 11.00 11.07 0.430 0.433 0.436 E 5.93 6.00 6.07 0.233 0.236 0.239 D1 --- 9.
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MYXPM6021* *Advanced information. Subject to change without notice. Revision History Revision # History Release Date Status 1.0 Initial Release September 2014 Preliminary 1.1 Added ECN # October 20, 2014 Preliminary MYXPM6021* Revision 1.