Cost Effective Network Processor for TCP/IP with ARM7TDMI™ MLN7400 Evaluation Board Manual Version 0.20 December 31, 2003 MCS Logic Inc. Copyright © 2003 MCS LOGIC Limited.
EVB7400 Revision History Version V 0.10 Date December 30, 2003 Revision Description First Release User’s Manual V.0.10 2/36 Copyright © 2004 MCS LOGIC Limited.
EVB7400 User’s Manual V.0.10 3/36 Copyright © 2004 MCS LOGIC Limited.
EVB7400 Table of Contents CHAPTER 1 1.1 1.2 SYSTEM REQUIREMENTS ............................................................................................................................................ 6 BOARD COMPONENTS ................................................................................................................................................ 8 CHAPTER 2 2.1 2.2 2.3 2.4 BOARD CONFIGURATION...........................................................................................
EVB7400 List of Figures [ F IGU R E 1 ] EVB7400 BLOCK DIAGRAM....................................................................................................................... 6 [ F IGU R E 2 ] MEMORY MAP .......................................................................................................................................... 7 [ F IGU R E 3 ] BLOCK DIAGRAM (TOP VIEW) ..................................................................................................................
EVB7400 Chapter 1 Introduction EVB7400 is a MLN7400 evaluation board and MCS-uClinux training kit that is suitable for code development and exploration of MN7400 with MCS-uClinux. It includes much of the hardware and software required completing your application development. It supports various function related with network, communication such as IIC, SPI, UART, 10/100 Ethernet, multimedia module such as sound DAC, storage media such as NAND FLASH memory module.
EVB7400 ADDRESS MLN7400 MAP EVB7400 0x000_0000 ~ 0x0FF_FFFF ROM/Flash bank 0 (16Mbytes) FLASH(512KB) 0x100_0000 ~ 0x1FF_FFFF ROM/Flash bank 1 (16Mbytes) SRAM(128KB) 0x200_0000 ~ 0x2FF_FFFF ROM/Flash bank 2 (16Mbytes) FLASH(2MB) 0x300_0000 ~ 0x3FF_FFFF ROM/Flash bank 3 (16Mbytes) PCMCIA Card 0x400_0000 ~ 0x5FF_FFFF Cacheable SDRAM area (32Mbytes) SDRAM 64Mbits(8Mbytes) 0x600_0000 ~ 0x600_5FFF (Cacheable) 0x800_0000 ~ 0xEFF_FFFF (Non-Cacheable) 0xF00_0000 ~ 0xFFF_FFFF SFR Registers [ Fi g
EVB7400 1.2 Board Components The arrangement of major components on the board is shown in Figure 3. The major components include: [ Fi gu re 3 ] BLOCK DIAGRAM (TOP VIEW) User’s Manual V.0.10 8/36 Copyright © 2004 MCS LOGIC Limited.
EVB7400 A Flash ROM There is a socket(U9) which accept 512Kbyte size of 8 bit Flash Memory(AT29C010 ~ 40). This is for diaganostic program(includes all pheriperal device driver and TCP/IP protocol stack) and BIOS(MCS-uClinux Boot loader) program. User Flash memory(Selectable Boot ROM) A mounted 48 TSOP type flash(AM29LV160BB), U8, is mounted for saving MCS-uClinux image. It has 2Mbytes(1M x 16bits)size. If you want to use this for boot ROM, SW2 should be set to to X16 and U9 should be removed.
EVB7400 Four buttons(SW5, SW8, SW11, SW14) are connected to ADIN1(ADC channel 1). Three buttons(SW5, SW8, SW11, SW14) are connected to ADIN2(ADC channel 2). External Interrrupt Key There are two button to use external interrupts. Each button(S1,S2) is connected to External interrupt0 and 2. External Timer0 Clock Timer0 can be supplied by the external clock(ocsillator) User’s Manual V.0.10 10/36 Copyright © 2004 MCS LOGIC Limited.
EVB7400 Board Configuration Chapter 2 The EVB7400 is set with default configuration. You can use the board with the defualt settings direclty. However, you can also change the settings according to your nedds. 2.1 Endian Selection (SW1) Status BIG Description BIG Endian LITTLE BIG Little Endian LITTLE 2.2 Boot ROM and ROM Bank0 length Selection (SW2) Status X8 Description ROM BANK0 Size is 8 bits.
EVB7400 2.
EVB7400 Chapter 3 3.1 Setup EVB7400 Environments Ethernet 10/100 BASE-T Connector Same connector and pin for both 10Base-T and 100 Base-Tx < At the network interface card/hubs > < At the cables > RJ45 female connetor at the network interface cards and hubs RJ45 male connector at the cable Pin 1 2 3 4 5 6 7 8 Name TX+ TXRX+ N/C N/C RXN/C N/C Descriptions Tranmit Data+ Tranmit DataReceive Data+ Not Connected Not Connected Receive DataNot Connected Not Connected NOTE : TX & RX are swapped on hub 3.
EVB7400 [ Fi gu re 4 ] UTP CABLE CONNECTION User’s Manual V.0.10 14/36 Copyright © 2004 MCS LOGIC Limited.
EVB7400 Chapter 4 4.1 Connection Configurations for Debug Console Configuration the Hyper Terminal To configure the Hyper Terminal, which is a Windows utility program for serial communications, refer to following steps: 1. 2. 3. Run the Hyper Terminal program -. Window 95/98/2000/XP start tool bar -> Program -> Accessories -> Hyper Terminal Group -> Double click Hyperterm.exe -> Enter a connection name -> Select a icon -> Click OK. Select COM Port to communicate with EVB7400 board. -.
EVB7400 [ Fi gu re 6 ] CHOOSE SETTING PAGE 6. 7. 4.2 Re-connect Hyper Terminal to run at new properties Disconnect : Call -> Disconnect Connect: Call -> Call Power-On Reset or push the reset button on EVB7400 board Now, the diagnostic program menu is showed on the Hyper Terminal Downloading Binary Image and Flash Write 4.2.1 Downloading Binary Image You can download a binary image file through the serial cable to target without an emulator. 1.
EVB7400 2. Type “8” at Flash Program Menu and type address to download. User’s Manual V.0.10 17/36 Copyright © 2004 MCS LOGIC Limited.
EVB7400 3. select the Send File from the Transfer menu File Name : Select the file name, which you want too download. Protocol : Select the Xmodem or 1K Xmodem. 4. Click Ok. Then, the file that you selected will be downloaded. User’s Manual V.0.10 18/36 Copyright © 2004 MCS LOGIC Limited.
EVB7400 4.2.2 Flash Write You can write downloaded binary image at User flash memory(AM29LV160BB, U8). Type “2” to write an executable binary file at User Flash memory. Then, you can execute your image by changing Boot Rom selection switch(SW2) to X16(default is X8). User’s Manual V.0.10 19/36 Copyright © 2004 MCS LOGIC Limited.
EVB7400 Chapter 5 5.1 Opennice32 Installation OPENice32 The OPENice32 can also be connected with the EVB7400 as a debugging system for software applications development. OPENice32 is a JTAG-based, nonintrusive, debugging system for ARM-based controllers or processors. JTAG provides the interface between a debugger and the ARM-based controller development board.
EVB7400 EVB7400 1.0 Schemetic and BOM Chapter 6 6.1 EVB7400 BOM No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PART NO MLN7400 MLN7400P AT24C256 AT25040 DS1629 K6R1016V1D K4S641632 AM29LV160BB AT29C040A AC101L H1102 MAX3232 74LVC14 74LV08 AMS1086 MAX4468EKA CS4340 K9F2808-YCB0 Xtal_osc 10MHz GEOMETRY 144LQFP 128TQFP 8 SOIC 8 SOIC 8 SOIC 44TSOP 54TSOP 48TSOP 32DIP 48 TQFP 8pin SOT23 16 SOIC 48 TSOP Half COUNT 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 20 Xtal_osc 25MHz Half 1 21 Crystal 32.
EVB7400 38 39 40 DB9 FEMAIL DB9 MAIL HEADER 13X2 5 1 4 41 42 43 44 HEADER 24X2 HEADER 4X2 HEADER 6X2 HEADER 1 1 1 1 7 UART0~4 HUART Option DATA, MII, ADDRESS, MEMORY GPIO heaser IIC & SPI HUART header Test Pin 45 46 Beads(100Mhz) 0 2012 0603(1608) 1 68 L R 47 48 0 33 1206(3216) 0603(1608) 4 12 R R 59 50 51 52 53 54 55 56 57 58 49.
EVB7400 65 66 67 68 100K 1M 0.01uF_2kV 0.01uF 0603(1608) 0603(1608) DIP 0603(1608) 3 1 1 9 R R 69 0.1uF 0603(1608) 65 C 70 1uF 0603(1608) 6 C 71 72 73 74 75 76 20pF 22pF 27pF 47pF 100pF 330pF 0603(1608) 0603(1608) 0603(1608) 0603(1608) 0603(1608) 0603(1608) 2 2 1 1 1 12 C C C C C C 77 78 820pF 1uF 0603(1608) SMD A(3216) 1 17 C T/C 79 80 81 2.2uF 3.
EVB7400 6.2 EVB7400 Schematic User’s Manual V.0.10 24/36 Copyright © 2004 MCS LOGIC Limited.
1 2 3 4 5 6 7 A A B B MLN7400 Evaluation Board C C D D E DESIGN CUSTOMER MCS LOGIC CHECK-1 E REV. MLN7400EV CHECK-2 DATE UPDATE 2003.11.
1 2 4 3 VCC_33 TDO TDI TCK TMS 10MHz X2 XO 1 C14 20pF 2 C184 NC VCC GND OUT 4 R5 VCC_33A GROUND A GROUND 33 XI MDIO MDC MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0 MII_RXDV MII_RXCLK MII_RXERR NRESET GROUND GROUND GROUND SYSCLK 0.1uF 3 10MHZ 20pF VCC_33 ADIN0 ADIN1 ADIN2 ADIN3 VCC_33 C1 C2 C3 C4 C5 C6 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.
1 2 3 4 5 6 7 97 RX_ERR VDD33_04 AD09 GP09_NBE(1) 94 93 92 91 90 89 88 87 86 B VCC_33 80 79 78 77 76 75 74 73 72 71 70 69 68 67 0.1uF 0.1uF C27 C28 1 0.1uF C26 TC5 0.1uF C25 47uF 0.1uF C24 2 0.1uF C23 1 0.1uF C22 TC4 0.1uF C21 47uF 0.1uF C GROUND 66 65 GP09_NBE1 MLN7400P_128TQFP D GROUND E ADDR(20:0) DESIGN CUSTOMER MCS LOGIC GP07_CURXD4 GP06_CUTXD4 GP05_CURXD3 GP04_CUTXD3 GP03_CURXD2 GP02_CUTXD2 GP01_CURXD1 GP00_CUTXD1 E 2 0.1uF C20 81 C19 82 0.
1 2 3 4 5 OPTIONAL Do not install Install to use NAND Flash Only use when CPU is MLN7400P and need to use DAC A GP25_IOWR* GP24_IORD* GP23_CE2* GP22_REG* GP42_DDATA GP41_DMCK GP40_DBCK GP39_DLRCK R8 0 R9 0 R10 0 R11 0 R27 0 R28 0 R29 0 R30 0 DDATA DMCK DBCK DLRCK GP38_TOUT3 GP37_TOUT2 GP36_EXINT3 GP34_HUARTNDTR4 GP33_HUARTNDSR4 GP32_HUARTNRTS4 GP31_HUARTNCTS4 GP30_HUARTNDCD4 MLN7400P DAC I/F DDATA DMCK DBCK DLRCK R31 0 R32 0 R33 0 R34 0 R35 0 R36 0 R37 0 R200 0
2 1 A 3 4 5 IIC EEPROM 6 7 A SPI EEPROM VCC_33 U3 3 4 VCC A1 WP A2 SCL GND SDA B 1 SPI_SS* VCC_33 8 2 SPI_MISO 7 6 SCL 5 C186 3 0.1uF 4 SDA S524A40X10 VCC_33 U4 2K 2 A0 2K 1 VCC_33 R67 R66 VCC_33 *CS SO VCC *HOLD *WP SCK GND SI 8 C187 7 6 0.1uF SPI_CLK 5 SPI_MOSI GROUND AT25040 B GROUND GROUND GROUND GROUND External Interrupt Test VCC_33 VCC_33 RTC R68 4.
1 2 3 4 5 6 7 VCC_33 A NC1 CS* NC2 WE* NC3 OE* VCC1 39 NBE0_LB NBE1_UB 40 VCC2 LB* UB* VSS1 VSS2 22 VCC_33 38 SDCLK SDCKE 37 VDDQ4 15 1 14 53 TC6 9 43 VDDQ3 3 VDDQ1 VDDQ2 27 49 13 51 CLK B CKE 23 28 33 GROUND 12 19 SDCSN SDRASN SDCASN SDWEN ADDR(15) ADDR(16) 11 34 18 17 16 R73 0 15 R74 0 39 CS* NC 40 RAS* CAS* WE* GROUND DQML DQMH 28 K6R1016V1D_SRAM BANK2 14 DQ15 12 50 2 15 DQ14 11 10uF_16V 38 A14 47 48 VCC_33 0.
2 1 3 4 6 5 7 A A VCC_33 VCC_33 VCC_33 X1_OE X2_OUT NC_GND R84 NC_VDD 0.1uF XTAL_OSC_25MHZ 75 GROUND C49 27pF 3 32 4 31 5 30 6 29 7 28 8 27 TDC TCMT TXDN TXN NC1 NC3 NC2 NC4 RDP RXP RDC RCMT RDN RXN 16 1 9 15 2 10 14 3 11 13 4 12 12 5 11 6 13 10 7 14 9 8 H1102 26 R93 R94 500 J1 TXP TXDP VCC_25 500 C51 R92 49.9 1uF_1608 R91 49.9 C50 R90 49.9 0.1uF R89 49.
1 3 2 4 5 6 7 UART0 P1 1 6 2 VCC_33 7 3 A A 8 U12 R1I 4 1 5 T2O R2O R2I C2+ V- C2- GND TC11 2 1uF 1 14 DB9_FEMALE 2 13 GROUND 7 UART1 P2 8 1uF 6 TC14 2 1 1 6 C70 2 T1O T2I 9 TC13 V+ T1I R1O 10 1uF C1- 2 7 15 MAX3232 3 330pF 12 5 C69 11 9 16 330pF 3 CUTXD0 CURXD0 CUTXD1 CURXD1 VCC C68 C1+ 330pF 1 1 C67 TC12 2 330pF 1uF 4 8 4 9 GROUND 5 B B DB9_FEMALE GROUND GROUND UART2 P3 1 6 2 VCC_33 7 3 8 U13 4 1 5 T2O R2O R2I C
2 1 3 5 4 6 7 VCC_33 ADDR(11:0) 66 11 37 12 38 13 39 14 40 15 41 0 58 7 PCMCIA_CE1* PCMCIA_CE2* 42 9 NEOE NEWE PCMCIA_IORD* PCMCIA_IOWR* 15 44 45 61 PCMCIA_REG* 67 36 59 PCMCIA_WAIT* PCMCIA_IRQ* D 16 57 43 62 63 60 33 D9 A23 D10 A24 D11 A25 50 53 54 55 56 D12 D13 R142 10 A22 4.7K 65 D8 49 R141 9 A21 4.7K 64 D7 48 R140 8 A20 4.7K 6 D6 47 R139 7 A19 4.7K 5 A18 D5 46 R138 6 A17 D4 B 19 4.7K 4 D3 20 R137 3 5 A16 4.
1 2 4 3 5 RESET SYSTEM 6 GPIO LED VCC_33 VCC_33 NRESET A GROUND R147 R146 330 4 VCC_33 330 74LVC14 3 2 330 1 GROUND SW_RESET LED LED VCC_33 B U16 14 1 R150 B D7 2 D6 S3 D5 14 Pin : VCC_33 7 Pin : Ground 2 1 LED VCC_33 10uF LED TC25 D4 1 U15 74LVC14 10K 1 10K U15 R145 R144 1N4148 VCC_33 0.1uF 0.1uF D3 VCC_33 C82 R149 2 R148 RESET C81 VCC_33 330 VCC_33 VCC_33 A 7 3 NTRST 2 GROUND LED0* 74LV08 LED1* 14 Pin : VCC_33 7 Pin : Ground 4.
1 2 4 3 DATA(15:0) 5 6 7 VCC_33 VCC_33 JP2 A SDA SCL JP3 14 12 10 8 6 4 2 0 25 26 23 24 21 22 19 20 17 18 15 16 13 14 11 12 9 10 7 8 5 6 3 4 1 2 1 2 3 4 5 6 7 8 A SPI_CLK SPI_MOSI SPI_MISO SPI_SS* VCC_33 HEADER2X4 15 GROUND 13 IIC & SPI HEADER 11 9 7 5 JP5 1 GP06_CUTXD4 GP07_CURXD4 GP30_HUARTNDCD4 3 1 VCC_33 2 3 4 5 6 7 GP31_HUARTNCTS4 GP32_HUARTNRTS4 GP33_HUARTNDSR4 GP34_HUARTNDTR4 8 9 10 11 12 HEADER2X6 HEADER2X13 B B GROUND GROUND
1 2 VCC_33A 3 5 4 6 7 VCC_33A VCC_33A A A 1K R153 1K R154 ADIN0 1 SW5 2 TACT_SW TACT_SW PLAY PGM 1 SW8 2 TACT_SW STOP MENU SW10 1 2 TACT_SW VOL_UP SW11 2 1 TACT_SW B SW12 2 TACT_SW VOL_DN AGND R161 R162 560 ESP 560 SKIP+ SW13 SW9 R159 2 TACT_SW 1 1 390 TACT_SW R158 1 R157 270 2 B 2 TACT_SW R156 R155 SW7 SW6 EQ 390 1 1 270 2 ADIN2 390 SW4 ADIN1 270 1 1K R160 R152 2 1 TACT_SW SW14 VCC_33A 2 TACT_SW C188 ENTER 820 SKIP-
3 5 4 TC35 A 3.3uF R172 7 560 A 2 R173 1uF_1608 10K 1 6 C90 2 1 AGND J6 B B TC36 R174 560 AOUTR 3 AOUTL 2 C91 1uF_1608 R175 AOUTR_S 0 AOUTL_S VCC_33A 1 LINE_OUT_JACK AGND C R176 C 3.3uF 2 10K 1 U20 DIF0 VQ DEM0 FILT+ 11 10 D 9 E 2 R178 1uF 100 1 CS4340 C92 REF_GND 0.1uF DIF1 12 TC37 AOUTR 1uF MCLK 13 1 8 AGND 2 D LRCK 14 C93 7 VA 0.1uF 6 SCLK 15 TC38 5 AOUTL 1 4 MUTEC SDATA 2 3 RST* 1uF 2 AGND 16 C94 1 0.
1 3 2 4 5 6 7 A A VCC_33 NAND_Flash U21 3 4 R179 B 5 6 NFPIN6 7 NFRBN 8 NFRDN NFCEN 100pF VCC_33 9 10 11 C95 12 14 0.
