Datasheet

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This is information on a product in full production.

January 2014 DocID8349 Rev 7 1/170

ST7LITE20F2 ST7LITE25F2

ST7LITE29F2

8-bit microcontroller with single voltage Flash memory, data

EEPROM, ADC, Timers, SPI

Datasheet - production data

Features

• Memories

– 8 Kbytes single voltage Flash Program

memory with Read-out protection

– In-circuit programming and in-application

programming (ICP and IAP)

– 10K write/erase cycles guaranteed

– Data retention: 20 years at 55 °C

– Temperature ranges:

– -40 °C to +85 °C

– -40 °C to +105 °C

– 384 bytes RAM

• Clock, reset and supply management

– Enhanced reset system

– Enhanced low voltage supervisor (LVD) for

main supply and an auxiliary voltage

detector (AVD) with interrupt capability for

implementing safe power-down procedures

– Clock sources: internal 1% RC oscillator,

crystal/ceramic resonator or external clock

– Internal 32-MHz input clock for auto-reload

timer

– Optional x4 or x8 PLL for 4 or 8 MHz

internal clock

– Five power saving modes: Halt, Active-halt,

Wait and Slow, Auto-wakeup from Halt

• I/O ports

– Up to 15 multifunctional bidirectional I/O

lines

– 7 high sink outputs

• 4 timers

– Configurable watchdog timer

– Two 8-bit Lite timers with prescaler

– 1 real-time base and 1 input capture

– One 12-bit auto-reload timer with 4 PWM

outputs, input capture and output compare

functions

• 1 communication interface

– SPI synchronous serial interface.

• Interrupt management

– 10 interrupt vectors plus TRAP and RESET

– 15 external interrupt lines (on 4 vectors)

• A/D converter

– 7 input channels

– Fixed gain op-amp

– 13-bit resolution for 0 to 430 mV

(@ 5 V V

)

– 10-bit resolution for 430 mV to 5 V (@ 5 V

)

• Instruction set

– 8-bit data manipulation

– 63 basic instructions with illegal opcode

detection

– 17 main addressing modes

– 8 x 8 unsigned multiply instructions

• Development tools

– Full hardware/software development

package

– DM (debug module)

DIP20

SO20 300”

www.st.com

Summary of content (170 pages)

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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, Timers, SPI Datasheet - production data Features • Memories – 8 Kbytes single voltage Flash Program memory with Read-out protection – In-circuit programming and in-application programming (ICP and IAP) – 10K write/erase cycles guaranteed – Data retention: 20 years at 55 °C – Temperature ranges: – -40 °C to +85 °C – -40 °C to +105 °C – 384 bytes RAM DIP20 SO20 300” • 1 communication interface – S
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Contents ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 6 2/170 4.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 7 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1 Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2 Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.4 Multi-oscillator (MO) . . . . . . . . . . . . . . . .
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Contents 11 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 11.5 12 11.4.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.4.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.4.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 13.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.5.1 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 131 13.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13.7 EMC characteristics . . . . . . . . . . .
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 17 Contents Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of tables ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96.
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List of tables ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 99. STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Table 100. ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Table 101. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41.
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List of figures Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 1 Description Description ST7LITE20F2, ST7LITE25F2 and ST7LITE29F2 are referred to as ST7LITE2. The ST7LITE2 is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7LITE2 features FLASH memory with byte-by-byte In-Circuit Programming (ICP) and In-Application Programming (IAP) capability.
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Description ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Figure 1. General block diagram PLL 8 MHz -> 32 MHz Int. 1% RC 1MHz PLL x 8 or PLL X4 12-bit Auto-reload Timer 2 CLKIN 8-bit Lite timer 2 /2 OSC1 OSC2 Ext.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 2 Pin description Pin description Figure 2.
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Pin description ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Port and control configuration: • Input: – • float = floating, wpu = weak pull-up, int = interrupt, ana = analog Output: – OD = open drain – PP = push-pull The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state. Table 2. Device pin description Pin No.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Pin description Table 2. Device pin description (continued) Pin No.
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Register & memory map 3 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Register & memory map As shown in Figure 4, the MCU is able of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 384 bytes of RAM, 256 bytes of data EEPROM and 8 Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 180h to 1FFh. The highest address bytes contain the user reset and interrupt vectors.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Register & memory map Table 3.
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Register & memory map ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 3.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Flash program memory 4 Flash program memory 4.1 Introduction The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using in-circuit programming or in-application programming.
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Flash program memory ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Depending on the ICP driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In-application programming (IAP) This mode uses an IAP driver program previously programmed in Sector 0 by the user (in ICP mode). This mode is fully controlled by user software.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Caution: Flash program memory During normal operation the ICCCLK pin must be pulled up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up. Figure 5.
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Flash program memory ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Write/erase protection is enabled through the FMP_W bit in the option byte. 4.6 Related documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 5 Data EEPROM 5.1 Introduction Data EEPROM The Electrically Erasable Programmable Read Only Memory can be used as a non-volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 5.
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Data EEPROM ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Read operation (E2LAT=0) The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared. On this device, Data EEPROM can also be used to execute machine code. Take care not to write to the Data EEPROM while executing from it. This would result in an unexpected code being executed. Write operation (E2LAT=1) To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared).
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Data EEPROM Table 4. Row definition ⇓ Row / Byte ⇒ 0 1 2 3 ... 30 31 Physical address 0 00h...1Fh 1 20h...3Fh ... N Nx20h...Nx20h+1Fh Figure 8.
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Data EEPROM 5.6 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Data EEPROM Read-out protection The Read-out protection is enabled through an option bit (see Section 15.1: Option bytes). When this option is selected, the programs and data stored in the EEPROM memory are protected against Read-out (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the Option Byte, the entire Program memory and EEPROM is first automatically erased.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Data EEPROM Table 5. DATA EEPROM register map and reset values Address (Hex.
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Central processing unit ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 6 Central processing unit 6.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 6.2 6.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Central processing unit Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation.
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Central processing unit ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. • Bit 2 = N Negative This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null 1: The result of the last operation is negative (i.e.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Central processing unit pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 11: • When an interrupt is received, the SP is decremented and the context is pushed on the stack. • On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area. Figure 11.
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Supply, reset and clock management 7 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Supply, reset and clock management The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. Main features • 7.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Note: Supply, reset and clock management See Section 13: Electrical characteristics for more information on the frequency and accuracy of the RC oscillator. To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. These two bytes are systematically programmed by ST, including on FASTROM devices.
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Supply, reset and clock management ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 for TA = -40 to +85°C) @ VDD = 4.5 to 5.5 V). Refer to Section 7.6.4: Register description for a description of the LOCKED bit in the SICSR register. 7.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Supply, reset and clock management Figure 13.
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Supply, reset and clock management Note: ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 When the Multi-oscillator is not used, PB4 is selected by default as external clock. Crystal/ceramic oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to Section 15.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Supply, reset and clock management 7.5 Reset sequence manager (RSM) 7.5.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 15: Reset block diagram: Note: • External RESET source pulse • Internal LVD RESET (low voltage detection) • Internal WATCHDOG RESET A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to Section 12.2.1: Illegal opcode reset for further details.
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Supply, reset and clock management 7.5.2 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. Note: See Section 13: Electrical characteristics for more details.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 7.5.5 Supply, reset and clock management Internal watchdog RESET The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 16. Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 16.
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Supply, reset and clock management ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 The LVD Reset circuitry generates a reset when VDD is below: • VIT+(LVD)when VDD is rising • VIT-(LVD) when VDD is falling. The LVD function is illustrated in Figure 17. The voltage threshold can be configured by option byte to be low, medium or high. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD), the MCU can only be in two modes: • under full software control • in static safe reset.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Supply, reset and clock management Figure 18. Reset and supply management block diagram Watchdog STATUS FLAG timer (WDG) System integrity management Reset sequence RESET AVD interrupt request manager SICSR (RSM) 0 0 0 WDGRF LOCKED LVDRF AVDF AVDIE Low voltage VSS detector VDD (LVD) Auxiliary voltage detector (AVD) 7.6.
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Supply, reset and clock management ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Figure 19. Using the AVD to monitor VDD VDD Early warning interrupt (Power has dropped, MCU not not yet in reset) Vhyst VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD) AVDF bit 0 1 RESET 1 0 AVD interrupt request if AVDIE bit = 1 Interrupt cleared by reset Interrupt cleared by hardware LVD RESET 7.6.3 Low power modes Table 9. Effect of low power modes on SI Mode Description WAIT No effect on SI.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 7.6.4 Supply, reset and clock management Register description System integrity (SI) control/status register (SICSR) Read / Write Reset Value: 0000 0xx0 (0xh) 7 0 0 0 0 WDGRF LOCKED LVDRF AVDF AVDIE • Bit 7:5 = Reserved, must be kept cleared. • Bit 4 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generated by the Watchdog peripheral.
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Supply, reset and clock management Note: 46/170 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 8 Interrupts Interrupts The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 20: Interrupt processing flowchart. The maskable interrupts must be enabled by clearing the I bit in order to be serviced.
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Interrupts ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. Note: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Interrupts Table 12. Interrupt mapping No.
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Interrupts ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 External interrupt control register (EICR) Read/Write Reset Value: 0000 0000 (00h) 7 IS31 Note: 0 IS30 IS21 IS20 IS11 IS10 IS01 IS00 • Bit 7:6 = IS3[1:0] ei3 sensitivity These bits define the interrupt sensitivity for ei3 (Port B0) according to Table 13: Interrupt sensitivity bits. • Bit 5:4 = IS2[1:0] ei2 sensitivity These bits define the interrupt sensitivity for ei2 (Port B3) according to Table 13: Interrupt sensitivity bits.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Interrupts External interrupt selection register (EISR) Read/Write Reset Value: 0000 1100 (0Ch) 7 0 IS31 • IS30 IS21 IS20 IS11 IS10 IS01 IS00 Bits 7:6 = ei3[1:0] ei3 pin selection These bits are written by software. They select the Port B I/O pin used for the ei3 external interrupt according to the table below. Table 14. External interrupt I/O pin ei3[1:0] selection ei31 ei30 I/O pin 0 0 PB0 (1) 0 1 PB1 1 0 PB2 1.
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Interrupts ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 16. External interrupt I/O pin ei1[1:0] selection ei11 ei10 I/O pin 0 0 PA4 0 1 PA5 1 0 PA6 1 1 PA7(1) 1. Reset state • Bits 1:0 = ei0[1:0] ei0 pin selection These bits are written by software. They select the Port A I/O pin used for the ei0 external interrupt according to the table below. Table 17. External interrupt I/O pin ei0[1:0] selection ei01 ei00 I/O pin 0 0 PA0 (1) 0 1 PA1 1 0 PA2 1 1 PA3 1.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Power saving modes 9 Power saving modes 9.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, five main power saving modes are implemented in the ST7 (see Figure 21): • Slow • Wait (and Slow-Wait) • Active Halt • Auto Wake up From Halt (AWUF) • Halt After a RESET the normal operating mode is selected by default (Run mode).
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Power saving modes ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 SLOW mode is controlled by the SMS bit in the MCCSR register which enables or disables SLOW mode. In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked at this lower frequency. Note: SLOW-WAIT mode is activated when entering WAIT mode while the device is already in SLOW mode. Figure 22. SLOW mode clock transition fOSC/32 fOSC fCPU fOSC SMS Normal Run mode request 9.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Power saving modes Figure 23. WAIT mode flowchart WFI INSTRUCTION OSCILLATOR PERIPHERALS CPU I BIT ON ON OFF 0 N RESET Y N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I BIT ON OFF ON 0 256 or 4096 CPU clock cycle delay OSCILLATOR PERIPHERALS CPU I BIT ON ON ON X(1) Fetch reset vector or service interrupt 1. Before servicing an interrupt, the CC register is pushed on the stack.
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Power saving modes ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see Section 15.1: Option bytes for more details). Figure 24.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Power saving modes Figure 25. HALT mode flowchart HALT instruction (ACTIVE-HALT disabled) (AWUCSR.AWUEN=0) Watchdog ENABLE WDGHALT (1) DISABLE 0 1 Watchdog reset Oscillator Peripherals (2) CPU I bit N N OFF OFF OFF 0 Reset Y Interrupt (3) Y Oscillator Peripherals CPU I bit ON OFF ON X 4) 256 or 4096 CPU clock cycle delay(5) Oscillator Peripherals CPU I bit ON ON ON X 4) Fetch reset vector or service interrupt 1. WDGHALT is an option bit (see Section 15.
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Power saving modes ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. 9.5 • For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. • The opcode for the HALT instruction is 0x8E.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Note: Power saving modes As soon as ACTIVE-HALT is enabled, executing a HALT instruction while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode. Figure 26. ACTIVE-HALT timing overview Run Activehalt 256 or 4096 CPU cycle delay (1) HALT instruction [ACTIVE-HALT enabled] Reset or interrupt Run Fetch vector 1.
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Power saving modes 9.6 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Auto-wakeup from HALT mode Auto Wake Up From Halt (AWUF) mode is similar to Halt mode with the addition of a specific internal RC oscillator for wake-up (Auto Wake Up from Halt Oscillator). Compared to ACTIVE-HALT mode, AWUF has lower power consumption (the main clock is not kept running, but there is no accurate realtime clock available. It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Power saving modes Figure 29. AWUF halt timing diagram tAWU Run mode HALT mode 256 or 4096 tCPU Run mode fCPU fAWU_RC Clear by software AWUF interrupt Figure 30. AWUF mode flowchart HALT instruction (Active-halt disabled) (AWUCSR.
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Power saving modes ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 interrupt). Refer to Table 12: Interrupt mapping for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. 5. If the PLL is enabled by option byte, it outputs the clock after an additional delay of tSTARTUP (see Figure 12: PLL output frequency timing diagram). 9.6.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Power saving modes AWUF prescaler register list (AWUPR) Read / Write Reset value: 1111 1111 (FFh) 7 0 AWUPR7 • AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0 Bits 7:0= AWUPR[7:0] Auto-wakeup prescaler These 8 bits define the AWUPR dividing factor (as explained in Table 19: AWU prescaler below): Table 19.
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I/O ports ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 10 I/O ports 10.1 Introduction The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may have several other functions. These functions can include external interrupt, alternate signal input/output for on chip peripherals or analog input. 10.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 I/O ports Spurious interrupts When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disabled by the OR register.
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I/O ports 10.2.3 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Alternate functions Many ST7s I/Os have one or more alternate functions. These may include output signals from, or input signals to, on-chip peripherals. The Device Pin Description table describes which peripheral signals can be input/output to which ports. A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the on-chip peripheral as an output (enable bit in the peripheral’s control register).
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Note: I/O ports Refer to the Section 10.7: Device-specific I/O port configuration for device specific information. Table 22. I/O port mode options(1) Diodes Configuration mode Pull-up P-buffer to VDD Input Floating with/without interrupt Off Pull-up with/without interrupt On Push-pull Output Off True open drain On On Off Open drain (logic level) to VSS On Off NI NI(2) NI 1.
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I/O ports ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 23. I/O configurations (continued) I/O port Hardware configuration VDD NOTE 3 DR register access RPU Open-drain output(2) PAD DR register VDD R/W Databus DR register access NOTE 3 RPU Push-pull output(3) DR register PAD Alternate Enable bit R/W Databus Alternate output From on-chip peripheral 1.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 I/O ports Figure 32. Interrupt I/O port state transitions 01 00 10 11 INPUT floating/pull-up interrupt INPUT floating (reset state) OUTPUT open-drain OUTPUT push-pull XX 10.4 = DDR, OR Unused I/O pins Unused I/O pins must be connected to fixed voltage levels. Refer to Section 13.8: I/O port pin characteristics. 10.5 Low power modes Table 24. Effect of low power modes on I/O ports 10.6 Mode Description WAIT No effect on I/O ports.
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I/O ports ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 26. Ports PA7:0, PB6:0 (continued) Mode DDR OR Open drain output 1 0 Push-pull output 1 1 Table 27.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 I/O ports Table 30. I/O port register map and reset values (continued) Address (Hex.
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On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 11 On-chip peripherals 11.1 Watchdog timer (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is freerunning: it counts down even if the watchdog is disabled.
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On-chip peripherals 11.1.6 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Register description Control register (CR) Read / Write Reset value: 0111 1111 (7F h) 7 0 WDGA • Note: T6 T5 T4 T3 T2 T1 T0 Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled This bit is not used if the hardware watchdog option is enabled by option byte.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 11.2.2 On-chip peripherals Main features • 12-bit upcounter with 12-bit autoreload register (ATR) • Maskable overflow interrupt • Generation of four independent PWMx signals • Frequency 2 kHz-4 MHz (@ 8 MHz fCPU) • – programmable duty-cycles – polarity control – programmable output modes – maskable Compare interrupt Input capture – 12-bit input capture register (ATICR) – triggered by rising and falling edges – maskable IC interrupt. Figure 34.
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On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 PWM frequency and duty cycle The four PWM signals have the same frequency (fPWM) which is controlled by the counter period and the ATR register value.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals Figure 36. PWM function 4095 Counter Duty cycle register (DCRx) Auto-reload register (ATR) PWMx output 000 t With OE=1 and OPx=0 With OE=1 and OPx=1 Figure 37.
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On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Software can set the BA bit to activate the break function without using the BREAK pin. • • When the break function is activated (BA bit =1): – the break pattern (PWM[3:0] bits in the BREAKCR) is forced directly on the PWMx output pins (after the inverter), – the 12-bit PWM counter is set to its reset value, – the ARR, DCRx and the corresponding shadow registers are set to their reset values, – the PWMCR register is reset.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals Figure 39. Input capture timing diagram fCOUNTER COUNTER 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah ATIC PIN INTERRUPT ATICR READ INTERRUPT ICF FLAG ICR REGISTER xxh 09h 04h t 11.2.4 Low power modes Table 33. Effect of low power modes Mode 11.2.
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On-chip peripherals 11.2.6 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Register description Timer control status register (ATCSR) Read / Write Reset value: 0x00 0000 (x0h) 7 0 0 ICF ICIE CK1 CK0 OVF OVFIE CMPIE • Bit 7 = Reserved. • Bit 6 = ICF Input capture flag This bit is set by hardware and cleared by software by reading the ATICR register (a read access to ATICRH or ATICRL will clear this flag). Writing to this bit does not change the bit value.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals 0: CMPF interrupt disabled. 1: CMPF interrupt enabled. Counter register high (CNTRH) Read only Reset value: 0000 0000 (000h) 15 0 8 0 0 0 CNTR11 CNTR10 CNTR9 CNTR8 Counter register low (CNTRL) Read only Reset value: 0000 0000 (000h) 7 CNTR7 0 CNTR6 CNTR5 CNTR4 CNTR3 CNTR2 CNTR1 CNTR0 • Bits 15:12 = Reserved • Bits 11:0 = CNTR[11:0] Counter value This 12-bit register is read by software and cleared by hardware after a reset.
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On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Autoreload register (ATRL) Read / Write Reset Value: 0000 0000 (00h) 7 ATR7 0 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 i PWM output control register (PWMCR) Read/Write Reset Value: 0000 0000 (00h) 7 0 • 0 OE3 0 OE2 0 OE1 0 OE0 Bits 7:0 = OE[3:0] PWMx output enable These bits are set and cleared by software and cleared by hardware after a reset. 0: PWM mode disabled.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals Break control register (BREAKCR) Read/Write Reset Value: 0000 0000 (00h) 7 0 0 0 BA BPEN PWM3 PWM2 PWM1 PWM0 • Bits 7:6 = Reserved. Forced by hardware to 0. • Bit 5 = BA Break Active This bit is read/write by software, cleared by hardware after reset and set by hardware when the BREAK pin is low. It activates/deactivates the Break function.
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On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Input capture register high (ATICRH) Read only Reset Value: 0000 0000 (00h) 15 8 0 0 0 0 ICR11 ICR10 ICR9 ICR8 Input capture register low (ATICRL) Read only Reset Value: 0000 0000 (00h) 7 0 ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 • Bits 15:12 = Reserved. • Bits 11:0 = ICR[11:0] Input capture data. This is a 12-bit register which is readable by software and cleared by hardware after a reset.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals Table 36. Register map and reset values (continued) Address (Hex.
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On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 11.3 Lite timer 2 (LT2) 11.3.1 Introduction The Lite timer can be used for general-purpose timing functions. It is based on two freerunning 8-bit upcounters, an 8-bit input capture register. 11.3.2 Main features • • Real-time clock – One 8-bit upcounter 1 ms or 2 ms timebase period (@ 8 MHz fOSC) – One 8-bit upcounter with autoreload and programmable timebase period from 4µs to 1.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 11.3.3 On-chip peripherals Functional description Timebase counter 1 The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from 0 at a frequency of fOSC/32. An overflow event occurs when the counter rolls over from F9h to 00h. If fOSC = 8 MHz, then the time period between two counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the LTCSR1 register.
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On-chip peripherals 11.3.4 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Low power modes Table 37. Effect of low power modes on Lite timer Mode 11.3.5 Description SLOW No effect on Lite timer (this peripheral is driven directly by fOSC/32) WAIT No effect on Lite timer ACTIVE-HALT No effect on Lite timer HALT Lite timer stops counting Interrupts Table 38.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals 1: A Counter 2 overflow has occurred. Lite timer autoreload register (LTARR) Read / Write Reset Value: 0000 0000 (00h) 7 AR7 • 0 AR7 AR7 AR7 AR3 AR2 AR1 AR0 Bits 7:0 = AR[7:0] Counter 2 Reload Value These bits register is read/write by software. The LTARR value is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs.
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On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 0: Timebase period = tOSC * 8000 (1 ms @ 8 MHz) 1: Timebase period = tOSC * 16000 (2 ms @ 8 MHz) • Bit 4 = TB1IE Timebase interrupt enable This bit is set and cleared by software. 0: Timebase (TB1) interrupt disabled 1: Timebase (TB1) interrupt enabled • Bit 3 = TB1F Timebase interrupt flag This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals 11.4 Serial peripheral interface (SPI) 11.4.1 Introduction The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 11.4.
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On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Figure 42.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals Figure 43. Single master/ single slave application SLAVE MASTER MSBit LSBit 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR MSBit MISO MISO MOSI MOSI SCK SS LSBit 8-BIT SHIFT REGISTER SCK +5V SS Not used if SS is managed by software Slave select management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software.
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On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Figure 45. Hardware/software slave select management SSM bit SSI bit 1 SS external pin 0 SS internal Master mode operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register).
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Note: On-chip peripherals While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Slave mode operation In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. Write to the SPICSR register to perform the following actions: – Note: Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see Figure 46: Data clock timing diagram).
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On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Figure 46 shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. Figure 46.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals 1. The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set. 2. The SPE bit is reset. This blocks all output from the Device and disables the SPI peripheral. 3. The MSTR bit is reset, thus forcing the Device into slave mode. Clearing the MODF bit is done through a software sequence: Note: 1. A read access to the SPICSR register while the MODF bit is set. 2. A write to the SPICR register.
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On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Figure 47. Clearing the WCOL bit (write collision flag) software sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SPICSR RESULT 2nd Step Read SPIDR SPIF =0 WCOL=0 Clearing sequence before SPIF = 1 (during a data byte transfer) Read SPICSR 1st Step RESULT 2nd Step Read SPIDR WCOL=0 1.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals Figure 48. Single master / multiple slave configuration SS SCK Slave Device SS SCK Slave Device SS SCK Slave Device SS SCK Slave Device MOSI MISO MOSI MISO MOSI MISO MOSI MISO SCK Master Device 5V 11.4.6 Ports MOSI MISO SS Low power modes Table 40. WAIT and HALT mode description Mode Description WAIT No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. HALT SPI registers are frozen.
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On-chip peripherals 11.4.7 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Interrupts Table 41. Interrupt events Event flag Interrupt Event SPI end of transfer event SPIF Master mode fault event MODF Overrun error Enable control bit SPIE OVR Exit from WAIT Exit from HALT Yes Yes Yes No Yes No Note: The SPI interrupt events are connected to the same interrupt vector (see Section 8: Interrupts).
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals 1: Master mode. The function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed. • Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. • Note: Bit 2 = CPHA Clock Phase This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge.
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On-chip peripherals Note: 102/170 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. • Bit 6 = WCOL Write collision status (Read only) This bit is set by hardware when a write to the SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 47: Clearing the WCOL bit (write collision flag) software sequence).
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals Data I/O register (SPIDR) Read/Write Reset Value: Undefined 7 0 D7 D6 D5 D4 D3 D2 D1 D0 The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte. Note: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer.
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On-chip peripherals 11.5.2 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Main features • 10-bit conversion • Up to 7 channels with multiplexed input • Linear successive approximation • Data register (DR) which contains the results • Conversion complete status flag • On/off bit (to reduce consumption) The block diagram is shown in Figure 49. 11.5.3 Functional description Analog power supply VDDA and VSSA are the high and low level reference voltage pins.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals For example, if VDD = 5 V, then the ADC can convert voltages in the range 0 V to 430 mV with an ideal resolution of 0.6 mV (equivalent to 13-bit resolution with reference to a VSS to VDD range). Note: For more details, refer to Section 13: Electrical characteristics. The amplifier is switched on by the ADON bit in the ADCCSR register, so no additional startup time is required when the amplifier is selected by the AMPSEL bit.
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On-chip peripherals 11.5.4 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Low power modes Table 44. Low power modes effects Mode Description WAIT No effect on A/D Converter HALT A/D Converter disabled. After wakeup from HALT mode, the A/D Converter requires a stabilization time tSTAB (see Electrical Characteristics) before accurate conversions can be performed. Note: The A/D converter may be disabled by resetting the ADON bit.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals Table 45. Channel selection bits (continued) Channel pin(1) CH2 CH1 CH0 AIN3 0 1 1 AIN4 1 0 0 AIN5 1 0 1 AIN6 1 1 0 1. The number of channels is device dependent. Refer to Table DocID8349 Rev 7 2: Device pin description.
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On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Data register high (ADCDRH) Read only Reset value: xxxx xxxx (xxh) 7 D9 • 0 D8 D7 D6 D5 D4 D3 D2 Bits 7:0 = D[9:2] MSB of analog converted value. AMP control/data register low (ADCDRL) Read / Write Reset Value: 0000 00xx (0xh) 7 0 Note: 0 0 0 AMP CAL SLOW AMPSEL D1 D0 • Bits 7:5 = Reserved. Forced by hardware to 0. • Bit 4 = AMPCAL Amplifier Calibration Bit This bit is set and cleared by software.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals Table 47. ADC register map and reset values Address (Hex.
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Instruction set ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 12 Instruction set 12.1 ST7 addressing modes The ST7 Core features 17 different addressing modes which can be classified in seven main groups: : Table 48.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Instruction set Table 49. ST7 addressing mode overview Mode Indexed Syntax Destination/ source Pointer address (Hex.) Pointer size (Hex.) Length (bytes) ld A,($1000,X) 0000..FFFF − − +2 Long Direct Short Indirect − ld A,[$10] 00..FF 00..FF byte +2 Long Indirect − ld A,[$10.w] 0000..FFFF 00..FF word +2 Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2 Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..
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Instruction set ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 50. Inherent instructions (continued) Instruction Function PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplication SLL, SRL, SRA, RLC, RRC Shift and Rotate operations SWAP Swap nibbles 12.1.2 Immediate Immediate instructions have two bytes: The first byte contains the opcode and the second byte contains the operand value. . Table 51.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Instruction set The indexed addressing mode consists of three submodes: 12.1.5 • Indexed (no offset) There is no offset, (no extra byte after the opcode), and it allows 00 - FF addressing space. • Indexed (short) The offset is a byte, thus requiring only one byte after the opcode and allows 00 - 1FE addressing space. • Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.
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Instruction set I ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 53. Short instructions supporting direct, indexed, indirect and indirect indexed addressing modes Short instructions only 12.1.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Instruction set Table 55.
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Instruction set ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 56. Instruction set overview Mnemo Description Function/example Dst Src H I N Z C ADC Add with Carry A=A+M+C A M H − N Z C ADD Addition A=A+M A M H − N Z C AND Logical And A=A.M A M − − N Z − BCP Bit compare A, memory tst (A .
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Instruction set Table 56.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 13 Electrical characteristics 13.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 13.1.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics Figure 51. Pin input voltage ST7 PIN VIN 13.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 57.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 1. All power (VDD) and ground (VSS) lines must always be connected to the external supply. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics 13.3 Operating conditions 13.3.1 General operating conditions TA = -40 to +85 °C unless otherwise specified. Table 60. General operating conditions Symbol Parameter VDD Supply voltage fCPU CPU clock frequency Conditions Min Max fCPU = 4 MHz. max. 2.4 5.5 fCPU = 8 MHz. max. 3.3 5.5 3.3 V≤VDD≤5.5 V up to 8 2.4 V≤VDD<3.3 V up to 4 Unit V MHz Figure 52.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 1. Not tested in production. 2. Not tested in production. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. When the VDD slope is outside these values, the LVD may not ensure a proper reset of the MCU. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull VDD down to 0 V to ensure optimum restart conditions.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 13.3.3 Electrical characteristics Auxiliary voltage detector (AVD) thresholds TA = -40 to 85°C, unless otherwise specified. Table 62. AVD thresholds Symbol Parameter Conditions Min Typ Max Unit 1=>0 AVDF flag toggle threshold (VDD rise) High Threshold Med. Threshold Low Threshold 4.40(1) 3.90(1) 3.20(1) 4.70 4.10 3.40 5.00 4.30 3.60 VIT-(AVD) 0=>1 AVDF flag toggle threshold (VDD fall) High Threshold Med. Threshold Low Threshold 4.30 3.70 2.90 4.60 3.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 64. RC oscillator and PLL characteristics (tested for TA = -40 to +85°C) @ VDD = 4.5 to 5.5 V Symbol fRC (1) Parameter Internal RC oscillator frequency (1) Conditions Min Typ Max RCCR = FF (reset value), TA=25 °C, VDD=5 V − 760 − (2) − 1000 − RCCR = RCCR0 , TA=25 °C, VDD=5 V Unit kHz Accuracy of Internal RC oscillator with RCCR=RCCR0(2) TA=25° C, VDD=4.5 to 5.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics RC oscillator and PLL characteristics (tested for TA = -40 to +85°C) @ VDD = 2.7 to 3.3V Symbol fRC(1) ACCRC Parameter Internal RC oscillator frequency(1) Accuracy of Internal RC oscillator when calibrated with RCCR=RCCR1(2)(3) Conditions Min Typ Max − 560 − − 700 − TA=25°C,VDD=3V -2 − +2 % TA=25°C,VDD=2.7 t 3.3V -25 − +25 % TA=-40 to +85°C,VDD=3V -15 − 15 % RCCR = FF (reset value), TA=25 °C, VDD= 3.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Output Freq. (MHz) Figure 54. RC Osc Freq vs VDD (calibrated with RCCR0: 5V@ 25°C) 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 -45° 0° 25° 90° 105° 130° 2.5 3 3.5 4 4.5 5 5.5 6 Vdd (V) Figure 55. Typical RC oscillator Accuracy vs temperature @ VDD=5V (calibrated with RCCR0: 5V @ 25°C) 2 (*) RC Accuracy 1 0 (*) -1 -2 -3 -4 -5 ( ) * -45 0 25 85 125 Temperature (°C) (*) tested in production Figure 56.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics Figure 58. PLLx4 Output vs CLKIN frequency Output Frequency (MHz) 7.00 6.00 5.00 3.3 4.00 3 2.7 3.00 2.00 1.00 1 1.5 2 2.5 3 External Input Clock Frequency (MHz) 1. fOSC = fCLKIN/2*PLL4 Figure 59. PLLx8 Output vs CLKIN frequency Output Frequency (MHz) 11.00 9.00 7.00 5.5 5 5.00 4.5 4 3.00 1.00 0.85 0.9 1 1.5 2 2.5 External Input Clock Frequency (MHz) 1. fOSC = fCLKIN/2*PLL8 Table 65.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 66. Supply current Symbol Parameter Conditions Typ Max 1 − 2.2 − fCPU=8MHz 7.5 12 External Clock, fCPU=1MHz(2) 0.8 − Internal RC, fCPU=1MHz 1.8 − fCPU = 8MHz(2) External Clock, fCPU = 1MHz(1) Supply current in Run mode Internal RC, fCPU=1MHz (1) Supply current in WAIT mode IDD 3.7 6 Supply current in SLOW mode fCPU = 250kHz (3) 1.6 2.5 Supply current in SLOW-wait mode fCPU = 250kHz(4) 1.6 2.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics Figure 61. Typical IDD in SLOW vs. fCPU 1.6 1.4 250Khz 125Khz 62.5Hz Idd (mA) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vdd (V) Figure 62. Typical IDD in WAIT vs. fCPU 1.6 1.4 250Khz 125Khz 62.5Hz Idd (mA) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vdd (V) Figure 63. Typical IDD in SLOW-WAIT vs. fCPU 1.4 250KHz 1.2 125KHz Idd (mA) 1.0 62.5Khz 0.8 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Figure 65. Typical IDD vs. temperature at VDD = 5V and fCPU = 8MHz 8.0 25° -45° 90° 130° 7.0 Idd (mA) 6.0 5.0 4.0 3.0 2.0 2.4 2.8 3.2 3.6 4 4.4 Vdd (V) 4.8 5.2 5.6 Table 67. On-chip peripherals Symbol IDD(AT) Parameter Conditions 12-bit Auto-Reload Timer supply current(1) IDD(SPI) SPI supply current(2) IDD(ADC) ADC supply current when converting(3) Typ fCPU=4MHz VDD=3.0V 300 fCPU=8MHz VDD=5.0V 1000 fCPU=4MHz VDD=3.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics Table 69. Auto Wakeup from Halt Oscillator (AWU) Symbol Parameter(1) Conditions Min Typ Max Unit fAWU AWU Oscillator Frequency − 50 125 250 kHz tRCSRT AWU Oscillator startup time − − − 50 µs 1. Guaranteed by design. 13.5.1 Crystal and ceramic resonator oscillators The ST7 internal clock can be supplied with eight different Crystal/Ceramic resonator oscillators.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 70. Resonator characteristics Symbol Parameter Conditions Min Typ Max Unit 2 − 16 MHz fCrOSC Crystal Oscillator Frequency(1) − CL1 CL2 Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (RS) − See Table 72: Resonator performances pF 1. When PLL is used, please refer to the Section 13.3.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics Table 72. Resonator performances Supplier (1) fCrOSC Typical ceramic resonators CL2(2) [pF] Rd [Ω] Supply voltage range [V] [MHz] Type 2 SMD CSTCC2M00G56-R0 (47) (47) 0 SMD CSTCR4M00G53-R0 (15) (15) 0 LEAD CSTLS4M00G53-B0 (15) (15) 0 SMD CSTCE8M00G52-R0 (10) (10) 0 LEAD CSTLS8M00G53-B0 (15) (15) 0 SMD CSTCE16M0V51-R0 (5) (5) 0 3.3V to 5.5V LEAD CSTLS16M0X53-B0 (15) (15) 0 4.5V to 5.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 74. Flash program memory Symbol Parameter Conditions (1) tprog tRET NRW IDD Min Typ Max Unit − 5 10 ms 0.24 0.48 s − − years 10K − − cycles Read / Write / Erase modes fCPU = 8MHz, VDD = 5.5V − − 2.6(5) mA No Read/No Write mode − − 100 μA Power down mode / HALT − 0 0.1 μA Programming time for 1~32 bytes TA=−40 to +85°C Programming time for 1.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics A device reset allows normal operations to be resumed. The test results are given in the Table 76 based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 77. Emission test Symbol Parameter SEMI Peak level Monitored Frequency Band Conditions VDD=5V, TA=+25°C, SO20 package, conforming to SAE J 1752/3 Max vs. [fOSC/fCPU] 8/4MHz 16/8MHz 0.1 MHz to 30 MHz 9 17 30 MHz to 130 MHz 31 36 130 MHz to 1 GHz 25 27 SAE EMI Level 3.5 4 Note: Data based on characterization results, not tested in production. 13.7.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics Table 79. Electrical sensitivities Symbol LU DLU Parameter Class(1) Conditions A Static latch-up class TA=+25°C Dynamic latch-up class VDD=5.5V, fOSC=4MHz, TA=+25°C A 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Figure 67. Two typical applications with unused I/O Pin VDD ST7XXX 10kΩ 10kΩ UNUSED I/O PORT UNUSED I/O PORT ST7XXX Caution: To avoid entering ICC mode unexpectedly during a reset, the ICCCLK pin must be pulled-up internally or externally during normal operation (external pull-up of 10k mandatory in noisy environment). Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics Table 81. Output driving current(1) Symbol Parameter Conditions Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 72) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 74) VOH(3) Max IIO=+5mATA≤85°C TA≥85°C 1.0 1.2 IIO=+2mATA≤85°C TA≥85°C 0.4 0.5 IIO=+20mATA≤85°C TA≥85°C 1.3 1.5 IIO=+8mATA≤85°C TA≥85°C 0.75 0.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Figure 70. Typical VOL at VDD = 2.7V (standard) 0.60 VOL at VDD=2.7V 0.50 0.40 -45°C 0°C 25°C 90°C 130°C 0.30 0.20 0.10 0.00 0.01 1 2 lio (mA) Figure 71. Typical VOL at VDD = 3.3V (standard) 0.70 VOL at VDD=3.3V 0.60 0.50 -45°C 0°C 25°C 90°C 130°C 0.40 0.30 0.20 0.10 0.00 0.01 1 2 3 lio (mA) Figure 72. Typical VOL at VDD = 5V (standard) 0.80 VOL at VDD=5V 0.70 0.60 -45°C 0°C 25°C 90°C 130°C 0.50 0.40 0.30 0.20 0.10 0.00 0.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics Figure 74. Typical VOL at VDD = 5V (high-sink) 2. 50 2. 00 -45 0°C 1. 50 25°C 1. 00 90°C 130°C 0. 50 0. 00 6 7 8 9 10 15 20 25 30 35 40 l i o (mA ) Figure 75. Typical VOL at VDD = 3V (high-sink) 1.20 Vol (V) at VDD=3V (HS) 1.00 0.80 -45 0°C 0.60 25°C 90°C 0.40 130°C 0.20 0.00 6 7 8 9 10 15 lio (mA) Figure 76. Typical VDD-VOH at VDD = 2.4V 1.60 VDD-VOH at VDD=2.4V 1.40 1.20 -45°C 0°C 25°C 90°C 130°C 1.00 0.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Figure 78. Typical VDD-VOH at VDD = 3V 1.60 VDD-VOH at VDD=3V 1.40 1.20 -45°C 0°C 25°C 90°C 130°C 1.00 0.80 0.60 0.40 0.20 0.00 -0.01 -1 -2 -3 lio (mA) Figure 79. Typical VDD-VOH at VDD = 4V 2.50 VDD-VOH at VDD=4V 2.00 -45°C 0°C 25°C 90°C 130°C 1.50 1.00 0.50 0.00 -0.01 -1 -2 -3 -4 -5 lio (mA) Figure 80. Typical VDD-VOH at VDD = 5V 2.00 VDD-VOH at VDD=5V 1.80 1.60 1.40 -45°C 0°C 25°C 90°C 130°C 1.20 1.00 0.80 0.60 0.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics Figure 82. Typical VOL vs. VDD (high-sink I/Os) 1.00 VOL vs VDD (HS) at lio=20mA VOL vs VDD (HS) at lio=8mA 0.70 0.60 0.50 -45 0.40 0°C 25°C 0.30 90°C 130°C 0.20 0.10 0.00 2.4 3 0.90 0.80 0.70 -45 0.60 0°C 0.50 25°C 0.40 90°C 0.30 0.20 130°C 0.10 0.00 2.4 5 3 5 VDD (V) VDD (V) Figure 83. Typical VDD-VOH vs. VDD 1.80 1.10 VDD-VOH (V) at lio=-2mA 1.70 VDD-VOH at lio=-5mA 1.60 1.50 -45°C 0°C 25°C 90°C 130°C 1.40 1.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 3. The IIO current sunk must always respect the absolute maximum rating and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 4. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between VILmax and VDD. 5. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (seeTable 2: Device pin description) 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin. 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any startup marginality.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 3. Depends on fCPU. For example, if fCPU = 8MHz, then TCPU = 1/ fCPU = 125ns and tSU(SS) = 550ns Figure 86. SPI slave timing diagram with CPHA = 0(1) SS INPUT SCK INPUT tsu(SS) tc(SCK) th(SS) CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) MISO OUTPUT (2) tw(SCKH) tw(SCKL) tv(SO) MSB OUT tsu(SI) th(SO) BIT6 OUT (2) LSB OUT th(SI) MSB IN MOSI INPUT tdis(SO) tr(SCK) tf(SCK) LSB IN BIT1 IN 1.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics Figure 88. SPI master timing diagram(1). SS INPUT tc(SCK) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) th(MI) tsu(MI) MISO INPUT MSB IN tv(MO) MOSI OUTPUT tr(SCK) tf(SCK) BIT6 IN LSB IN th(MO) MSB OUT (2) LSB OUT BIT6 OUT (2) 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 5. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then always valid. Figure 89. Typical application with ADC VDD VT 0.6V RAIN AINx 10-Bit A/D Conversion VAIN CAIN VT 0.6V IL ±1μA CADC 6pF ST72XXX Table 85. ADC accuracy with VDD = 5.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics Figure 90.
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Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Figure 92. Amplifier noise vs voltage Vout (ADC input) Vmax Noise Vmin 0V 430mV Vin (OPAMP input) Table 86. ADC characteristics(1) Symbol Parameter VDD(AMP) Amplifier operating voltage VIN Amplifier input voltage(2) VOFFSET Amplifier output offset voltage(3) VSTEP Step size for monotonicity(4) Linearity Output voltage response Gain factor Amplified analog input Conditions Min Typ − 3.6 − 5.5 VDD=3.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Package characteristics 14 Package characteristics 14.1 Package mechanical data Figure 93. 20-pin plastic small outline package, 300-mil width D h x 45× L A1 A c a B e E H Table 88. Small outline package characteristics mm inches Dim. Min Typ Max Min Typ Max A 2.35 − 2.65 0.093 − 0.104 A1 0.10 − 0.30 0.004 − 0.012 B 0.33 − 0.51 0.013 − 0.020 C 0.23 − 0.32 0.009 − 0.013 D(1) 12.60 − 13.00 0.496 − 0.512 E 7.40 − 7.
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Package characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Figure 94. 20-pin plastic dual in-line package, 300-mil width A2 A A1 L c b eB D1 e b2 D 20 11 1 10 E1 Table 89. Dual in-line package characteristics mm inches Dim. Min Typ Max Min Typ Max A − − 5.33 − − 0.210 A1 0.38 − − 0.015 − − A2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 D 24.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Package characteristics Table 90. Thermal characteristics Symbol Ratings SO20 DIP20 Value Unit 125 63 °C/W RthJA Package thermal resistance (junction to ambient) TJmax Maximum junction temperature(1) 150 °C PDmax Power dissipation(2) 500 mW 1. The maximum chip-junction temperature is based on technology characteristics. 2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA.
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Device configuration 15 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Device configuration Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (FASTROM). ST7FLITE2 devices are FLASH versions. ST7PLITE2 devices are Factory Advanced Service Technique ROM (FASTROM) versions: they are factory programmed FLASH devices.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Device configuration Table 93. Size definition Sector 0 size SEC1 SEC0 0.5k 0 0 1k 0 1 2k 1 0 4k 1 1 • OPT1 = FMP_R Read-out protection Read-out protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected will cause the whole memory to be erased first and the device can be reprogrammed.
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Device configuration 15.1.2 Note: ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Option byte 1 • OPT7 = PLLx4x8 PLL Factor selection.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Device configuration Table 96. List of valid option combinations Operating conditions VDD range Option bits Clock Source Internal RC 1% PLL (1) 2.4V - 3.3V External clock or oscillator (depending on OPT6:4 selection) Internal RC 1% External clock or oscillator (depending on OPT6:4 selection) PLLOFF PLLx4x8 0.7MHz @3V 0 1 1 x4 2.8MHz @3V 0 0 0 x8 − − − − off 0-4MHz 1 1 1 x4 4MHz 1 0 0 − − − 0 1 1 − − − − x8 1MHz @5V − x4 3.
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Device configuration ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 97. Supported part numbers Part number Program memory (Bytes) RAM (Bytes) Data EEPROM (Bytes) ST7FLITE20F2B6 ST7FLITE25F2B6 8K Flash − 384 SO20 -40 °C to +85 °C ST7FLITE29F2B6 256 ST7FLITE29F2M7 8K FASTROM ST7PLITE29F2B6 256 ST7PLITE29F2M6 158/170 − 384 Contact ST sales office for product availability.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Device configuration Table 98. ST7LITE2 FASTROM microcontroller option list Customer Address Contact Phone No Reference/FASTROM code (assigned by STMicroelectronics) FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.
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Device configuration 15.3 ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Development tools STMicroelectronics offers a range of hardware and software development tools for the ST7 microcontroller family. Full details of tools available for the ST7 from third party manufacturers can be obtained from the STMicroelectronics Internet site: http//www.st.com. Tools from these manufacturers include C compliers, evaluation tools, emulators and programmers.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Device configuration Table 99. STMicroelectronics development tools Emulation Supported Products ST7FLITE20 ST7FLITE25 ST7FLITE29 ST7 DVP3 Series Programming ST7 EMU3 series Emulator Connection kit Emulator Active Probe & T.E.B. ST7MDT10-DVP3 ST7MDT10-20/ DVP ST7MDT10-EMU3 ST7MDT10-TEB ICC Socket Board ST7SB10/123(1) 1. Add suffix /EU, /UK, /US for the power supply of your region. 15.4 Application notes Table 100.
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Device configuration ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 100.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Device configuration Table 100. ST7 application notes (continued) Identification Description AN1151 Performance Comparison Between ST72254 & PC16F876 AN1278 LIN (Local Interconnect Network) Solutions Product Migration AN1131 Migrating applications from ST72511/311/214/124 to ST72521/321/324 AN1322 Migrating an application from ST7263 Rev.
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Device configuration ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 100.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Important notes 16 Important notes 16.1 Execution of BTJX instruction When testing the address $FF with the "BTJT" or "BTJF" instructions, the CPU may perform an incorrect operation when the relative jump is negative and performs an address page change. To avoid this issue, including when using a C compiler, it is recommended to never use address $00FF as a variable (using the linker parameter for example). 16.
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Important notes ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Concurrent interrupt context The symptom does not occur when the interrupts are handled normally, i.e. when: • The interrupt request is cleared (flag reset or interrupt mask) within its own interrupt routine. • The interrupt request is cleared (flag reset or interrupt mask) within any interrupt routine. • The interrupt request is cleared (flag reset or interrupt mask) in any part of the code while this interrupt is disabled.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 17 Revision history Revision history Table 101. Revision history Date 30-Aug-2004 Revision 3 Description of changes Updated Figure 62. Typical IDD in WAIT vs. fCPU with correct data Added data for Fcpu @ 1MHz into Section 13.4.1 Supply Current table. EnabledProgramming Capability for EMU3, Table 26 Reset delay in section 11.1.3 on page 53 changed to 30µs Altered note 1 for section 13.2.
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Revision history ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Table 101. Revision history (continued) Date 07-Jul-2006 168/170 Revision Description of changes 4 Added 300K read/write cycles for EEPROM on first page Updated Section 4.4 on page 22 and modified note 5 and Figure 5 Added note 2 in External interrupt control register (EICR) on page 41 and changed External interrupt function on page 64 Modified read operation section in Memory access on page 25 Added note to Section 7.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Revision history Table 101. Revision history (continued) Date Revision Description of changes 25-Jun-2013 5 Added Temperature range in Features. Added ST7FLITE29F2M toTable 97: Supported part numbers and Table 98: ST7LITE2 FASTROM microcontroller option list. 31-Jul-2013 6 Added a second Temperature range in Features. Updated the Operating temperature row in Table 1: Device summary. Updated the Temp.
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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.