User manual

Timing and Clock Overview
8-2 Campus-RS Fractional Interface Card User Manual
Standard Timing Configuration
In this configuration, the internal oscillator of one unit is used as a frequency
reference for all clocks in the system. Since the Fractional Interface Cards are
designed as DCE, they are expected to provide both Serial Clock Transmit
(SCT) and Serial Clock Receive (SCR) output signals. Within a Campus
system, set the Timing Source option for one of the Fractional Interface Cards
to HDSL timing, as shown in the following figure. The connected host
devices then use the SCT and SCR timing signals in order to derive transmit
and receive timing for the Send Data (SD) and Receive Data (RD) signals.
The Terminal Timing (TT) signal shown in the figure above compensates for
clock and data delays associated with long cables, or delays that may be
inherent to the connected host equipment. Although it is highly
recommended, the TT signal is optional in this timing configuration. If the TT
signal is used, the host equipment must derive the TT signal from the SCT
signal. This is discussed further in the “Transmit Clock” section of this
manual.
Desktop or
Line Unit*
Desktop or
Line Unit**
DTE Host
Equipment
DTE Host
Equipment
SCT
SCT
TT TT
HDSL
SCR
SCR
Oscillator
* Set to Internal Timing
** Set to HDSL Timing