User manual

Timing and Clock Overview
Campus-RS Fractional Interface Card User Manual 8-3
Port Timing Configuration
If one of the Fractional Interface Cards needs to accept primary timing from
the connected host equipment, set its Timing Source option to Port timing. Set
the Timing Source option for any connected Campus units to HDSL timing.
The TT input of the “Port-timed” unit is used as a frequency reference for all
clocks in the system, as shown in the figure below. A phase lock loop (PLL)
keeps the Campus system in phase with the host timing. In this configuration,
the TT input of the “Port-timed” unit serves a different purpose than in the
figure on page 8-2, and the Transmit Clock option becomes irrelevant. The
TT input is used as a means of establishing the primary timing reference for
both of the fractional interfaces and the HDSL link. Because the TT input is
used to synchronize all clocks, excessive jitter and poor frequency stability at
the TT input can cause degraded link performance.
The timing configuration shown in the figure above reverses the DTE/DCE
role on one of the Fractional Interface Cards, forcing it to act as DTE instead
of DCE. With this timing configuration, and with a DTE/DCE “cross-over”
cable, you could connect one of the Fractional Interface Cards to a standard
DCE host, as shown in the figure below.
Desktop or
Line Unit*
Desktop or
Line Unit**
DTE Host
Equipment
DTE Host
Equipment
SCT
SCT
TT TT
HDSL
SCR
PLL
SCR
* Set to Port Timing
** Set to HDSL Timing
Host Equipment
as DCE
Campus Desktop
or Line Unit as DTE
Port Timing
C
ross-
O
ver
Data Cable
TT SCR
SD
SCT
SCR
RD
NC NC
RD
SCT
TT
SD
Primary
Timing
HDSL