User manual

Timing and Clock Overview
8-4 Campus-RS Fractional Interface Card User Manual
The SCT signal on the Fractional Interface Cards cannot be configured as an
input. Also, in a standard DCE host, the SCT signal is also an output. There
are two critical implications for the configuration shown in the figure above:
• The Fractional Interface Card accepts only one clock input (TT), this
clock is assumed to provide a timing reference for both the transmit and
receive data paths. The Fractional Interface Card uses the TT input to
clock-in the SD input, and to clock-out the RD output. For proper
operation, the DCE host must generate SCT and SCR from the same
primary timing source. SCT and SCR can have a constant phase delay
relative to each other, but they must be generated from the same timing
source.
• Because the Fractional Interface Card synchronizes the RD output to the
SCR clock output pin, the DCE host must be configured to sample the
SD input based upon the TT clock input.
TRANSMIT CLOCK
Set the Transmit Clock option only if the Timing Source is set to either
Internal or HDSL. When the Timing Source option is set to Port timing, the
Transmit Clock option does not need to be set because TT is equivalent to
SCT. The Transmit Clock option can be set to either External or Internal, and
determines how the SD signal is sampled.
• External: The SD is sampled based upon the clock transitions on the TT
input.
• Internal: The SD is sampled based upon the clock transitions on the
SCT output.
One of the functions of the TT signal is to compensate for potential problems
with clock and data delays associated with long cables, or delays that may be
inherent to the connected host equipment. Potential delay problems exist
when the SD signal arriving at the input of the Fractional Interface Card
experiences phase delays relative to the SCT clock provided at the output of
the Fractional Interface Card (shown in the figure below). This occurs when
the data cable causes a significant delay on the SCT and SD signals, or when
the host equipment delays the transmission of the SD signal, relative to the
transitions on the received SCT signal, causing the SCT and SD signals to
lose synchronization.