User manual

Timing and Clock Overview

Campus-RS Fractional Interface Card User Manual 8-5

To circumvent this potential problem, set the Transmit Clock option on the

Fractional Interface Card to External, so that the transmit clock is taken from

the TT input instead of the SCT output. With this approach, the TT and SD

signals experience the same delay as they propagate through the data cable,

and remain synchronized to each other.

When the Timing Source is set to either Internal or HDSL, the SCT signal is

used by the Fractional Interface Card to establish the frequency of the

transmit data path. It does not necessarily indicate exactly where the

transitions on SD should occur. SD typically has a constant phase delay from

SCT. The TT signal, on the other hand, indicates the exact location of the

binary transitions on SD. Any phase delay from the SCT output to the TT

input must be constant. Furthermore, the TT signal cannot be from a different

frequency source than SCT, and should not insert any jitter.

Host Equipment

Campus Desktop

or Line Unit

Internal or

HDSL Timing

Data

able

SCR

SCT

HDSL