User manual

Configuring with an ASCII Terminal
Campus-RS Fractional Interface Card User Manual 5-17
Setting the Primary Timing Source
The primary timing source determines the timing for the entire HDSL system.
Timing can come from one of three parts of the Campus system:
• Data Port receives timing through the host equipment connected to the
data port.
• Internal receives timing from the internal oscillator of the Campus unit
(default setting).
• HDSL receives timing over the HDSL line.
Either the local or remote unit must have the timing source set to HDSL. The
other unit must be set to Data Port or Internal, depending on the system setup.
See “Timing Source” on page 8-1 for examples of timing configurations.
To set the Primary Timing Source:
1 From the Data Port Settings menu, type then press . The
Timing Source option changes to the next available setting.
2 Repeat the previous step until the Data Port Settings menu displays the
desired Timing Source setting.
Setting the Transmit Clock
The Transmit Clock option determines how the SD signal is sampled if the
Timing Source is set to Internal or HDSL. There are two settings:
• External SD is sampled based on the clock transitions on the TT input.
• Internal SD is sampled based on the clock transitions on the SCT output.
For complete information about the Transmit Clock option, see “Transmit
Clock” on page 8-4.
To set the Transmit Clock:
1 From the Data Port Settings menu, type then press . The
Transmit Clock option changes to the next available setting.
2 Repeat the previous step until the Data Port Settings menu displays the
desired Transmit Clock setting.
3 ENTER
4 ENTER