User's Manual
Table Of Contents
- 1. Introduction
- 2. Hardware
- 3. The A431 Radio Module
- 3.1. About the A431 Radio Module
- 3.2. Functional description
- 3.3. Manufacturing Issues
- 3.3.1. Marking and labeling issues
- 3.3.2. Alignment Range and Switching Range
- 3.3.3. Tuning Procedure
- 3.3.4. Setting Up the Default Parameters
- 3.3.5. Definitions
- 3.3.6. Test Equipment Settings
- 3.3.7. Trimming Elements
- 3.3.8. Adjusting the Receiver Front End
- 3.3.9. Adjusting the VCOs
- 3.3.10. Adjusting the Crystal Reference
- 3.3.11. Checking the Receiver Parameters
- 3.3.12. Checking the Transmitter Parameters
- 3.3.13. Data Transfer Check
- 3.6. Frequency Reference Specifications
- 3.7. A431 Module’s Photographs
- 4. Software
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The A431 Radio Module
The incoming signal is then applied to the first mixer, U7, through an LC impedance
matching network (L12/C48). The local oscillator signal is obtained by means of the
VCO built around U10 and applied to the mixer (the LO has a lower frequency than
the incoming signal). The VCO is locked to the OSC1 reference by means of the U9
dual-PLL chip.
The mixer’s output on 45 MHz is filtered by means of XF1, which is needed to ensure
a sufficient attenuation (over 70dB) of the second image frequency (at 44.090 MHz).
The second local oscillator is built around the IF chip, but it is locked by means of
the second PLL of U9. In this way, all signals are generated from a common reference
oscillator (OSC1, see also “Frequency Reference Specifications” on page 45).
The IF chain chip amplifies the signal to a proper level for FM detection. A particu-
larity of this chip is that the FM detector is PLL-based, thus no coils or ceramic dis-
criminators are needed. Two ceramic filters, CF1 and CF2, ensure the required
adjacent channel separation. The audio output is delivered on pin 17 and is slightly
amplified through U11 in order to bring it to 1Vpp, and centered on half the supply
voltage (which is 3.3 volt approximately). The audio signal is fed out of the module
on the pin
RXDO
of the interface connector. In addition, an RSSI level signal is ob-
tained on pin 18 of U8 and is fed to switch U6. As long as the module is in receive
mode, the RSSI signal will be present on the
RSSI/PO
pin of the interface connector.
3.2.2. Transmitter Section
The carrier is generated directly on the operating frequency by means of the VCO
built around U2. The signal is locked on the reference OSC1 with the aid of the dual
PLL chip based on U9. The chip, a National Semiconductor LMX2332L, was chosen
for its fast locking scheme, low power consumption, and good RF characteristics.
The modulation is applied on both the VCO and the reference, in order to attain a
flat characteristic in the whole band (10 Hz to 2.5 kHz). Due to the phase differences
between the two modulation points, the signal applied on the reference is inverted
by means of U4. Meanwhile, U4 is used to center the reference on the channel (using
the trimpot R75). The PLL low-pass filter (third-order) composed of C66/C67/R69/
R59/C64 is calculated around 400 Hz. R64 is used for the FastLock® mechanism.
(For further details on the FastLock mechanism, please consult the National Semi-
conductor documentation.)
The signal is pre-amplified to approximately 0 dBm by Q1 and then it is applied to
the PA built with U1. The output signal is pre-filtered and impedance-matched by
means of theC21/L10/C22 low-pass filter and then fed to the antenna switch. Before
reaching the antenna output, a three-cell, low-pass filter (used also on the receive
path) is used to attenuate the unwanted harmonics and keep them below the re-
quired limits.