Serial ATA International Organization: Serial ATA Interoperability Program Revision 1.3 Unified Test Document Version 1.1 15- October-2009 SATA-IO Board Members: Dell Computer Corporation Hewlett Packard Corporation Hitachi Global Storage Technologies, Inc. Intel Corporation Seagate Technology Maxim Integrated Products, Inc.
Serial ATA International Organization: Serial ATA Interoperability Program Unified Test Document is available for download at www.sata-io.org. DOCUMENT DISCLAIMER THIS DOCUMENT IS PROVIDED TO YOU “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE.
Version History Version 1.00 1.0.95 Date 06/12/2008 12/18/2008 1.01RC1 1.01RC2 1.01RC3 1.
Digital – Host – normative Digital – Device – Documented minimum loop counts (IPM-03 / -04 / -11) Informative tests: Cable - eSATA cable (electrical and mechanical) Product Mechanical - eSATA mechanical Digital - Port Multiplier Device Mechanical - uSATA SATA-IO Confidential 4
Table of Contents Goals, Objectives, & Constraints............................................................................................................................... 8 1.1. References ......................................................................................................................................................... 8 1.1.1. Definitions .............................................................................................................................................
2.5.10. IPM-10 : Slumber State exit latency (device-initiated) .......................................................................... 35 2.5.11. IPM-11 : Speed matching upon resume (device-initiated) .................................................................... 36 2.6. Mechanical - Cable Assembly - Standard Internal and eSATA ....................................................................... 37 2.6.1. MCI-01 : Visual and Dimensional Inspections ...............................................
2.15.2. RX-02 : Single-Ended Impedance (Obsolete) ....................................................................................... 60 2.15.3. RX-03 : Gen2 (3Gb/s) Differential Mode Return Loss .......................................................................... 60 2.15.4. RX-04 : Gen2 (3Gb/s) Common Mode Return Loss ............................................................................. 61 2.15.5. RX-05 : Gen2 (3Gb/s) Impedance Balance .....................................................
1. Goals, Objectives, & Constraints This document defines the test requirements specific to the SATA-IO Interoperability Program. Many of the test requirements are associated with a subset of requirements included in the Serial ATA (SATA) Revision 2.6 specification and these test requirements are based upon the requirements for the Serial ATA protocol and features, intended to verify a subset of the specification requirements and ensuring compatibility for Serial ATA.
021 022v1 Correct internal height dimension for eSATA plug Remove references to “KB” Included in MXE-01a No impact 1.1.1. Definitions 1.1.1.1. Product General reference to any SATA product supportable by the Interop Program for testing. 1.1.1.2. Device A product falling under the Device product class which is a storage peripheral. This includes hard disk drives, halfheight, and slimline ATAPI devices. 1.1.1.3.
1.1.2.1.3. may A keyword that indicates flexibility of choice with no implied preference. 1.1.2.1.4. normative A test or test area which is required to an applicable product type. Unless otherwise stated, all tests, test areas are required for the applicable product types. Only normative product types that have passed all the normative tests can be placed on the integrators list. Informative or obsolete test results shall have no bearing on a products approval status. 1.1.2.1.5.
1.3. Methods of Implementation A Method of Implementation (MOI) is defined as documentation specifying test tool details and procedures for the specific use of verifying the different Interoperability test areas. In the future a template for development of a MOI for a specific test tool may be developed, but at this time a MOI, at a minimum, must simply include the following: • Hardware equipment model number(s) • Software revision number(s) • Hardware dependencies (e.g.
1.4.4. Host Considerations A host vendor is required to supply at least two samples. In some cases up to two samples will be run through testing in parallel at a given time. In most cases, the second or third sample shall not be secured within a chassis or platform case, as this sample may be used specifically for mechanical testing. Prior to execution of any testing on a host, a “worst port” must be identified.
Test GRP Sec # NCQ 2.2 ASR 2.3 SSP 2.4 IPM 2.5 MCI 2.6 MCX MCE SI 2.6.6 MDI 2.8 MDP MHI MXE * PHY 2.9 2.10 2.11.1 2.12 Test Req.
Test GRP Sec # TX 2.13 TSG 2.14 RX 2.15 RSG 2.16 OOB 2.17 PM 2.18 Test Req.
Test GRP Sec # Test Req.
Measurement Requirements • Check Word 76 bit 2 in IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data (set to one) • If the above are true, then run the following test when connected to a 3Gb/s host and 1.5Gb/s host Check Word 76 bit 1 in IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data (set to one) Complete OOB sequence at least 10 times Pass/Fail Criteria • Values below shall be confirmed when tested in connection with both 3Gb/s host and 1.
• Issue and complete one tracks worth of read commands using the DMA protocol with transfer size of greater than 8Kbytes but less than or equal to 128Kbytes, followed by issue and completion of another tracks worth of read commands using the DMA protocol to the same disk location that the previous reads were completed. The test shall verify that the contents read have the same values that were read initially.
• Transmit undefined FIS to device Pass/Fail Criteria • Verify R_ERR response from device 2.2. Native Command Queuing The Native Command Queuing (NCQ) test requirements are determined by the requirements of the feature as defined in Serial ATA Revision 2.6. All of the test requirements listed in this section require that support for NCQ is claimed by the product for verification of the Expected Behavior. Support for NCQ can be verified by reading Word 76 bit 8 set to one in IDENTIFY DEVICE data. 2.2.1.
o Issue READ LOG EXT to log page 10h Pass/Fail Criteria • Verify successful completion & data transfer for log page 0h • Verify offset 20h of log page 00h contains value of 1 • Verify offset 21h of log page 00h contains value of 0 • Verify successful completion & data transfer for log page 10h, it is NOT necessary that the contents of the log page are verified for specific values 2.2.3. NCQ-03 : Intermix of Legacy and NCQ commands 2.2.3.1. Device Expected Behavior See section 13.5.
2.2.4. NCQ-04 : Device response to malformed NCQ command 2.2.4.1. Device Expected Behavior See section 13.5.2.and 13.5.4.1 of Serial ATA Revision 2.6.
Pass/Fail Criteria • In the case of a duplicate tag or tag out of range, verify the following: o Verify receipt of Register FIS with error, followed by • Verify SDB receipt with ERR bit cleared to zero, DRDY bit set to 1,DF bit cleared to 0, and ‘I’ bit cleared to zero. The SActive field shall be set to FFFFFFFFh.
In a case where the device is in an interface quiescent state in response to receipt of a COMRESET signal from the host, the device shall respond with a COMINIT signal within 10 ms of de-qualification of a received COMRESET signal. Measurement Requirements • Power on host & device • Setup bus analyzer (or scope) for tracing of bus activity & begin tracing • Initiate COMRESET sequence o This requirement must be verified on 5 total sequences within the trace.
Pass/Fail Criteria • Verify that once device is powered off, that host sends COMRESET repeatably and no faster than every 10ms (use trace to verify behavior and timings). Since a single result is reported, the worst-case result out of all 10 cases must be reported (i.e. smallest value). • NOTE : the time to be compared to this requirement is from the start of the first COMRESET burst (detectable point) to the start of a subsequent COMRESET burst from the host.
Measurement Requirements • Check Word 78 bit 6 in IDENTIFY DEVICE (set to one) • Check Word 84 bit 4 (set to one) • If the above is false, then the test is not applicable • Otherwise, run the following test o Check value of log pages 22:21 o Complete an ATA specification compliant activity to change the values represented in log pages 22:21 such that they do not represent the default values. The state of the new values must be known for comparison in pass/fail criteria.
NOTE - To test the following requirement, a device must claim support for Host Protected Area (Word 82 bit 10 set to one in IDENTIFY DEVICE data). Upon receipt of a COMRESET, a device shall maintain the max address established by the SET MAX ADDRESS or SET MAX ADDRESS EXT command. Specifically, the value contained within Words 61:60 in IDENTIFY DEVICE data shall be maintained after a COMRESET.
2.4.6. SSP-06 : Set Features – Set Transfer Mode 2.4.6.1. Device Expected Behavior Upon receipt of a COMRESET, a device shall maintain the Multiword DMA and Ultra DMA mode settings. Specifically, the values contained within Word 63 bits 10:8 (MWDMA) and Word 88 bits 14:8 (UDMA) in IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data shall be maintained after a COMRESET. The bits in Word 88 are only valid if Word 53 bit 2 is set to one.
o o o o o o Check Word 86 bit 3 (set to one) Issue SET FEATURES to alter setting for APM enable/disable If Word 86 bit 3 is set to one, Check value of Word 91 bits 7:0 Issue COMRESET and complete OOB sequence Check Word 83 bit 3, If Word 86 bit 3 is set to one, Check value of Word 91 bits 7:0 Pass/Fail Criteria • Verify that IDENTIFY DEVICE Word 86 bit 3 contains the same value following COMRESET o If Word 86 bit 3 was set to one, verify that IDENTIFY DEVICE 91 bits 7:0 contains the same value followi
• • If the above is false, then the test is not applicable Otherwise, run the following test o Check value of Word 85 bit 7 o Issue SET FEATURES to alter setting for release interrupt enable/disable o Issue COMRESET and complete OOB sequence o Check value of Word 85 bit 7 Pass/Fail Criteria • Verify that IDENTIFY DEVICE or IDENTIFY PACKET DEVICE Word 85 bit 7 contains the same value following COMRESET 2.4.10. SSP-10 : Set Features – Service Interrupt 2.4.10.1.
o o o o o o Check for non-zero value of Word 47 bits 7:0 Issue Set Multiple command to change the block size from the value reported in Word 47 bits 7:0 Check value of Word 59 bits 8:0 Verify correct block size is set due to Set Multiple command Issue COMRESET and complete OOB sequence Check value of Word 59 bits 8:0 Pass/Fail Criteria • Verify that IDENTIFY DEVICE Word 59 bits 8:0 contains the same value following COMRESET 2.5.
NOTE – ensure there is no conflict with a device initiated request NOTE – a host vendor may provide a vendor unique tool for initiating the power management requests as to ensure the test does complete as necessary. Issue COMWAKE and wait for complete wake of host This requirement must be verified on 10 total sequences within the trace.
2.5.3. IPM-03 : Speed matching upon resume (host-initiated) 2.5.3.1. Device/Host Expected Behavior See section 8.3 of Serial ATA Revision 2.6. The product signaling speed upon returning from a partial or slumber state shall match the speed prior to entering the partial or slumber state.
• • • Check Word 76 bit 9 in IDENTIFY DEVICE or IDENTIFY PACKET DEVICE (cleared to zero) If the above is true, then run the following test o Issue PMREQ_P or PMREQ_S and receive device response This requirement must be verified on 10 total sequences Measurement Requirements (Host) • Setup bus analyzer (or scope) for tracing of bus activity & begin tracing • Issue PMREQ_P or PMREQ_S and receive host response • This requirement must be verified on 10 total sequences of PMREQ_P and 10 total sequences of PMRE
If a device claims support host interface power management (Word 76 bit 9 set to one in IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data), upon receipt of a PMREQ_S the following are valid device responses: • • respond with between 4 and 16 PMACK primitives and place the device Phy layer into the slumber state respond with PMNAK until SYNC is received from the host, no device Phy layer power transition shall occur.
Pass/Fail Criteria • Verify that Word 79 bit 3 in IDENTIFY DEVICE or IDENTIFY PACKET DEVICE is cleared to zero in both instances above • Since a single pass/fail result is reported, it must be verified that all 10 test sequences were a pass for the final result to be a PASS for this test requirement. 2.5.8. IPM-08 : Device Initiated Power Management enable / disable 2.5.8.1. Device Expected Behavior This test is not applicable to hosts. See section 13.2.4.3 of Serial ATA Revision 2.6.
The device and host exit latency (i.e. COMWAKE response) from the partial state shall start within 10 microseconds of COMWAKE receipt from the host.
If not Slumber IPM request has been generated by the device, issue a STANDBY IMMEDIATE command to device and wait up to 10 seconds • NOTE – a device vendor may provide a vendor unique tool for initiating the power management requests as to ensure the test does complete as necessary.
• This requirement must be verified on 10 total sequences of PMREQ_P, if supported and 10 total sequences of PMREQ_S, if supported. Pass/Fail Criteria • A sequence fails if there is no response (i.e. no PMACK or PMNAK is returned) or if the interface rate changes from before to after the power management sequence. • To report a single pass/fail result for all sequences, the following pass/fail rules apply: 1. If 1 or more of the sequences fails, the result is Fail. 2.
• For a latching cable the latch engagement feature shall be able to deflect below 1.50 mm (Figure 31). 2.6.2. MCI-02 : Insertion Force (Latching and Non-Latching) 2.6.2.1. Cable Assembly Expected Behavior See section 6.1.10.2, Table 6 of the Serial ATA Revision 2.6 specification. Measurement Requirements See section 6.1.10.2, Table 6 of the Serial ATA Revision 2.6 specification. This test is only applicable to standard internal (latching and non-latching) SATA cables.
Measurement Requirements See section 6.1.10.2, Table 6 of the Serial ATA Revision 2.6 specification. This test is applicable to standard internal (latching and non-latching) SATA and eSATA cables. A before and after test resistance measurement shall be made and the difference will be the change in resistance. Pass/Fail Criteria • NOTE : all applicable measurements within this test must be verified as a pass for the overall result of this test requirement to be reported as a PASS.
The tester shall ensure that the cable assemblies are clearly labeled so that each line in a cable assembly can be uniquely identified. For a standard internal cable assembly, a suggested labeling method is: • Each of the cables is labeled • The two ends of the cable are also labeled, e.g. Recept_A, Recept_B • The signal lines use the pin names provided in the specification. For standard internal connectors table 2 and Figure 29 of section 6.1.3.2, in the Serial ATA Revision 2.
Pass/Fail Criteria For an internal SATA and eSATA cable: • Cable Absolute Differential Impedance 100 Ohms ±10% 2.7.3. SI-03 : Cable Pair Matching 2.7.3.1. Cable Assembly Expected Behavior See section 6.5.1.1, Table 16 of the Serial ATA Revision 2.6 specification. The test shall be performed on one end of the cable assembly, for each differential pair of the assembly. Measurement Requirements • See section 6.5.2.4, Table 21, Procedure P3 of the Serial ATA Revision 2.6 specification.
Figure – 1 Example result showing the last vestige of the connector response (at 1.8 ns) The test shall be performed on one end of the cable assembly, for each differential pair of the assembly. After completing the common procedures (and before doing the measurement) the instrument rise time shall be set or the results filtered for a minimum of 55 ps to a maximum of 70 ps (20-80%) system rise time. The system rise time shall be set as close to 70 ps (20-80%) as practical.
2.7.6. SI-06 : Intra-Pair Skew 2.7.6.1. Cable Assembly Expected Behavior See section 6.5.1.1, Table 16 of the Serial ATA Revision 2.6 specification. The test shall be performed in one direction on the cable assembly, for each differential pair of the assembly. Measurement Requirements • See section 6.5.2.4, Table 14, Procedure P10 of the Serial ATA Revision 2.6 specification. • This test is normative for internal SATA cables and informative for eSATA cables.
• For an internal SATA and eSATA cable: • See section 6.5.2.4, Table 21, Procedure P6 of the Serial ATA Revision 2.6 specification. • If a time-based test equipment is used to measure the NEXT, it must use a acquisition window that is at least 4 times the propagation delay of the cable (electrical length). • For test adapters comprising of 2 plugs to SMA and 1 receptacle to SMA adapters, each combination of plug / receptacle shall have a NEXT performance better than -36dB (10-4500 MHz).
• • • • • • For a 5.25” non-optical device see either section 6.1.2, Figure 18 or section 6.1.2, Figure 19 of the Serial ATA Revision 2.6 specification. For a 3.5” side mounted device see section 6.1.2, Figure 20 of the Serial ATA Revision 2.6 specification. For a 3.5” bottom mounted device see section 6.1.2, Figure 21 of the Serial ATA Revision 2.6 specification. For a 2.5” side mounted device see section 6.1.2, Figure 22 of the Serial ATA Revision 2.6 specification. For a 2.
• • d2) From the centerline of the bottom mounting holes to the base of the tongue of the SATA plug shall be 36.38 +/- 0.50 mm. For a 2.5” device: a1) From the centerline of the side mounting holes to the top of the tongue of the SATA plug shall be 0.50 +/- 0.38 mm. a2) From the bottom surface of the drive to the top of the tongue of the SATA plug shall be 3.50 +/- 0.38 mm. b) Parallelism of the top of the tongue of the SATA plug vs. the bottom surface of the drive shall be 0.25 mm.
b) If the “Optional Wall” of Figure 28 is present then the distance from the device plug tongue to the wall shall be 1.58 +/- 0.08 mm. c) If the “Optional Wall” of Figure 28 is not present then there shall be a minimum of a 1.5 mm keep out zone from Datum A of Figure 26 to the nearest obstruction. d) The combined width of the power and signal segments shall be 33.39 +/- 0.08 mm. e) The separation between the power and signal segments shall be 2.41 +/- 0.05 mm. 2.9. Mechanical – Device - Power Connector 2.
Pass/Fail Criteria • NOTE : all applicable measurements within this test must be verified as a pass for the overall result of this test requirement to be reported as a PASS. For Slimline hosts: a) (TBD – next major revision) For all other hosts: a) Gap between tongue to edge of blind mate key shall be 1.65 +/- 0.15 mm b) Gap between tongue to blind mate key shall be 2.65 +/- 0.08 mm c) Gap between tongue and 2nd wall shall be a minimum of 1.10 mm d) Width of tongue shall be 10.41 +/- 0.
2.12. 2.12.1. Phy General Requirements PHY-01 : Unit Interval 2.12.1.1. Device/Host Expected Behavior See section 7.2.2.1.3 of Serial ATA Revision 2.6. Measurement Requirements • See section 7.4.11 of Serial ATA Revision 2.6. • For products which support 3Gb/s, this requirement must be tested at both interface rates (1.5Gb/s and 3Gb/s). Pass/Fail Criteria • PHY-01a - Mean Unit Interval measured between 666.4333ps (min) to 670.2333ps (max) (for products running at 1.
2.12.4. PHY-04 : Spread-Spectrum Modulation Deviation 2.12.4.1. Device/Host Expected Behavior See sections 7.2.2.1.6 and 7.3.3 of Serial ATA Revision 2.6. This test requires support for Spread Spectrum Clocking (SSC), which is optional. Measurement Requirements • See section 7.4.11 of Serial ATA Revision 2.6. • This test is only run once at the maximum interface rate of the product (1.5Gb/s or 3Gb/s).
Measurement Requirements • See section 7.4.23 of Serial ATA Revision 2.6. • This test requirement is only applicable to products running at 1.5Gb/s. For products which support 3Gb/s, this test is not required. • Testing of this requirement must be completed during transmission of the Mid Frequency Test Pattern (MFTP), The amplitude of a TDR pulse or excitation applied to an active transmitter shall not exceed 139mVpp (-13.2dBm 50 ohms) single ended.
• Calibrate to the end of the SMA cables, but do NOT include (de-embed) the SMA to SATA PCB and the SATA connector, so the board and the SATA connector are INCLUDED with the product measurement. • This test requirement is only applicable to products running at 3Gb/s. • Testing of this requirement must be completed during transmission of the Mid Frequency Test Pattern (MFTP), The amplitude of a TDR pulse or excitation applied to an active transmitter shall not exceed 139mVpp (-13.
Measurement Requirements • See section 7.4.10 of Serial ATA Revision 2.6. • Calibrate to the end of the SMA cables, but do NOT include (de-embed) the SMA to SATA PCB and the SATA connector, so the board and the SATA connector are INCLUDED with the product measurement. • This test requirement is only applicable to products running at 1.5Gb/s. For products which support 3Gb/s, this test is not required.
o Vtest = min(DH, DM, VtestAPP) – 1.5Gb/s [TSG-01b], 3 Gb/s [TSG-01h] • Note that gathering a minimum result from either of the options above is acceptable. It is not required to report a result for both. • Note that the pu/pl measurements outlined in the specification are to be taken, but the results are informative. There is not verification of maximum limit values for this measurement.
Table 7 - TX Rise/Fall Time Limit Min 20-80% Max 20-80% 2.14.3. Time @ 1.5Gb/s (ps (UI)) 100 (0.15) 273 (0.41) Time @ 3Gb/s (ps (UI)) 67 (0.20) 136 (0.41) TSG-03 : Differential Skew 2.14.3.1. Device/Host Expected Behavior See section 7.2.2.3.4 of Serial ATA Revision 2.6. Measurement Requirements • See section 7.4.12 of Serial ATA Revision 2.6. • This test is only run once at the maximum interface rate of the product (1.5Gb/s or 3Gb/s). • DC blocks or software/hardware equivalent shall be used.
TX+ rise TX+ fall TX- fall TX- rise TSG-05a TSG-05b TSG-05c TSG-05d Pass/Fail Criteria • Mean R/Fbal measured at a maximum of 20% (for products running at 3Gb/s) • The value above shall be based on at least 10,000 UIs 2.14.6. TSG-06 : Amplitude Imbalance 2.14.6.1. Device/Host Expected Behavior See section 7.2.2.3.10 of Serial ATA Revision 2.6. Measurement Requirements • See section 7.4.15 of Serial ATA Revision 2.6. • This test requirement is only applicable to products running at 3Gb/s.
TSG-12. In the past, a Data-to-Data Transmit Jitter (see section 7.2.2.3.11 in SATA Revision 2.6) method was used but is no longer preferred for the use of the interoperability testing. Pass/Fail Criteria • TJ measured at a maximum of 0.30 UI when measured at fBAUD/10 (for products running at 1.5Gb/s) 2.14.8. TSG-08 : Gen1 (1.5Gb/s) DJ at Connector, Clock to Data, fBAUD/10 (Obsolete) 2.14.8.1. Device/Host Expected Behavior See sections 7.2.2.3.11 and 7.3 of Serial ATA Revision 2.6.
TSG-12. In the past, a Data-to-Data Transmit Jitter (see section 7.2.2.3.11 in SATA Revision 2.6) method was used but is no longer preferred for the use of the interoperability testing. Pass/Fail Criteria • TJ measured at a maximum of 0.37 UI when measured at fBAUD/500 (for products running at 1.5Gb/s) o NOTE : Due to the nature of taking this measurement with the Clock-to-Data method, the specification requirement is aligned to that of the Clock-to-Data requirement of 3Gb/s products. 2.14.10.
Pass/Fail Criteria • TJ measured at a maximum of 0.37 UI when measured at fBAUD/500 (for products running at 3Gb/s) 2.14.12. TSG-12 : Gen2 (3Gb/s) DJ at Connector, Clock to Data, fBAUD/500 2.14.12.1. Device/Host Expected Behavior See sections 7.2.2.3.12 and 7.3 of Serial ATA Revision 2.6. Measurement Requirements • See sections 7.4.6 and 7.4.8 of Serial ATA Revision 2.6. • This test requirement is only applicable to products running at 3Gb/s.
2.15.2. RX-02 : Single-Ended Impedance (Obsolete) 2.15.2.1. Device/Host Expected Behavior See section 7.2.2.4.2 of Serial ATA Revision 2.6. Measurement Requirements • See section 7.4.23 of Serial ATA Revision 2.6. • This test requirement is only applicable to products running at 1.5Gb/s. For products which support 3Gb/s, this test is not required. • Testing of this requirement must be completed during a PHYRDY Interface Power State (see section 8.1. of SATA Revision 2.6).
2.15.4. RX-04 : Gen2 (3Gb/s) Common Mode Return Loss 2.15.4.1. Device/Host Expected Behavior See section 7.2.2.4.4 of Serial ATA Revision 2.6. Measurement Requirements • See section 7.4.10 of Serial ATA Revision 2.6. • Calibrate to the end of the SMA cables, but do NOT include (de-embed) the SMA to SATA PCB and the SATA connector, so the board and the SATA connector are INCLUDED with the product measurement. • This test requirement is only applicable to products running at 3Gb/s.
RX-05d RX-05e RX-05f 2.15.6. 1.2GHz-2.4GHz 2.4GHz-3.0GHz 3.0GHz-5.0GHz 10 4 4 (N/A for test Gen2m) RX-06 : Gen1 (1.5Gb/s) Differential Mode Return Loss 2.15.6.1. Device/Host Expected Behavior See section 7.2.2.2.3 of Serial ATA Revision 2.6. Measurement Requirements • See section 7.4.10 of Serial ATA Revision 2.6.
The following parameters are to be used for creating the appropriate input source involved in the RSG tests (see Table 31 in SATA Revision 2.6 for specification requirements): • No SSC • Pre-emphasis : 0dB • No CDR (Clock Data Recover unit) to be used for the jitter calibration. Real time scopes use a dataset derived clock, and BERTs use a 1.5 or 3 GHz square wave direct from the jitter source dependent on data rate. More details available in MOIs. • Rise/Fall Time : 100 ps (20/80%) 2.16.1.
2.16.2. RSG-02 : Gen2 (3Gb/s) Receiver Jitter Tolerance Test 2.16.2.1. Device/Host Expected Behavior See sections 7.2.2.6.8 and 7.3 of Serial ATA Revision 2.6. See parameter detail at beginning of RSG section. Measurement Requirements See sections 7.4.7 and 7.4.9 of Serial ATA Revision 2.6. This test requirement is only applicable to products running at 3Gb/s.
For products which support 3Gb/s, this requirement must be tested at both interface rates (1.5Gb/s and 3Gb/s). Note that the specification stipulates a Detection Threshold with value of Vthresh, where Vthresh is 50 ≤ Vthresh ≤ 200 in millivolts (mV) for 1.5Gb/s devices, and where Vthresh is 75 ≤ Vthresh ≤ 200 in millivolts (mV) for 3Gb/s devices. For the interests of the Interoperability Program, the measurements will only be taken to verify this requirement at the lower and upper limits.
Measurement Requirements See section 7.4.11 of Serial ATA Revision 2.6. This test is only run once at the maximum interface rate of the product (1.5Gb/s or 3Gb/s). Pass/Fail Criteria • Mean UIOOB measured to be between 646.67 ps and 686.67 ps over entire OOB burst 2.17.3. OOB-03 : COMINIT/RESET and COMWAKE Transmit Burst Length 2.17.3.1. Device/Host Expected Behavior See section 7.2.2.7.3 of Serial ATA Revision 2.6. Measurement Requirements See section 7.4.21 of Serial ATA Revision 2.6.
2.17.5. OOB-05 : COMWAKE Transmit Gap Length 2.17.5.1. Device/Host Expected Behavior See section 7.2.2.7.5 of Serial ATA Revision 2.6. Measurement Requirements • See section 7.4.21 of Serial ATA Revision 2.6. • This test is only run once at the maximum interface rate of the product (1.5Gb/s or 3Gb/s). • Note that the requirement within the specification is called out in UI.
Figure - 2 Example OOB-06 test stimulus and PUT response, nominal COMINIT/COMRESET, COMWAKE (Test stimulus top, yellow. PUT response bottom, purple.) 2) Detection Tests: Changing the COMWAKE gap values only, verify that the PUT continues to consistently enter speed negotiation for gap values of 155 and 165UIOOB (103.
Pass/Fail Criteria • OOB-06a - Verification of product COMWAKE response at 155UIOOB • OOB-06b - Verification of product COMWAKE response at 165UIOOB • OOB-06c - Verification of no product COMWAKE response at 45UIOOB • OOB-06d - Verification of no product COMWAKE response at 266UIOOB • If any of the above cases fails, this is considered a failure by the product. 2.17.7. OOB-07 : COMINIT/COMRESET Gap Detection Windows 2.17.7.1. Device/Host Expected Behavior See section 7.2.2.7.7 of Serial ATA Revision 2.6.
Figure - 4 Example OOB-07 test stimulus and PUT response, for nominal COMINIT/COMRESET gap (Test stimulus top, yellow. PUT response bottom, purple.) 2) Detection Tests: Changing the COMINIT/COMRESET gap values only, verify that the PUT continues to respond to gap values of 459 and 501UIOOB (306 and 334ns, respectively) 3) No-Detection Tests: Changing the COMINIT/COMRESET gap values only, verify that the PUT consistently DOES NOT respond to gap values of 259 and 791UIOOB (172.66 and 527.
• • Host: o OOB-07a - Verification of COMWAKE response at 459UIOOB o OOB-07b - Verification of COMWAKE response at 501UIOOB o OOB-07c - Verification of no COMWAKE response at 259UIOOB o OOB-07d - Verification of no COMWAKE response at 791UIOOB If any of the above cases fails, this is considered a failure by the product. 2.18. Port Multiplier Requirements (informative) Devices used for testing Port Multipliers shall be limited to HDD type devices.
2.18.2. PM-02 : General Status and Control Register (GSCR) Access 2.18.2.1. Expected Behavior See sections 16.4.1of Serial ATA Revision 2.6. GSCRs are accessed using the READ PORT MULTIPLIER and WRITE PORT MULTIPLIER commands with the PortNum field in the FIS27h Device field set to 15. The full range of register numbers addressable through these commands is 0 – 65535, however most are Reserved and only a handful are Mandatory. We use the Mandatory registers to verify that the GSCRs can be accessed.
2.18.3. PM-03 : Port Status and Control Register (PSCR) Access 2.18.3.1. Expected Behavior See sections 16.4.2 and 14.1 of Serial ATA Revision 2.6. Each device port in a Port Multiplier has a set of PSCRs associated with it. PSCRs are accessed using the READ PORT MULTIPLIER and WRITE PORT MULTIPLIER commands with the PortNum field in the FIS27h Device field set to the number of the port (range 0 – 14).
• • Verify that the reserved fields in each PSCR for all implemented ports except 0 contain all zero. Verify that PSCR(2) Bits [3:0] for all implemented ports except 0 contain 4h. On the port with the attached SATA device, check the DET field in PSCR(0) and confirm that it contains 3h. This confirms that communication has been established, and indirectly confirms that the two WRITE PORT MULTIPLIER were correctly executed.
For setup consistency, issue Soft Reset to Port F of the port multiplier before starting the test sequence. a) Determine whether low power modes are supported by the port multiplier. Issue COMRESET from the HBA port to the host port of the PM and allow time for the sequence to complete. Verify that the H-PM interface is in active state. Issue PMREQ_P to the device using the SPM field of the HBA SPM register or through a vendor specific method. Ensure that the H-PM interface goes to partial state.
Place the H-PM interface into partial state as described in step A. Issue the COMWAKE OOB signal as described in step B. Stop the bus analyzer or other device recording interface activity. Record the time between the end of the COMWAKE burst from the host to the end of the ALIGN burst following the COMWAKE burst from the PM. One execution of step a) is required for this test. Ten iterations each of steps b) and c) above are required for this test.
Attach and power up an HDD to a PM device port with a port number >0. a) Verify that the port multiplier supports issuing PMREQ to the host. Issue COMRESET from the HBA port to the host port of the PM and allow time for the sequence to complete. Check PM GSCR[64] bit 1. If bit 1 = 0, skip the rest of PM-06 and put out a message, “Port multiplier does not support issuing PMREQ to the host.” If bit 1 = 1, set PM GSCR[96] bit 1 = 1.
Measurement Requirements For setup consistency, issue Soft Reset to Port F of the port multiplier before starting the test sequence. a) Verify that the device supports HIPM. Attach an HDD to the selected device port. Initialize the PM-Dev interface. This can be done through the DET field of the SControl register of the device port. Issue an IDENTIFY DEVICE command to the device and check IDENTIFY DEVICE word 76 bit 9. If bit 9 = 1, then the device supports host (PM) initiated interface power management.
For setup consistency, issue Soft Reset to Port F of the port multiplier before starting the test sequence. a) Verify that the device supports DIPM Connect an HDD to a device port in the port multiplier. Initialize the PM-Dev interface for that port and verify that the interface is in active state. Check that the drive supports DIPM (IDENTIFY DEVICE Word 78 Bit 3 = 1), enable the DIPM feature in the drive using the SET FEATURES command, then issue a STANDBY IMMEDIATE command to the attached HDD.
2.18.9. PM-09 : Speed matching upon resume (H-PM interface) 2.18.9.1. Expected Behavior See section 8.4.3.2 of Serial ATA Revision 2.6. The quoted statement below refers to the situation in which a port has received COMWAKE after entering partial or slumber state: “Calibration and speed negotiation is bypassed since it has already been performed at power-on and system performance depends on quick resume latency. The device, therefore, shall transmit ALIGNP primitives at the speed determined at power-on.
test is FAIL. b) Verify that the H-PM interface running at reduced speed resumes at the reduced speed. If the interface speed before and after a power management sequence is the 1.5 Gb/s, the result is PASS. If the H-PM interface did not enter a low power state when requested or resumed at a different speed, then the result is FAIL. There is no N/A result for this test step. If all 10 results are PASS, then the test result is PASS. If there is a single FAIL result, then the result for this test is FAIL. 2.
b) Verify that the H-PM interface running at reduced speed resumes at the reduced speed. If the test methodology permits access to the PM PSCRs and the default rate on the PM-Dev interface is 3 Gb/s, then set the IPM field of the PM port SControl register to limit the interface speed to Gen1 speed. A vendor specific method may be used instead, if available. Issue COMRESET. Confirm that the PM-Dev interface speed is 1.5 Gb/s.
If all 10 PMREQ_P results are PASS, then the PMREQ_P test result is PASS. If there is a single FAIL result, then the result for this test is FAIL. Put out a message indicating a rate matching failure for PMREQ_P/COMWAKE sequence. If all 10 PMREQ_S results are PASS, then the PMREQ_S test result is PASS. If there is a single FAIL result, then the result for this test is FAIL. Put out a message indicating a rate matching failure for PMREQ_S/COMWAKE sequence. 2.18.11. PM-11 : Port Multiplier Reset Response 2.
• The port multiplier returns a FIS 34h with ERROR and ABRT bits = 1. 2.18.12. PM-12 : Device Port 0 Hot Plug with non-PM aware host software. 2.18.12.1. Expected Behavior When host software has no port multiplier support, it will not send a FIS to the PM Control Port under any circumstances. If device port 0 receives a COMINIT signal from an attached device, as will happen if a device is hot plugged, port 0 will complete the OOB sequence. The device is required to send a signature FIS34h at that point.
Connect a drive to device port 0 (drive power can be applied concurrently or beforehand) to the selected device port numbered >0. Do not initialize the interfaces of these two ports. Pass/Fail Criteria 1) Read the SError register for device port 0 and verify that bit 26 = 1 (this is the X bit for device port 0). For the selected device port numbered >0, check that the corresponding bit number in GSCR(32) = 1. (E.g., if the selected device port is 5, then check bit 5).
2.18.15.1. Expected Behavior When a port multiplier receives a FIS from the host system directed to a device port that is beyond the range of supported port numbers, it shall not respond with either R_OK or R_ERR. Instead, it shall send a SYNC primitive to the host system, terminating the FIS transfer. This test does not apply to a port multiplier that supports the full range of allowable device port numbers, 0-14.
• If the port multiplier is working properly, it should send a Register Device -> Host FIS containing the port multiplier signature as defined in SATA 2.6, 13.3.2.2 after the soft reset completes. 3. System Interoperability Tests The system interoperability tests are required tests above and beyond the tests described in the preceding sections of the document. This testing is required for the Device product type. No System Interoperability testing is required for Cable products. 3.1.
For device product testing, the host controllers used in the configurations must either be those identified above, or selected from the Integrators List as already approved products. A substitution of a host product from the Integrators List may only be a substitution of a product from the same SATA interface vendor (e.g.
3.2.2. SYS-01: System Interoperability Test Requirements 3.2.2.1. Data Pattern The data pattern used by System Interoperability test shall exactly reproduce the Long COMP pattern on the SATA interface. The host typically scrambles and encodes the data before it is transmitted on the SATA interface. The source data pattern shall be designed to take this into consideration such that the Long COMP pattern is still presented on the SATA interface. 3.2.2.2.
1. 2. 3. 4. 5. 6. 7. 8. First read of the copy, comes from the original data source, not the PUT The first write, using the data from the first read is written to the PUT The second read comes from the first write data on the PUT nd The second write comes from the second read, but writes to a 2 file location on the PUT …. th th The 39 read comes from the 38 write data on the PUT th th th The 40 write comes from the 39 read on the PUT, but writes to the 40 file location on the PUT.
Pass/Fail Criteria • PASS if all of the following are true, otherwise FAIL: The 8 KB Long COMP data pattern is verified to be correct and complete. The MD5 signature must match the SATA-IO Logo published MD5 signature 3.3.2. SYT-02 – Data pattern alignment 3.3.2.1. Device Expected Behavior The test tool shall present the first DWord of the Long COMP data pattern as the first Dword of a DATA FIS on the SATA interface.
• With a bus analyzer demonstrate a complete (no missing or additional) data pattern set for each device type is transferred on the SATA bus for each test tool request. Traces that filter the user data, but still indicate the FIS structure are acceptable. Reads of non-data set (file system reads) are allowed, but should be minimized Pass/Fail Criteria • A complete data pattern set for each device type is transferred on the SATA bus for each test tool request.
Pass/Fail Criteria • Directory of PUT showing no operating system files or Logs from test tool validation and the PUT validation showing the OS/drivers are identical (MD5 signatures of critical files are one such way) 4. Framed COMP Pattern See SATA Standard 2.6, ECN 009 “Long FRAMED COMP Pattern” This section defines the framed version of the COMP pattern, for use in RSG and Interoperability testing.
535: -D30.3+ 7E 0111100011 769: -K28.5+ BC 0011111010 771: -D30.3+ 7E 0111100011 1025: -K28.5+ BC 0011111010 1027: -D30.3+ 7E 0111100011 1048: - D3.7+ E3 1100011110 1049: -D12.0+ 0C 0011011011 1050: +D12.0- 0C 0011010100 1281: -K28.5+ BC 0011111010 1283: -D12.0+ 0C 0011011011 1284: +D12.0- 0C 0011010100 1307: -D20.2- 54 0010110101 1537: -K28.5+ BC 0011111010 1539: -D20.2- 54 0010110101 1564: -D20.2- 54 0010110101 1565: +D11.5+ AB 1101001010 1793: +K28.5- BC 1100000101 1795: +D11.5+ AB 1101001010 1822: +D11.
