User`s manual

DIGITAL-LOGIC AG MPC40/A/B/C, MPC41 Manual V1.4C
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4.9.1.2 Deep Sleep State
Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep
Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped
during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings
on Intel 855PM and Intel 855GM chipset-based platforms are as follows:
Intel® Pentium® M Processor Datasheet 14
4.9.1.2.1 Low Power Features
• Deep Sleep entry - DPSLP# and CPU_STP# are asserted simultaneously. The platform clock
chip will stop/tristate BCLK within 2 BCLKs +/- a few nanoseconds.
• Deep Sleep exit - DPSLP# and CPU_STP# are deasserted simultaneously. The platform clock
chip will drive BCLK to differential DC levels within 2-3 ns and starts toggling BCLK 2-6 BCLK periods later.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-started after DPSLP#
deassertion as described above. A period of 30 microseconds (to allow for PLL stabilization) must occur be-
fore the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be
deasserted to re-enter the Stop-Grant state. While in Deep Sleep state, the processor is incapable of re-
sponding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the sys-
tem bus while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to Stop-Grant state will result in unpredictable behavior.
4.9.1.3 Deeper Sleep State
The Deeper Sleep state is the lowest power state the processor can enter. This state is functionally identical
to the Deep Sleep state but at a lower core voltage. The control signals to the voltage regulator to initiate a
transition to the Deeper Sleep state are provided on the platform. Please refer to the platform design guides
for details.
4.9.1.4 Enhanced Intel® SpeedStep® Technology
The Intel Pentium M processor features Enhanced Intel SpeedStep® technology. Unlike previous implemen-
tations of Intel SpeedStep technology, this technology enables the processor to switch between multiple fre-
quency and voltage points instead of two. This will enable superior performance with optimal power savings.
Switching between states is software controlled unlike previous implementations where the GHI# pin is used
to toggle between two states. Following are the key features of Enhanced Intel SpeedStep technology:
• Multiple voltage/frequency operating points provide optimal performance at the lowest power.
• Voltage/Frequency selection is software controlled by writing to processor MSR’s (Model Specific Regis-
ters) thus eliminating chipset dependency.
— If the target frequency is higher than the current frequency, Vcc is ramped up by placing a
new value on the VID pins and the PLL then locks to the new frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the new
frequency and the Vcc is changed through the VID pin mechanism.
— Software transitions are accepted at any time. If a previous transition is in progress, the
new transition is deferred until its completion.
• The processor controls voltage ramp rates internally to ensure glitch free transitions.
• Low transition latency and large number of transitions possible per second.
— Processor core (including L2 cache) is unavailable for up to 10 µs during the frequency
transition
— The bus protocol (BNR# mechanism) is used to block snooping