User`s manual

DIGITAL-LOGIC AG MPC40/A/B/C, MPC41 Manual V1.4C
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4.10 INTEL 855GM: Grafic-Memory-Control Hub
4.10.1 Processor Host Interface
The GMCH is optimized for the Intel Pentium M processor. Key features of the Intel Pentium M
processor system bus (PSB) are:
• Source synchronous double pumped address
• Source synchronous quad pumped data
• System bus interrupt delivery
• Low voltage swing (Vtt = 1.05 V)
• Dynamic Power Down (DPWR#) support
• GMCH supports a 64-B cache line size
• Support for a 400-MHz system bus frequency. Dual processor is not supported
• Integrates AGTL+ termination resistors on all of the AGTL+ signals
• Supports 64-bit host bus addressing allowing the CPU to access the entire 4 GB of the GMCH memory ad-
dress space.
• A 12-deep, In-Order queue to support up to twelve outstanding pipelined address requests on the
host bus
• Drives DPWR# signal to the processor, which can then disable its sense amplifiers
• Supports only one outstanding defer cycle at a time to any particular I/O interface
• Host initiated I/O cycles are positively decoded to the GMCH configuration space and
subtractively decoded to the Hub Interface
• Host initiated memory cycles are positively decoded to DDR SDRAM
• Memory accesses initiated from the Hub Interface to DDR SDRAM will be snooped on the system
bus
4.10.1.1 Intel 855GM GMCH Host Bus Error Checking
The Intel 855GM GMCH does not generate nor check parity on Data, Address/Request, and Response
signals on the PSB.
4.10.1.2 Intel 855GM GMCH System Memory Interface
The GMCH System Memory Controller directly supports the following:
• One channel of PC1600/2100 SO-DIMM DDR SDRAM memory
• DDR SDRAM devices with densities of 128-Mb, 256-Mb, and 512-Mb technology
• Maximum System Memory with two, double-sided SO-DIMMs (four rows populated) supporting
up to 1 -GB system memory, and high density supporting up to 2-GB system memory
• Variable page sizes of 2 kB, 4 kB, 8 kB, and 16 kB. Page size is individually selectable for every
row and a maximum of 16 pages may be opened simultaneously
The GMCH System Memory interface supports a thermal throttling scheme to selectively throttle reads
and/or writes. Throttling can be triggered either by the on-die thermal sensor, or by preset write
bandwidth limits. Read throttle can also be triggered by an external input pin. The memory controller
logic supports aggressive Dynamic Row Power Down features to help reduce power and supports
Address and Control line Tri-stating when DDR SDRAM is in an active power down or in self refresh
state. The GMCH System Memory architecture is optimized to maintain open pages (up to 16-kB page size)
across multiple rows. As a result, up to 16 pages across four rows is supported. To complement this, the
GMCH will tend to keep pages open within rows, or will only close a single bank on a page miss. The
GMCH supports only four bank memory technologies.