User`s manual

DIGITAL-LOGIC AG MPC40/A/B/C, MPC41 Manual V1.4C
52
4.10.2 Intel 855GM GMCH Internal Graphics
The GMCH IGD provides a highly integrated graphics accelerator delivering high performance 2D, 3D,
and video capabilities. With its interfaces to UMA using a DVMT configuration, an analog display, a
LVDS port, and two digital display ports (e.g. flat panel), the GMCH can provide a complete graphics
solution.
The GMCH also provides 2D hardware acceleration for block transfers of data (BLTs). The BLT engine
provides the ability to copy a source block of data to a destination and perform raster operations (e.g.,
ROP1, ROP2, and ROP3) on the data using a pattern, and/or another destination. Performing these
common tasks in hardware reduces CPU load, and thus improves performance.
High bandwidth access to data is provided through the System Memory interface. The GMCH uses
Tiling architecture to increase System Memory efficiency and thus maximize effective rendering
bandwidth. The Intel 855GM GMCH also improves 3D performance and quality with 3D Zone
Rendering technology.
The GMCH has four display ports, one analog and three digital. These provide support for a
progressive scan analog monitor, a dedicated dual channel LVDS LCD panel, and two DVO devices.
Each port can transmit data according to one or more protocols. The DVO ports are connected to an
external device that converts one protocol to another. Examples of this are TV-out encoders, external
DACs, LVDS transmitters, and TMDS transmitters. Each display port has control signals that may be
used to control, configure and/or determine the capabilities of an external device. The data that is sent
out the display port is selected from one of the two possible sources, Pipe A or Pipe B.
4.10.2.1 Intel 855GM GMCH Analog Display Port
Intel 855GM GMCH has an integrated 350-MHz, 24-bit RAMDAC that can directly drive a progressive
scan analog monitor pixel resolution up to 1600x1200 at 85-Hz refresh and up to 2048x1536 at 72-Hz
refresh. The Analog display port can be driven by Pipe A or Pipe B.
4.10.2.2 Intel 855GM GMCH Integrated DVO Ports
The DVO B/C interface is compliant with the DVI Specification 1.0. When combined with a DVI
compliant external device (e.g. TMDS Flat Panel Transmitter, TV-out encoder, etc.), the GMCH
provides a high-speed interface to a digital or analog display (e.g. flat panel, TV monitor, etc.).
The GMCH provides two DVO ports that are each capable of driving a 165-MHz pixel clock at the DVO
B or DVO C interface. When DVO B and DVO C are combined into a single DVO port, then an
effective pixel rate of 330 MHz can be achieved. The DVO B/C ports can be driven by Pipe A or Pipe
B. If driven on Pipe B, then the LVDS port must be disabled.
4.10.3 Hub Interface
A proprietary interconnect connects the GMCH to the ICH4-M. All communication between the GMCH
and the ICH4-M occurs over the Hub Interface 1.5. The Hub Interface runs at 66 MHz (266-MB/s).
4.10.4 Address Decode Policies
Host initiated I/O cycles are positively decoded to the GMCH configuration space and subtractively
decoded to Hub Interface. Host initiated System Memory cycles are positively decoded to DDR
SDRAM and are again subtractively decoded to Hub Interface if under 4 GB. System Memory accesses
from Hub Interface to DDR SDRAM will be snooped on the PSB.