User`s manual

DIGITAL-LOGIC AG MPC40/A/B/C, MPC41 Manual V1.4C

Power Management Logic ACPI 2.0 compliant

ACPI-defined power states (C1–C2, S3–S5 )

Supports Desktop S1 state (like C2 state, only STPCLK# active)

ACPI power management timer

PCI PME# support

SMI# generation

All registers readable/restorable for proper resume from 0V susp.states

External Glue Integration Integrated pull-up, pull-down and series termination resistors on IDE, proc-

essor interface

Integrated Pull-down and Series resistors on USB

Enhanced Hub Interface Buffers Improve Routing flexibility (Not available with all MemController Hubs)

Firmware Hub (FWH) Interface Supports BIOS memory size up to 8 MB

Low Pin Count (LPC) Interface Supports two Master/DMA devices.

Enhanced DMA Controller Two cascaded 8237 DMA controllers

PCI DMA: Supports PC/PCI — Includes two PC/PCI REQ#/GNT# pairs

Supports LPC DMA

Supports DMA collection buffer to provide Type-F DMA performance for all

DMA channels

Real-Time Clock 256-byte battery-backed CMOS RAM

System TCO Reduction Cir-

cuits

Timers to generate SMI# and Reset upon detection of system hang

Timers to detect improper processor reset

Supports ability to disable external devices

SMBus New: Hardware packet error checking

New: Supports SMBus 2.0 Specification

Host interface allows processor to communicate via SMBus

Slave interface allows an ext. microcontroller to access system resources

Compatible with most 2-wire components that are also I2C compatible

GPIO TTL, open-drain, inversion