User`s manual

DIGITAL-LOGIC AG MPC40/A/B/C, MPC41 Manual V1.4C

4.15 FIREWIRE IEEE1394

Description:

The Texas Instruments TSB43AB22 device is an integrated 1394a-2000 OHCI PHY/link-layer controller

(LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management

Interface Specification,

IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface Specification. It is

capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and

400M bits/s. The TSB43AB22 device provides two 1394 ports that have separate cable bias (TPBIAS). The

TSB43AB22 device also supports the IEEE Std 1394a-2000 power-down features for battery-operated appli-

cations and arbitration enhancements.

Features:

The TSB43AB22 device supports the following features:

- Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance and IEEE Std 1394a

- Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394

- Compliant with Intel Mobile Power Guideline 2000

- Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed

concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume

- Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s

- Cable ports monitor line conditions for active connection to remote node

- Cable power presence monitoring

- PCI burst transfers and deep FIFOs to tolerate large host latency

- External cycle timer control for customized synchronization

- Extended resume signaling for compatibility with legacy DV components

- PHY-Link logic performs system initialization and arbitration functions

- PHY-Link encode and decode functions included for data-strobe bit level encoding

- PHY-Link incoming data resynchronized to local clock

- Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200 and 400M bits/s

Node power class information signaling for system power management

- Serial ROM interface supports 2-wire serial EEPROM devices

- Register bits give software control of contender, power class, link active control bit, and IEEE Std

1394a

- PCI and CardBus register support

- Isochronous receive dual-buffer mode

- Out-of-order pipelining for asynchronous transmit requests

- Register access fail interrupt when the PHY SCLK is not active

- PCI power-management D0, D1, D2, and D3 power states

- Initial bandwidth available and initial channels available registers