User`s guide

18 • Registers

3.2 DI_CSR: DI Control & Status Register

Digital input control and status checking is done by this register.

Address: BASE + 00

Attribute: READ/WRITE

Data Format:

Bit # 3~0 DI_HND_SHK DI_CLK_SEL DI_32

Bit # 7~4 0

PA_TERM_OF

DI_WAIT_TRI

-- (1)

Bit # 11~8 DI_FIFO_FULL DI_OVER DI_FIFO_CLR DI_EN

Bit # 15~12 - - - DI-FIFO_EMPTY

Bit # 31~16 Don’t Cared

(1) This bit is different between Rev.A and Rev.B.

DI_32 (R/W)

0: Input port is not 32-bit wide (16-bit or 8-bit wide)

1: Input port is 32-bit wide, PORTB is configured as the extension of PORTA.

That means PORTA is input lines 0…15, and PORTB is input lines 16…31.

All the PORTB control signals are disabled.

DI_CLK_SEL (R/W)

00: use timer0 output as input clock

01: use 20MHz clock as input clock

10: use 10MHz clock as input clock

11: use external clock (DI_REQ) as input clock

DI_HND_SHK (R/W)

0: No handshaking

1: REQ/ACK handshaking mode

DI_WAIT_TRIG (R/W)

0: delay input sampling until DITRIG is active

1: start input sampling immediately

PA_TERM_OFF (R/W)

0: PORTA terminator ON

1: PORTA terminator OFF

DI_EN (R/W)

0: Disable digital inputs

1: Enable digital inputs