User`s guide

36 • Operation Theory
Notes: When the DMA function of digital input starts, the input data will be
stored in the FIFO of the cPCI/PCI-7300A. The data then transfer to
system memory i f PCI bus is available. If the speed of translation from
external device to the FIFO on board is higher than that from FIFO to
system memory or the PCI bus is busy for a long time, the FIFO
become full and overrun situation occurs after the next data being
written to the input FIFO. Users should check the overrun status to
see whether the overrun occurs or not. Some input data will lost when
the input FIFO is overrun.
Notes: The overrun occurs when the DMA idle time (from the end of DMA
transfer N to the start of DMA transfer N+1) is longer than the
on-board FIFO buffer time. The FIFO size is 16K sample, so it has 1.6
ms buffer time for 10MHz sampling rate if the FIFO is empty when last
DMA is complete. Users may try different DMA buffer size to see how
the DMA buffer size affects the overall performance. Generally, the
larger DMA size the less overhead, however, the process time
required between DMAs also increases.
4.10.2 Digital Input DMA in External Clock Mode
The digital input data transfer can be controlled by external strobe, which is
from pin-83 DI-REQ of CN1. The operation sequence is very similar to Internal
Clock. The only difference is the clock source comes from the outside
peripheral devices. The operations sequence of digital input with external clock
are listed:
1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width.
2. Enable or disable the active terminators.
3. Define the input sampling rate as external clock. Connect the external clock
to the input pin DI-REQ.
4. Define the starting mode to be NoWait or WaitTRIG.
5. The digital input data are stored in the input FIFO after a DI command is
issued and waiting for DI-TRIG signal if in WaitTRIG mode..
6. The data saved in FIFO will transfer to system memory of your computer
directly and automatically by bus mastering DMA.
7. The DI-ACK signal indicates the status of the cPCI/PCI-7300A’s input FIFO
is in external clock mode. When the digital input circuit of cPCI/PCI-7300A
is enabled and its FIFO is not almost full, the DIACK signal will remain
asserted. If the external device does not transfer data according to the
status of DI-ACK, the on-board FIFO could be full and data could be lost.