User`s guide

22  Registers Format
3.3 FIFO Enable Register
The FF_ENA bit directly control FIFO memory. Clear FF_ENA bit to ‘0’
can always reset the FIFO and any read operation to the A/D FIFO port
will get value ‘0’. Set FF_ENA bit to ‘1’ can enable the FIFO. Note that
FF_ENA status can be read back from Base+13.
Address : BASE + 8
Attribute : write only
Data Format:
Bit 7 6 5 4 3 2 1 0
X X X X X X X FF_ ENA
FF_ENA: FIFO Enable Control
0: FIFO Disable
1: FIFO Enable
3.4 Gain Control Register
The gain control register is used to adjust the analog input ranges for A/D
channels. Table 4.2 shows the relationship between the register data,
gain value and the A/D input range.
Address : BASE + 9
Attribute : write only
Data Format:
Bit 7 6 5 4 3 2 1 0
X X X X X X G1 G0
G1 G0 Gain A/D input Range
0 0 1 - 10V ~ +10V
0 1 2 - 5V ~ +5V
1 0 4 - 2.5V ~ +2.5V
1 1 8 - 1.25V ~ +1.25V