User`s guide

Operation Theory • 49
5.3 General Purpose Timer/Counter Operation
An independent 16-bit up/down timer/counter is designed in the FPGA for user
applications. Fig 19 shows a simplified model of the timer/counter on the 9116
series card. It has the following features:
Counter
UP/DOWN(pin98)
C
G
O
CLK(pin96)
Gate(pin97)
OUT(pin48)
Initial
Count
load
Count
read back
CPCI-9116
D0
D15
Q0
Q15
Mode
control
Controller
Figure 19: General-purpose Timer/Counter model (CLK, Gate, UP/DOWN
Counter can be software programmed externally or internally)
• Count up/Count down controlled by hardware or software (low or 0: counts
down, high or 1: counts up)
• Programmable counter CLK source selection (Internal 24MHz or External
CLK input up to 20MHz)
• Programmable Gate selection (Internal or External. For Internal control,
you can disable counting only by software. For External gate control, either
software or setting Gate = low on pin 97 of J1 disables the counting)
• Initial Count can be loaded from software
• Current count value can be read with software without affecting circuit
operation