cExpress-BL User’s Manual Manual Revision: 1.
Revision History Revision Description Date By 1.
Preface Copyright 2015 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.
Table of Contents Revision History ............................................................................................................ 2 Preface............................................................................................................................ 3 1 Introduction ............................................................................................................ 6 2 Specifications ......................................................................................
Smart Embedded Management Agent (SEMA) ................................................ 37 5.1 6 Board Specific SEMA Functions ................................................................................................. 38 System Resources ................................................................................................. 40 6.1 System Memory Map................................................................................................................. 40 6.
1 Introduction The cExpress-BL is a COM Express® COM.0 R2.1 Type 6 Compact size module featuring the 64-bit 5th Generation Intel® Core™ i7/i5/i3 and Intel® Celeron® Ultra-Low TDP processors (formerly “Broadwell-U”) with CPU, memory controller, graphics processor and I/O hub on a single chip.
2 Specifications 2.1 Core System ¾ CPU: 5th Generation Intel® Core™ processor SoC (formerly “Broadwell-U”) • Intel® Core™ i7-5650U 2.2 GHz (3.2 GHz Turbo), 15W (2C/GT3) • Intel® Core™ i5-5350U 1.8 GHz (2.9 GHz Turbo), 15W (2C/GT3) • Intel® Core™ i3-5010U 2.1 GHz (no Turbo), 15W (2C/GT2) • Future 5th Generation Intel® Celeron® processor Supporting: Intel® VT, Intel® TXT, Intel® SSE4.2, Intel® HT Technology, Intel® 64 Architecture, Execute Disable Bit, Intel® Turbo Boost Technology 2.
2.4 Audio ¾ Integrated: Intel® HD Audio integrated on SoC ¾ Codec: Realtek ALC886 on Express-BASE6 Reference Carrier Board 2.5 LAN ¾ Integrated: MAC integrated on SoC ¾ Intel PHY: Intel® Ethernet Controller i218LM ¾ Interface: 10/100/1000 GbE connection 2.6 Multi I/O and Storage ¾ I/O Hub: Integrated on SOC ¾ USB: 2x USB 3.0 ports (USB0,1) and 6x USB 2.0 ports (USB2,3,4,5,6,7) ¾ SATA: 4x SATA 6Gb/s ports ¾ GPIO: 4 GPO and 4 GPI 2.
2.11 Power Specifications ¾ Power Modes: ¾ Standard Voltage Input: ATX = 12V±5% / 5Vsb ±5% or AT = 12V±5% ¾ Wide Voltage Input: ATX = 5~20 V / 5Vsb ±5% or AT = 5 ~20V ¾ Power Management: ACPI 4.0 compliant, Smart Battery support ¾ Power States: supports C1-C6, S0, S3, S4, S5 (Wake-on-USB S3/S4, WoL S3/S4/S5) ¾ ECO mode: supports deep S5 for 5Vsb power saving 2.
2.
2.17 Mechanical Drawing connectors on bottom side Top View Side View All tolerances ± 0.05 mm Other tolerances ± 0.
3 Pinouts and Signal Descriptions 3.1 AB/CD Pin Definitions The cExpress-BL is a Type 6 module supporting USB 3.0 upgrade signals and DDI channels on the CD connector All pins in the COM Express specification are described, including those not supported on the cExpress-BL. Those not supported on the cExpress-BL module are crossed out.
Row A Row B Row C Row D Pin Name Pin Name Pin Name Pin Name A36 USB6- B36 USB7- C36 DDI3_CTRLCLK_AUX+ D36 DDI1_PAIR3+ A37 USB6+ B37 USB7+ C37 DDI3_CTRLDATA_AUX- D37 DDI1_PAIR3- A38 USB_6_7_OC# B38 USB_4_5_OC# C38 DDI3_DDC_AUX_SEL D38 RSVD A39 USB4- B39 USB5- C39 DDI3_PAIR0+ D39 DDI2_PAIR0+ A40 USB4+ B40 USB5+ C40 DDI3_PAIR0- D40 DDI2_PAIR0- A41 GND (FIXED) B41 GND (FIXED) C41 GND (FIXED) D41 GND (FIXED) A42 USB2- B42 USB3- C42 DDI3_PAIR1+ D42
Row A Row B Row C Row D Pin Name Pin Name Pin Name Pin Name A80 A81 GND (FIXED) B80 B81 GND (FIXED) LVDS_B_CK+ C80 C81 GND (FIXED) PEG_RX9+ D80 D81 GND (FIXED) PEG_TX9+ A82 LVDS_A_CKLVDS_I2C_CK /eDP_AUX+ * LVDS_I2C_DAT /eDP_AUX- * B82 LVDS_B_CKLVDS_BKLT_CTRL /eDP_BKLT_CTRL * C82 PEG_RX9- D82 PEG_TX9- RSVD D83 RSVD B84 VCC_5V_SBY GND D84 GND A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10+ D85 PEG_TX10+ A86 RSVD RSVD /eDP_HPD * B86 VCC_5V_SBY C86 PEG_RX10- D86 PEG_TX10
3.2 Signal Description Terminology The following terms are used in the COM Express AB/CD Signal Descriptions below. I Input to the Module O Output from the Module I/O Bi-directional input/output signal OD Open drain output I 3.3V Input 3.3V tolerant I 5V Input 5V tolerant O 3.3V Output 3.3V signal level O 5V Output 5V signal level I/O 3.3V Bi-directional signal 3.3V tolerant I/O 5V Bi-directional signal 5V tolerant I/O 3.3Vsb Input 3.
3.3 AB Signal Descriptions 3.3.1 Audio Signals Signal Pin # Description I/O AC_RST# / HDA_RST# A30 Reset output to codec, active low. O 3.3VSB AC_SYNC / HDA_SYNC A29 Sample-synchronization signal to the codec(s). O 3.3V AC_BITCLK / HDA_BITCLK A32 Serial data clock generated by the external codec(s). I/O 3.3V AC _SDOUT / HDA_SDOUT A33 Serial TDM data output to the codec. O 3.3V AC _SDIN[2:0] HDA_SDIN[2:0] B28 B30 Serial TDM data inputs from up to 3 codecs. I/O 3.3VSB 3.3.
3.3.
3.3.4 Gigabit Ethernet Gigabit Ethernet Pin # Description I/O GBE0_MDI0+ GBE0_MDI0GBE0_MDI1+ GBE0_MDI1GBE0_MDI2+ GBE0_MDI2GBE0_MDI3+ GBE0_MDI3- A13 A12 A10 A9 A7 A6 A3 A2 Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following: I/O Analog GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. O 3.
3.3.6 PCI Express Signal Pin # Description I/O PCIE_TX0+ PCIE_TX0- A68 A69 PCI Express channel 0, Transmit Output differential pair. O PCIE AC coupled on Module PCIE_RX0+ PCIE_RX0- B68 B69 PCI Express channel 0, Receive Input differential pair. I PCIE AC coupled off Module PCIE_TX1+ PCIE_TX1- A64 A65 PCI Express channel 1, Transmit Output differential pair. O PCIE AC coupled on Module PCIE_RX1+ PCIE_RX1- B64 B65 PCI Express channel 1, Receive Input differential pair.
3.3.9 USB Signal Pin # Description I/O USB0+ USB0- A46 A45 USB differential data pairs for Port 0 I/O 3.3VSB USB 1.1/ 2.0 compliant USB1+ USB1- B46 B45 USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant USB2+ USB2- A43 A42 USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant USB3+ USB3- B43 B42 USB differential data pairs for Port 2 I/O 3.3VSB USB 1.1/ 2.0 compliant USB4+ USB4- A40 A39 USB differential data pairs for Port 3 I/O 3.
3.3.10 USB Root Segmentation 3.3.11 SPI (BIOS only) Signal Pin # Description I/O SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V.
3.3.12 Miscellaneous Signal Pin # Description I/O SPKR B32 Output for audio enunciator, the “speaker” in PC-AT systems O 3.3V WDT B27 Output indicating that a watchdog time-out event has occurred. O 3.3V THRM# B35 Input from off-module temp sensor indicating an overtemp situation. I 3.3V THERMTRIP# A35 Active low output indicating that the CPU has entered thermal shutdown. O 3.3V FAN_PWMOUT B101 Fan speed control.
Signal Pin # Description I/O PU/PD Comment GPO[3] B63 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET output low GPI[0] A54 General purpose input pins. Pulled high internally on the module. I 3.3V PU 10K 3.3V GPI[1] A63 General purpose input pins. Pulled high internally on the module. I 3.3V PU 10K 3.3V GPI[2] A67 General purpose input pins. Pulled high internally on the module. I 3.3V PU 10K 3.3V GPI[3] A85 General purpose input pins.
Signal Pin # Description I/O PU/PD BATLOW# A27 Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low, or may be used to signal some other external power-management event. I 3.3VSB PU 10k 3.3VSB LID# LID button. Low active signal used by the ACPI operating system for a LID switch. I OD 3.3VSB PU 10k 3.3VSB Emulated on GPIO (BIOS) SLEEP# Sleep button.
3.4 CD Signal Descriptions 3.4.1 USB 3.
3.4.3 DDI Channels DDI 1 Signal Pin Description I/O DDI1_PAIR0+ DDI1_PAIR0DDI1_PAIR1+ DDI1_PAIR1DDI1_PAIR2+ DDI1_PAIR2DDI1_PAIR3+ DDI1_PAIR3DDI1_PAIR4+ DDI1_PAIR4DDI1_PAIR5+ DDI1_PAIR5DDI1_PAIR6+ DDI1_PAIR6- D26 D27 D29 D30 D32 D33 D36 D37 C25 C26 C29 C30 C15 C16 Digital Display Interface1 differential pairs O PCIE DDI1_HPD C24 Digital Display Interface Hot-Plug Detect I PCIE DDI1_CTRLCLK_AUX+ D15 IF DDI1_DDC_AUX_SEL is floating I/O PCIe DP1_AUX+ IF DDI1_DDC_AUX_SEL pulled high I/O OD 3.
DDI 2 Signal Pin Description DDI2_PAIR0+ DDI2_PAIR0DDI2_PAIR1+ DDI2_PAIR1DDI2_PAIR2+ DDI2_PAIR2DDI2_PAIR3+ DDI2_PAIR3- D39 D40 D42 D43 D46 D47 D49 D50 Digital Display Interface2 differential pairs DDI2_HPD D44 DDI2_CTRLCLK_AUX+ C32 DDI2_CTRLCLK_AUX- DDI2_DDC_AUX_SEL C33 I/O PU/PD Comment IF DDI2_DDC_AUX_SEL is floating I/O PCIe DP2_AUX+ IF DDI2_DDC_AUX_SEL pulled high I/O OD 3.
3.4.
3.4.
Signal Pin PEG_TX15+ PEG_TX15- D101 D102 PEG_LANE_RV# D54 3.4.6 Description I/O PCI Express Graphics lane reversal input strap. Pull low on the Carrier board to reverse lane order. I 1.05V PU/PD Comment Not supported Module Type Definition Signal Pin # Description I/O TYPE0# TYPE1# TYPE2# C54 C57 D57 The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are noconnects (NC).
4 Connector Pinouts on Module This chapter describes connectors and pinouts, LEDs and switches that are used on the module but are not included in the PICMG standard specification ¾ Connector and LED Locations XDP 60-pin to CPU CPU Keep out CD BIOS Defaults Reset Switch AB cExpress-BL LED3 LED1 4-pin Fan LED2 FAN 40-pin Debug Connector Page 31
4.
40-pin Debug Connector Pin Definition on the COM Express Module ¾ Pin Interface Signal Remark Pin Interface Signal 1 SPI Program interface VCC_SPI_IN SPI Power Input from flash tool to module.
4.2 Status LEDs To facilitate easier maintenance, status LED’s are mounted on the board. ¾ LED Descriptions Name Color Connection Function LED1 Blue BMC output Power Sequence Status Code (BMC) Power Changes, RESET (see 5.1.
4.3 XDP Debug header The debug port is a connection into a target-system environment that provides access to JTAG, run control, system control, and observation resources. The XDP target system connector is a Samtec™ 60-pin BSH-030-01 series connector.
4.4 Fan Connector ¾ Connector Type: JVE 24W1125A-04M00 ¾ Pin Assignment Name Signal Description 1 BMC_FAN_OUT FAN_PWMOUT 2 BMC_FAN_PWM_IN FAN_TACHIN 3 GND Ground 4 P5V_S 5V 4.5 BIOS Setup Defaults Reset Button To perform a hardware reset of BIOS default settings, perform the following steps: 1. Shut down the system. 2. Press the BIOS Setup Defaults RESET Button continuously and boot up the system. You can release the button when the BIOS prompt screen appears 3.
5 Smart Embedded Management Agent (SEMA) The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality. The microcontroller communicates via the System Management Bus with the CPU/chipset. The following functions are implemented: ‧ Total operating hours counter. Counts the number of hours the module has been run in minutes. ‧ On-time minutes counter. Counts the seconds since last system start. ‧ Temperature monitoring of CPU and board temperature.
5.1 Board Specific SEMA Functions 5.1.1 Voltages The BMC of the cExpress-BL implements a voltage monitor and samples several onboard voltages. The voltages can be read by calling the SEMA function “Get Voltages”. The function returns a 16-bit value divided into high-byte (MSB) and low-byte (LSB). 5.1.2 ADC Channel Voltage Name Voltage Formula [V] 0 +V1.5S (MSB<<8 + LSB) x 3.3 / 1024 1 +VCORE (MSB<<8 + LSB) x 3.3 / 1024 2 +V1.05S (MSB<<8 + LSB) x 3.3 / 1024 3 +V3.3A (MSB<<8 + LSB) x 1.
5.1.4 Exception Codes In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore, a “Clear Exception Code” command is not needed or supported. 5.1.
6 System Resources 6.1 System Memory Map Address Range (decimal) Address Range (hex) Size Description (4GB-2MB) FFE00000 – FFFFFFFF 2 MB High BIOS Area (4GB-18MB) – (4GB-17MB-1) FEE00000 – FEEFFFFF 1 MB MSI Interrupts (4GB-20MB) – (4GB-19MB-1) FEC00000 – FECFFFFF 1 MB APIC Configuration Space 15MB – 16MB F00000 – FFFFFF 1 MB ISA Hole 1MB -15MB 100000 - EFFFFF 14MB Main Memory 0K –1MB 00000 – FFFFFF 1MB DOS Compatibility Memory 6.
6.
Hex Range Device 3F0-3F7 Available 3F8-3FF Serial port 1 4D0 Master PIC Edge/Level Trigger register 4D1 Slave PIC Edge/Level Trigger register CF8-CFB PCI configuration address register (32 bit I/O only) CF9 Reset Control register (8 bit I/O) CFC-CFF PCI configuration data register F040 Smbus base address for SB. 1C00 GPIO Base Address for SB 1800 PM (ACPI) Base Address for SB 1860 Alias for ICH TCO base address.
6.
IRQ# Typical Intterupt Resource Connected to Pin Available 11 Serial Port 4 (COM4) IRQ11 via SERIRQ / PIRQ Note (1) 12 PS/2 Mouse IRQ12 via SERIRQ / PIRQ Note (1) 13 Math Processor N/A Note (1) 14 Primary IDE controller IRQ14 via SERIRQ / PIRQ Note (1) 15 Secondary IDE controller IRQ15 via SERIRQ / PIRQ Note (1) 16 N/A P.E.G Root Port,Intel HDA, PCIE Port Note (1) 0/1/2/3/4/5/6, EHCI Conterller #2 , I.G.D ,XHCI Controller 17 N/A PCIE Port 0/1/2/3/4/5/6, P.E.
6.5 PCI Configuration Space Map Bus Number Device Number Function Number Routing Description 00h 00h 00h N/A Intel host Bridge 00h 02h 00h Internal Intel I.G.
6.6 PCI Interrupt Routing Map INT Line P.E.
7 BIOS Setup 7.1 Menu Structure This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.
7.2 Main The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below the screen shot of this menu for details of the submenus and settings. 7.2.1 Main > System Information Feature Options Description BIOS Version Info only ADLINK BIOS version. Build Date and Time Info only ADLINK date the BIOS was build. 7.2.
7.2.5 Main >System Management > Board Information Board Information Info only SEMA Firmware Read only Display SEMA Firmware. Read only Display SEMA firmware build date. Read only Display SEMA boot loader. Read only Display SEMA boot loader build date. Hardware Version Read only Display SEMA hardware Version. Serial Number Read only Display SEMA serial Number. Manufacturing Date Read only Display SEMA manufacturing date. Last Repair Date Read only Display SEMA last repair date.
Feature Options Description V3.30 Read only Display actual voltage of the V3.30. VMEM Read only Display actual voltage of the VMEM. V5.00 Read only Display actual voltage of the V5.00. VIN Read only Display actual voltage of the VIN. AIN7 Read only Display actual voltage of the AIN7. 7.2.
7.2.11 System Management > LVDS Backlight Feature Options LVDS Backlight Info only LVDS Backlight Bright 255 Description The value range starts by 0 and ends by 255. 7.2.12 System Management > Smart Fan Feature Options Description Smart Fan Info only CPU Smart FanTemperature Source CPU Sensor System Sensor Select CPU smart fan source. CPU Fan Mode AUTO (Smart Fan) Fan Off Fan On Select CPU Fan Mode.
7.3 Advanced Menu This menu contains the settings for most of the user interfaces in the system. 7.3.1 Advanced > CPU Submenu Feature Options Description CPU Info only Manufacturer, model, speed CPU Signature Info only Display CPU Signature. Microcode Patch Info only Display Microcode Patch. Max CPU speed Info only Display Max CPU speed. Min CPU speed Info only Display Min CPU speed. CPU Speed Info only Display CPU Speed. Processor Cores Info only Display Processor Cores.
Feature Options Description CPU C7 Report Disabled CPU C7 CPU C7S Enable / Disable CPU C7 report to OS. C1 State auto undemotion Disabled Enabled Un-demotion from Demoted C1 C3 State auto undemotion Disabled Enabled Un-demotion from Demoted C3 ACPI T State Disabled Enabled Enable / Disable ACPI T state support. CPU DTS Disabled Enabled Enable / Disable CPU DTS. 7.3.
Feature Options Description IGfx Frequency Info only Display IGfx Frequency. Graphics Turbo IMON Current Number entry field Graphics turbo IMON current values supported (14-31). Primary Display Auto IGFX PEG PCIE Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select SG for Switchable Gfx. Primary PCIE Auto PCIE1 PCIE2 PCIE3 PCIE4 PCIE5 PCIE6 PCIE7 Select PCIE0/PCIE1/PCIE2/PCIE3/PCIE4/PCIE5/PCIE6/PCIE7 Graphics device should be Primary PCIE.
Feature Options Description 1920X1200 1440X900 1600X900 1024X768 LVDS2 1280X800 1920X1080 2048X1536 Active LFP No LVDS Edp Port-A Select the Active LFP Configuration. Panel Color Depth 18 Bit 24 Bit Select the LFP Panel Color Depth Panel Scaling Auto Off Force Scaling Select the LCD panel scaling option used by the Internal Graphics Device. GT – Power Management Control Info only GT Info Info only Display GT info of Intel Graphics.
Feature Options Description RAID1 Enabled Disabled Enable / Disable RAID1 feature. RAID10 Enabled Disabled Enable / Disable RAID10 feature. RAID5 Enabled Disabled Enable / Disable RAID5 feature. Intel Rapid Recovery Technology Enabled Disabled Enable / Disable Intel Rapid Recovery Technology. OROM UI and BANNER Enabled Disabled If enabled, then the OROM UI is shown. Otherwise, no OROM banner or information will be displayed if all disks and RAID volumes are Normal.
7.3.7 Advanced > USB Submenu Feature Options USB Module Version Info only USB Devices Info only X Drive, X Keyboards, X Mouse, X Hubs Legacy USB Support Enabled Disabled Auto Enables legacy USB support. Auto option disables legacy support if no USB devices are connected. Disable option will keep USB devices available only for EFI applications and setup. XHCI Hand-off Enabled Disabled This is a workaround for OSes without XHCI hand-off support.
7.3.9 Advanced > Network Submenu Feature Options Description Network Stack Info only Network Stack Enabled Disabled Enable/Disable UEFI network stack. PCH LAN Controller Enabled Disabled Enable / Disable onboard NIC. Wake on LAN Enabled Disabled Enable / Disable integrated LAN to wake the system. (The Wake On LAN cannot be disabled if ME is on at Sx state. AMT Configuration Info only Intel AMT Enabled Disabled Enable/Disable Intel (R) Active Management Technology BIOS Extension.
Feature Options Description 64 PCI Bus Clocks 96 PCI Bus Clocks 128 PCI Bus Clocks 160 PCI Bus Clocks 192 PCI Bus Clocks 224 PCI Bus Clocks 248 PCI Bus Clocks VGA Palette Snoop Disabled Enabled Allow PCI cards that do not contain their own VGA color palette to access the video core’s palette PERR# Generation Disabled Enabled Enables or Disables PCI Device to Generate PERR#. SERR# Generation Disabled Enabled Enables / Disables PCI Device to Generate SERR#.
7.3.11 Advanced > PCI and PCIe > PCH-PCIe Configuration Feature Options Description PCH-PCIe Configuration Info only PCI Express Clock Gating Disable Enable Enable / Disable PCI Express Clock Gating for each root port. DMI Link ASPM Control Disable Enable The control of Active State Power Management on both NB side and SB side of the DMI Link. DMI Link Extended Synch Control Disable Enable The control of Extended Synch on SB side of the DMI Link.
Feature Options Description SENFE Disable Enable Enable / Disable Root PCI Express System Error on Non-Fatal Error. SECE Disable Enable Enable / Disable Root PCI Express System Error on Correctable Error. PME SCI Disable Enable Enable / Disable PCI Express PME SCI. Hot Plug Disable Enable Enable / Disable PCI Express Hot Plug. PCIe Speed Auto Gen1 Gen2 Select PCI Express port speed. Detect Non-Compiance Disable Enable Detect Non-Compliance PCI Express Device.
Feature Serial Port 2 Configuration Serial Port Device Settings Change Settings N5104D Super IO Configuration Serial Port 1 Configuration Serial Port Device Settings Change Settings Device Mode Serial Port 2 Configuration Serial Port Device Settings Change Settings Device Mode Options Description Enabled Disabled Enable / Disable Serial Port (COM). IO=2F8h; IRQ=4 Fixed configuration of serial port.
Feature ACPI Sleep State Options Description ATX BIOS will report no suspend functions to ACPI OS. In windows XP, it will make OS show shutdown message during system shutdown. Suspend Disabled S1 only (CPU Stop Clock) S3 only (Suspend to RAM) Both S1 and S3 available for os to choose from Select ACPI sleep state the system will enter when the SUSPEND button is pressed. 7.3.
7.3.17 Advanced > Serial Port Console > Console Redirection Feature Options Description Console Redirection Settings Info only Terminal Type VT100 VT100+ VT-UTF8 ANSI Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes. Bits per second 9600 19200 38400 57600 115200 Selects serial port transmission speed. Data Bits 7 8 Select Data Bits.
Feature Options Description settings. Set to Disabled for manual conmfiguration. Critical Trip Point Disable 85 C 95C This value controls the temperature of the ACPI Critical Trip Point - the point in which the OS will shut the system off. NOTE: 100C is the Plan Of Record (POR) for all Intel mobile processors.
7.4 Boot Menu The Boot Menu allows control of Boot features 7.4.1 Boot > Boot Configuration Feature Options Boot Configuration Info only Setup Prompt Timeout 1 Enable / Disable the onboard SATA controllers. Bootup NumLock State On Select SATA controller mode. Quiet Boot Disabled Enabled Enable / Disable the PATA port. In fact this enables or disables the SATA channel on which the onboard SATA to PATA converter is attached.
7.5 Security Menu 7.5.1 Security > Password Description Feature Options Administrator Password Enter password User Password Enter password Secure Boot menu Submenu 7.5.2 Description Security > Secure Boot menu Feature Options Description System Mode Setup Secure Boot Info only Secure Boot Support Disabled Enabled Secure Boot can be enabled if 1.System running in User mode with enrolled Platform Key(PK) 2.CSM function is disabled.
8 BIOS Checkpoints, Beep Codes This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions. Checkpoints and Beep Codes Definition A checkpoint is either a byte or word value output to I/O port 80h.
8.1 Status Code Ranges Status Code Range Description 0x01 – 0x0B SEC execution 0x0C – 0x0F SEC errors 0x10 – 0x2F PEI execution up to and including memory detection 0x30 – 0x4F PEI execution after memory detection 0x50 – 0x5F PEI errors 0x60 – 0x8F DXE execution up to BDS 0x90 – 0xCF BDS execution 0xD0 – 0xDF DXE errors 0xE0 – 0xE8 S3 Resume (PEI) 0xE9 – 0xEF S3 Resume errors (PEI) 0xF0 – 0xF8 Recovery (PEI) 0xF9 – 0xFF Recovery errors (PEI) 8.2 Standard Status Codes 8.2.
SEC Error Codes 0x0C – 0x0D Reserved for future AMI SEC error codes 0x0E Microcode not found 0x0F Microcode not loaded 8.2.2 SEC Beep Codes None 8.2.
Status Code Description 0x36 CPU post-memory initialization.
Status Code Description 0xEB S3 OS Wake Error 0xEC-0xEF Reserved for future AMI error codes Recovery Progress Codes 0xF0 Recovery condition triggered by firmware (Auto recovery) 0xF1 Recovery condition triggered by user (Forced recovery) 0xF2 Recovery process started 0xF3 Recovery firmware image is found 0xF4 Recovery firmware image is loaded 0xF5-0xF7 Reserved for future AMI progress codes Recovery Error Codes 0xF8 Recovery PPI is not available 0xF9 Recovery capsule is not found 0xFA
Status Code Description 0x66 CPU DXE initialization (CPU module specific) 0x67 CPU DXE initialization (CPU module specific) 0x68 PCI host bridge initialization 0x69 North Bridge DXE initialization is started 0x6A North Bridge DXE SMM initialization is started 0x6B North Bridge DXE initialization (North Bridge module specific) 0x6C North Bridge DXE initialization (North Bridge module specific) 0x6D North Bridge DXE initialization (North Bridge module specific) 0x6E North Bridge DXE initial
Status Code Description 0x9D USB Enable 0x9E – 0x9F Reserved for future AMI codes 0xA0 IDE initialization is started 0xA1 IDE Reset 0xA2 IDE Detect 0xA3 IDE Enable 0xA4 SCSI initialization is started 0xA5 SCSI Reset 0xA6 SCSI Detect 0xA7 SCSI Enable 0xA8 Setup Verifying Password 0xA9 Start of Setup 0xAA Reserved for ASL (see ASL Status Codes section below) 0xAB Setup Input Wait 0xAC Reserved for ASL (see ASL Status Codes section below) 0xAD Ready To Boot event 0xAE Legacy
Status Code Description 0xD6 No Console Output Devices are found 0xD7 No Console Input Devices are found 0xD8 Invalid password 0xD9 Error loading Boot Option (LoadImage returned error) 0xDA Boot Option is failed (StartImage returned error) 0xDB Flash update is failed 0xDC Reset protocol is not available 8.2.
8.
9 Mechanical Information 9.1 Board-to-Board Connectors To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When 5 mm receptacles are chosen, the carrier board should be free of components. Tyco 3-1827253-6 Foxconn QT002206-2131-3H • 220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm. • This connector can be used with 5 mm through-hole standoffs (SMT type).
9.2 Thermal Solution 9.2.1 Heat Spreaders The function of the heat spreader is to ensure an identical mechanical profile for all COM Express modules. By using a heat spreader, the thermal solution that is built on top of the module is compatible with all COM Express modules. 9.2.2 Heat Sinks A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless, depending on the thermal requirements. 9.2.
Step 4: Use the four M2.5, L=6mm screws provided to fasten the heatsink to the module. Step 5: Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown. Then press down on the module until it is firmly seated on the carrier board. Step 6: Use the five M2.5, L=16mm screws provided to secure the COM Express module to the carrier board from the solder side. Step 7: If you are installing a heatsink with a fan, plug the fan connector into the carrier board as shown.
9.3 Mounting Methods There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the choice of 5 mm or 8mm board-to-board connectors, there is the choice of Top and Bottom mounting. In Top mounting, the threaded standoffs are on the carrier board and the thermal solution is equipped with through-hole standoffs. In Bottom mounting, the threaded standoffs are on the thermal solution and the carrier board has through-hole standoffs.
9.4 Standoff Types The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and throughhole standoffs are SMT type. Other types not listed are available upon request.
Safety Instructions Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use. • Please read these safety instructions carefully. • Please keep this User‘s Manual for later reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment.
Getting Service ADLINK Technology, Inc. Address: Tel: Fax: Email: 9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan +886-2-8226-5877 +886-2-8226-5717 service@adlinktech.com Ampro ADLINK Technology, Inc. Address: Tel: Toll Free: Fax: Email: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA +1-408-360-0200 +1-800-966-5200 (USA only) +1-408-360-0222 info@adlinktech.com ADLINK Technology (China) Co., Ltd. Address: Tel: Fax: Email: 300 Fang Chun Rd.
ADLINK Technology, Inc. (French Liaison Office) Address: 6 allée de Londres, Immeuble Ceylan 91940 Les Ulis, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com ADLINK Technology Japan Corporation Address: KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho, Chiyoda-ku Tokyo 101-0045, Japan Tel: +81-3-4455-3722 Fax: +81-3-5209-6013 Email: japan@adlinktech.com ADLINK Technology, Inc.
