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cExpress-HL

User’s Manual

Manual Revision: 1.01

Revision Date: September 23, 2014

Part Number: 50-1J049-1010

Summary of content (83 pages)

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cExpress-HL User’s Manual Manual Revision: 1.
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Revision History Revision Description Date By 1.00 Initial release 2014-07-28 JC 1.01 Add BIOS Checkpoints, Beep Codes; remove Industrial Temp.
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Preface Copyright 2014 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.
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Table of Contents Revision History ............................................................................................................ 2 Preface............................................................................................................................ 3 1 Introduction ............................................................................................................ 6 2 Specifications ......................................................................................
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.1 6 Board Specific SEMA Functions ................................................................................................. 37 System Resources ................................................................................................. 39 6.1 System Memory Map................................................................................................................. 39 6.2 Direct Memory Access Channels ..............................................................................
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1 Introduction The cExpress-HL is a COM Express® COM.0 R2.1 Type 6 Compact size module supporting the 64-bit 4th Generation Intel® Core™ i7/i5/3 ULT Processors with CPU, memory controller, graphics processor and I/O hub on the same chip. Leveraging the benefits provided by the Intel® Core™ i7/i5/3 ULT System-on-Chip, the cExpress-HL is specifically designed for customers who need optimum processing and graphics performance with low power consumption in a long product life solution.
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2 Specifications 2.1 Core System ¾ CPU: 4th Generation Intel® Core™ processor SoC (formerly "Haswell-ULT", Ultra Low TDP) • Intel® Core™ i7-4650U 1.7 GHz (3.3 GHz Turbo), 15W (2C/GT3) • Intel® Core™ i5-4300U 1.9 GHz (2.9 GHz Turbo), 15W (2C/GT2) • Intel® Core™ i3-4010U 1.7 GHz (no Turbo) 3MB, 15W (2C/GT2) • Intel® Celeron® 2980U 1.6 GHz (no Turbo), 15W (2C/HDG) Supporting: Intel® VT, Intel® TXT, Intel® SSE4.
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2.4 Audio ¾ Integrated: Intel® HD Audio integrated in PCH QM87 ¾ Codec: Realtek ALC886 on Express-BASE6 2.5 LAN ¾ Integrated: MAC integrated in SOC ¾ Intel PHY: Intel® Ethernet Controller i218LM ¾ Interface: 10/100/1000 GbE connection 2.6 Multi I/O and Storage ¾ Integrated: in SOC ¾ USB ports: 2 ports USB 3.0 (USB0,1) and 6 ports USB 2.0 (USB2,3,4,5,6,7) ¾ SATA ports: four ports SATA 6Gb/s ¾ GPIO: 4 GPO and 4 GPI with interrupt 2.
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2.11 Power Specifications ¾ Power Modes: ¾ Standard Voltage Input: ATX = 12V±5% / 5Vsb ±5% or ¾ Wide Voltage Input: ATX = 5~20 V / 5Vsb ±5% or AT = 5 ~20V ¾ Power Management: ACPI 4.0 compliant, Smart Battery support ¾ Power States: supporting C1-C6, S0, S1, S4, S3, S5 (Wake-on-USB S3/S4, WoL S3/S4/S5) ¾ ECO mode supports deep S5 (ECO mode) 2.
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2.16 Functional Diagram 1333/1600 MHz 1~8 GB DDR3L 60-pin 1333/1600 MHz 1~8 GB DDR3L single/dual 18/24-bit LVDS RTD2136R DDI 0 (port B) DP / HDMI / DVI eDP 2 lanes DDI 1 (port C) DP / HDMI / DVI 4x PCIe x1 (Gen2) (ports 0~3) 2x USB 3.0 upgrade (ports 0/1) PCIe x1 (port 4) i217LM SoC “Haswell-ULT” 4x SATA 6 Gb/s (ports 0/1/2/3) 6x USB 2.
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2.17 Mechanical Drawing connectors on bottom side Top View Side View All tolerances ± 0.05 mm Other tolerances ± 0.
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3 Pinouts and Signal Descriptions 3.1 AB / CD Pin Definitions The cExpress-HL is a Type 6 module supporting USB 3.0 and DDI channels on the CD connector All pins in the COM Express specification are described, including those not supported on the cExpress-HL.
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Row A Row B Row C Row D Pin Name Pin Name Pin Name Pin Name A36 USB6- B36 USB7- C36 DDI3_CTRLCLK_AUX+ D36 DDI1_PAIR3+ A37 USB6+ B37 USB7+ C37 DDI3_CTRLDATA_AUX- D37 DDI1_PAIR3- A38 USB_6_7_OC# B38 USB_4_5_OC# C38 DDI3_DDC_AUX_SEL D38 RSVD A39 USB4- B39 USB5- C39 DDI3_PAIR0+ D39 DDI2_PAIR0+ A40 USB4+ B40 USB5+ C40 DDI3_PAIR0- D40 DDI2_PAIR0- A41 GND (FIXED) B41 GND (FIXED) C41 GND (FIXED) D41 GND (FIXED) A42 USB2- B42 USB3- C42 DDI3_PAIR1+ D42
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Row A Row B Row C Row D Pin Name Pin Name Pin Name Pin Name A81 LVDS_A_CK+ B81 LVDS_B_CK+ C81 PEG_RX9+ D81 PEG_TX9+ A82 LVDS_A_CK- B82 LVDS_B_CK- C82 PEG_RX9- D82 PEG_TX9- A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C83 TPM_PP D83 RSVD A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84 GND D84 GND A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10+ D85 PEG_TX10+ A86 RSVD B86 VCC_5V_SBY C86 PEG_RX10- D86 PEG_TX10- A87 RSVD B87 VCC_5V_SBY C87 GND D87 GND A88 PCIE0_CK_REF+ B88
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3.2 Signal Description Terminology The following terms are used in the COM Express AB/CD Signal Descriptions below. I Input to the Module O Output from the Module I/O Bi-directional input / output signal OD Open drain output I 3.3V Input 3.3V tolerant I 5V Input 5V tolerant O 3.3V Output 3.3V signal level O 5V Output 5V signal level I/O 3.3V Bi-directional signal 3.3V tolerant I/O 5V Bi-directional signal 5V tolerant I/O 3.3Vsb Input 3.
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3.3 AB Signal Descriptions 3.3.1 Audio Signals Signal Pin # Description I/O AC_RST# / HDA_RST# A30 Reset output to codec, active low. O 3.3VSB AC_SYNC / HDA_SYNC A29 Sample-synchronization signal to the codec(s). O 3.3V AC_BITCLK / HDA_BITCLK A32 Serial data clock generated by the external codec(s). I/O 3.3V AC _SDOUT / HDA_SDOUT A33 Serial TDM data output to the codec. O 3.3V AC _SDIN[2:0] HDA_SDIN[2:0] B28 B30 Serial TDM data inputs from up to 3 codecs. I/O 3.3V 3.3.
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3.3.
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3.3.5 Serial ATA Signal Pin # Description I/O SATA0_TX+ SATA0_TX- A16 A17 Serial ATA channel 0, Transmit Output differential pair. O SATA AC coupled on Module SATA0_RX+ SATA0_RX- A19 A20 Serial ATA channel 0, Receive Input differential pair. I SATA AC coupled on Module SATA1_TX+ SATA1_TX- B16 B17 Serial ATA channel 1, Transmit Output differential pair. O SATA AC coupled on Module SATA1_RX+ SATA1_RX- B19 B20 Serial ATA channel 1, Receive Input differential pair.
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Signal Pin # Description I/O PCIE_RX5+ PCIE_RX5- B52 B53 PCI Express channel 5, Receive Input differential pair. I PCIE PCIE_CLK_REF+ PCIE_CLK_REF- A88 A89 PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes. O PCIE 3.3.7 PU/PD Not supported Express Card Signal Pin # Description I/O PU/PD EXCD0_CPPE# EXCD1_CPPE# A49 B48 PCI ExpressCard: PCI Express capable card request I 3.3V PU 10k 3.
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Signal Pin # Description I/O PU/PD Comment USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. . I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up for this line shall be present on the module.
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3.3.12 Miscellaneous Signal Pin # Description I/O SPKR B32 Output for audio enunciator, the “speaker” in PC-AT systems O 3.3V WDT B27 Output indicating that a watchdog time-out event has occurred. O 3.3V THRM# B35 Input from off-module temp sensor indicating an overtemp situation. I 3.3V THERMTRIP# A35 Active low output indicating that the CPU has entered thermal shutdown. O 3.3V FAN_PWMOUT B101 Fan speed control.
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Signal Pin # Description I/O GPO[3] B63 General purpose output pins. O 3.3V GPI[0] A54 General purpose input pins. Pulled high internally on the module. I 3.3V PU 10K 3.3V GPI[1] A63 General purpose input pins. Pulled high internally on the module. I 3.3V PU 10K 3.3V GPI[2] A67 General purpose input pins. Pulled high internally on the module. I 3.3V PU 10K 3.3V GPI[3] A85 General purpose input pins. Pulled high internally on the module. I 3.3V PU 10K 3.3V PU/PD 3.3.
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Signal Description I/O PU/PD LID# LID button. Low active signal used by the ACPI operating system for a LID switch. I OD 3.3VSB PU 10k 3.3VSB SLEEP# Sleep button. Low active signal used by the ACPI operating system to bring the system to sleep state or to wake it up again. I OD 3.3VSB PU 10K 3.3VSB 3.3.18 Pin # Comment Power and Ground Signal Pin # Description I/O VCC_12V A104-A109 B104-B109 Primary power input: +12V nominal (5 ~ 20V wide input).
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3.4 CD Signal Descriptions 3.4.1 USB 3.
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3.4.3 DDI Channels DDI 1 Signal Pin Description I/O DDI1_PAIR0+ DDI1_PAIR0DDI1_PAIR1+ DDI1_PAIR1DDI1_PAIR2+ DDI1_PAIR2DDI1_PAIR3+ DDI1_PAIR3DDI1_PAIR4+ DDI1_PAIR4DDI1_PAIR5+ DDI1_PAIR5DDI1_PAIR6+ DDI1_PAIR6- D26 D27 D29 D30 D32 D33 D36 D37 C25 C26 C29 C30 C15 C16 Digital Display Interface1 differential pairs O PCIE DDI1_HPD C24 Digital Display Interface Hot-Plug Detect I PCIE DDI1_CTRLCLK_AUX+ D15 IF DDI1_DDC_AUX_SEL is floating I/O PCIe DP1_AUX+ IF DDI1_DDC_AUX_SEL pulled high I/O OD 3.
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DDI 2 Signal Pin Description DDI2_PAIR0+ DDI2_PAIR0DDI2_PAIR1+ DDI2_PAIR1DDI2_PAIR2+ DDI2_PAIR2DDI2_PAIR3+ DDI2_PAIR3- D39 D40 D42 D43 D46 D47 D49 D50 Digital Display Interface2 differential pairs DDI2_HPD D44 DDI2_CTRLCLK_AUX+ C32 DDI2_CTRLCLK_AUX- DDI2_DDC_AUX_SEL C33 I/O PU/PD Comment IF DDI2_DDC_AUX_SEL is floating I/O PCIe DP2_AUX+ IF DDI2_DDC_AUX_SEL pulled high I/O OD 3.
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3.4.
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3.4.
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Signal Pin PEG_TX15+ PEG_TX15- D101 D102 PEG_LANE_RV# D54 3.4.6 Description I/O PCI Express Graphics lane reversal input strap. Pull low on the Carrier board to reverse lane order. I 1.05V PU/PD Comment Not supported Module Type Definition Signal Pin # Description I/O TYPE0# TYPE1# TYPE2# C54 C57 D57 The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are noconnects (NC).
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4 Connector Pinouts on Module This chapter describes connectors and pinouts, LEDs and switches that are used on the module but are not included in the PICMG standard specification ¾ Connector and LED Locations XDP 60-pin to CPU Keep out CPU CD BIOS Defaults Reset Switch AB 4-pin Fan Page 30 LED1 LED2 LED3 FAN 40-pin Debug Connector cExpress-HL
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4.
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40-pin Debug Connector Pin Definition on the COM Express Module ¾ Pin Interface Signal Remark Pin Interface Signal 1 SPI Program interface VCC_SPI_IN SPI Power Input from flash tool to module.
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4.2 Status LEDs To facilitate easier maintenance, status LED’s are mounted on the board. ¾ LED Descriptions Name Color Connection Function LED1 Blue BMC output Power Sequence Status Code (BMC) Power Changes, RESET (see 5.1.
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4.3 XDP Debug header The debug port is a connection into a target-system environment that provides access to JTAG, run control, system control, and observation resources. The XDP target system connector is a Samtec™ 60-pin BSH-030-01 series connector.
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4.4 Fan Connector ¾ Connector Type: JVE 24W1125A-04M00 ¾ Pin Assignment Name Signal Description 1 BMC_FAN_OUT FAN_PWMOUT 2 BMC_FAN_PWM_IN FAN_TACHIN 3 GND Ground 4 P5V_S 5V 4.5 BIOS Setup Defaults Reset Button To perform a hardware reset of BIOS default settings, perform the following steps: 1. Shut down the system. 2. Press the BIOS Setup Defaults RESET Button continuously and boot up the system. You can release the button when the BIOS prompt screen appears 3.
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5 Smart Embedded Management Agent (SEMA) The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality. The microcontroller communicates via the System Management Bus with the CPU/chipset. The following functions are implemented: ‧ Total operating hours counter. Counts the number of hours the module has been run in minutes. ‧ On-time minutes counter. Counts the seconds since last system start. ‧ Temperature monitoring of CPU and board temperature.
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5.1 Board Specific SEMA Functions 5.1.1 Voltages The BMC of the cExpress-HL implements a voltage monitor and samples several onboard voltages. The voltages can be read by calling the SEMA function “Get Voltages”. The function returns a 16-bit value divided into high-byte (MSB) and low-byte (LSB). 5.1.2 ADC Channel Voltage Name Voltage Formula [V] 0 +V1.05S (MSB<<8 + LSB) x 3.3 / 1024 1 +VCORE (MSB<<8 + LSB) x 3.3 / 1024 2 +V1.05S (MSB<<8 + LSB) x 3.3 / 1024 3 +V3.3A (MSB<<8 + LSB) x 1.
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5.1.4 Exception Codes In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore, a “Clear Exception Code” command is not needed or supported. 5.1.
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6 System Resources 6.1 System Memory Map Address Range (decimal) Address Range (hex) Size Description (4GB-2MB) FFE00000 – FFFFFFFF 2 MB High BIOS Area (4GB-18MB) – (4GB-17MB-1) FEE00000 – FEEFFFFF 1 MB MSI Interrupts (4GB-20MB) – (4GB-19MB-1) FEC00000 – FECFFFFF 1 MB APIC Configuration Space 1MB -15MB 100000 - EFFFFF 14MB Main Memory 0K –1MB 00000 – FFFFFF 1MB DOS Compatibility Memory 6.
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6.
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Hex Range Device 3BC-3BE Reserved for parallel port 3C0-3DF VGA registers 3E0-3EF Available 3F0-3F7 Available 3F8-3FF Serial port 1 4D0 Master PIC Edge/Level Trigger register 4D1 Slave PIC Edge/Level Trigger register CF8-CFB PCI configuration address register (32 bit I/O only) CF9 Reset Control register (8 bit I/O) CFC-CFF PCI configuration data register F040 Smbus base address for SB.
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6.
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IRQ# Typical Intterupt Resource Connected to Pin Available 16 N/A Intel HDA, PCIE Port 0/1/2/3 EHCI Conterller #2 , I.G.D ,XHCI Controller Note (1) 17 N/A PCIE Port 0/1/2/3 Note (1) 18 N/A PCIE Port 0/1/2/3 SMBus Controller, Note (1) 19 N/A PCIE Port 0/1/2/3 Note (1) 20 N/A Gbe Controller Note (1) 21 N/A 22 N/A Intel HDA Note (1) 23 N/A EHCI Controller #1 Note (1) Note (1): Note (1) These IRQs can be used for PCI devices when onboard device is disabled.
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6.5 PCI Configuration Space Map Bus Number Device Number Function Number Routing Description 00h 00h 00h N/A Intel host Bridge 00h 02h 00h Internal Intel I.G.
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6.
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7 BIOS Setup 7.1 Menu Structure This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.
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7.2 Main The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below for details of the submenus and settings. 7.2.1 System Information Feature Options Description BIOS Version Info only ADLINK BIOS version Build Date and Time Info only Date the BIOS was built 7.2.2 Processor Information Feature Options Description CPU Brand String Info only Display CPU Brand Name.
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7.2.6 System Management 7.2.6.
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Feature Options Description V1.00 Read only Display actual V1.00 voltage V3.30 Read only Display actual V3.30 voltage VIN Read only Display actual VIN voltage AIN7 Read only Display actual AIN7 voltage 7.2.6.4 System Management > Runtime Statistics Feature Options Runtime Statistics Info only Description Total Runtime Read only The returned value specifies the total time in minutes the system is running in S0 state.
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7.2.6.7 System Management > LVDS Backlight Feature Options LVDS Backlight Info only LVDS Backlight Bright 7.2.6.8 255 Description The value range starts at 0 and ends at 255.
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7.3 Advanced This menu contains the settings for most of the user interfaces in the system. 7.3.1 CPU Feature Options CPU Infor only CPU Brand Name Info only Display CPU brand name CPU Signature Info only Display CPU signature Processor Family Info only Display processor family Microcode Patch Info only Display microcode patch FSB Speed Info only Display FSB Speed Max CPU speed Info only Display max. CPU speed Min CPU speed Info only Display min.
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Feature Options Description CPU C3 Report Disabled Enabled Enable / Disable CPU C3 report to OS. CPU C6 Report Disabled Enabled Enable / Disable CPU C6 report to OS. CPU C7 Report Disabled CPU C7 CPU C7S Enable / Disable CPU C7 report to OS. C1 State auto undemotion Disabled Enabled Un-demotion from Demoted C1 C3 State auto undemotion Disabled Enabled Un-demotion from Demoted C3 ACPI T State Disabled Enabled Enable / Disable ACPI T state support.
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7.3.3 Graphics Feature Options Graphics Info only IGFX VBIOS Version Info only Display VBIOS Version. IGfx Frequency Info only Display IGfx Frequency. Graphics Turbo IMON Current Number entry field Graphics turbo IMON current values supported (14-31). Primary Display Auto IGFX PCIE Select which of IGFX/PCI Graphics device should be Primary Display Or select SG for Switchable Gfx.
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Feature Options Description 1280X1024 1400X1050 1600X1200 1366X768 1680X1050 1920X1200 1440X900 1600X900 1024X768 LVDS2 1280X800 1920X1080 2048X1536 Active LFP No LVDS Edp Port-A Select the Active LFP Configuration. Panel Color Depth 18 Bit 24 Bit Select the LFP Panel Color Depth Panel Scaling Auto Off Force Scaling Select the LCD panel scaling option used by the Internal Graphics Device. GT – Power Management Control Info only GT Info Info only Display GT info of Intel Graphics.
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Feature Options SATA Port Configuration Submenu Software Feature Mask Configuration Info only RAID0 Enabled Disabled Enable / Disable RAID0 feature. RAID1 Enabled Disabled Enable / Disable RAID1 feature. RAID10 Enabled Disabled Enable / Disable RAID10 feature. RAID5 Enabled Disabled Enable / Disable RAID5 feature. Intel Rapid Recovery Technology Enabled Disabled Enable / Disable Intel Rapid Recovery Technology. OROM UI and BANNER Enabled Disabled If enabled, then the OROM UI is shown.
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Feature Options Description SATA Device Type Hard Disk Drive Sold State Drive Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. Spin up Device Disabled Enabled On an edge detect from 0 to 1, the PCH starts a COMRESET initialization sequence to the device. 7.3.5 USB Feature Options USB Info only USB Module Version Info only USB Devices Info only Drives, keyboards, mouse, hubs Legacy USB Support Enabled Disabled Auto Enables legacy USB support.
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7.3.5.1 USB > Chipset USB Configuration Feature Options USB Configuration Info only USB Precondition Disable Enable Precondition work on USB host controller and root ports for faster enumeration. XHCI Mode Enabled Disabled Auto Smart Auto Mode of operation of xHCI controller. XHCI Idle L1 Enabled Disabled Enable or disable XHCI Idle L1.\n XhciIdleL1 can be set to disable for LPT-LP Ax stepping to workaround USB3 hot plug will fail after 1 hot plug removal.
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Feature Options Description USB Configure Enabled Disabled Enable/Disable USB Configure function. PET Progress Enabled Disabled User can Enable/Disable PET Events progress to recieve PET events or not. AMT CIRA Timeout 0 OEM defined timeout for MPS connection to be established. 0 use the default timeout value of 60 seconds. 255 - MEBX waits until the connection succeeds. Watchdog Enabled Disabled Enable/Disable WatchDog Timer. OS Timer Set OS watchdog timer.
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Feature Options Description 4096 Bytes PCI Express Link Register Settings Info only ASPM Support WARNING: Enabling ASPM may cause some PCI-E devices to fail Disabled Auto Force L0s Set the ASPM Level: Force L0s - Force all links to L0s Auto - BIOS auto configure Disabled - Disables ASPM Extended Synch Disabled Enabled If enabled, allows generation of Extended Synchronization patterns.
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PCI and PCIe > PCIe Configuration > PCI Express Port x Page 60 Feature Options Description PCI Express Port x Enabled Disabled Enable or disable the PCI Express port x in the chipset. ASPM support Disabled L0s L1 L0Sl1 Auto Set the ASPM Level: Force L0s – Force all links to L0s State : AUTO – BIOS auto configure : DISABLE – Disables ASPM L1 Substates Disabled L1.1 L1.2 L1.1 & L1.
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Feature 7.3.8 Options Description Snoop Latency Ocerrid Disable Manual Auto Snoop Latency Ocerride for PCH PCIE. Non Snoop Latency Ocerrid Disable Manual Auto Non Snoop Latency Ocerride for PCH PCIE. Super IO Feature Options Super IO Chip Info only W83627DHG Super IO Configuration Submenu NCT5104D Super IO Configuration Submenu Serial Port 1 Configuration Serial Port Description Enabled Disabled Enable/Disable Serial Port 1 (COM0).
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Feature Options Description XP, the the "OS shutdown message" will be shown when the system is shutdown. ACPI Sleep State Suspend Disabled S3 (Suspend to RAM) Select the highest ACPI sleep state the system will enter when the Suspend button is pressed. Feature Options Description Sound Info only Azalia Disabled Enabled Auto Control detection of the Azalia device. Disabled = Azalia will be unconditionally disabled. Enabled = Azalia will be unconditionally enabled.
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7.3.11.1 Serial Port Console > Console Redirection Settings Feature Options Description COM1/ COM2/ COM3/ COM4 Console Redirection Settings Info only Terminal Type VT100 VT100+ VT-UTF8 ANSI VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes. ANSI: Extended ASCII char set. Bits per second 9600 19200 38400 57600 115200 Selects serial port transmission speed.
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Feature Options Description Active Cooling Trip Point Disabled 40 C 50 C 60 C 70 C BMC Default Active Cooling Trip Point. Passive Trip Point Disabled 90 C 80 C This value controls the temperature of the ACPI Passive Trip Point - the point at which the OS will begin throtting the processor. Passive TC1 Value 1 This value sets the TC1 value for the ACPI Passive Cooling Formula. Range 1 - 16 Passive TC2 Value 5 This value value sets the TC2 value for the ACPI Passive Cooling Formula.
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7.3.13.2 Miscellaneous > Trusted Computing Feature Options Coniguration Info only Security Device Support Enabled Disabled Current Status Information Info only Description Enables or disables BIOS support for security device. OS will not show security device. TCG EFI protocol and INT1A interface will not be available. 7.4 Boot 7.4.1 Boot Configuration Feature Options Boot Configuration Info only Setup Prompt Timeout 1 Number of seconds to wait for setup activation key.
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7.4.1.2 Boot Configuration > CSM Parameters Feature Options Description Launch CSM Enable Disable This option controls if CSM will be launched. Boot Option filter UEFI and Legacy Legacy only UEFI only This option controls what devices system can to boot. Launch PXE OpROM policy Do not launch Legacy only UEFI only Controls the execution of UEFI and Legacy PXE OpROM. Launch Storage OpROM policy Do not launch UEFI only Legacy only Controls the execution of UEFI and Legacy Storage OpROM.
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7.6 Save & Exit 7.6.1 Save and Exit > Reset Options Feature Options Description Save Changes and Reset Save changes and reset the system. Save Changes and Reset Discard Changes and Reset Reset the system without saving any changes. Discard Changes and Reset 7.6.2 Save and Exit > Save Options Feature Options Description Save Changes Yes No Save Changes done so far to any of the setup options. Discard Changes Yes No Discard Changes done so far to any of the setup options.
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8 BIOS Checkpoints, Beep Codes This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions. Checkpoints and Beep Codes Definition A checkpoint is either a byte or word value output to I/O port 80h.
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8.1 Status Code Ranges Status Code Range Description 0x01 – 0x0F SEC Status Codes & Errors 0x10 – 0x2F PEI execution up to and including memory detection 0x30 – 0x4F PEI execution after memory detection 0x50 – 0x5F PEI errors 0x60 – 0xCF DXE execution up to BDS 0xD0 – 0xDF DXE errors 0xE0 – 0xE8 S3 Resume (PEI) 0xE9 – 0xEF S3 Resume errors (PEI) 0xF0 – 0xF8 Recovery (PEI) 0xF9 – 0xFF Recovery errors (PEI) 8.2 Standard Status Codes 8.2.
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8.2.2 SEC Beep Codes None 8.2.
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Status Code Description 0x3C Post-Memory South Bridge initialization (South Bridge module specific) 0x3D Post-Memory South Bridge initialization (South Bridge module specific) 0x3E Post-Memory South Bridge initialization (South Bridge module specific) 0x3F-0x4E OEM post memory initialization codes 0x4F DXE IPL is started PEI Error Codes 0x50 Memory initialization error. Invalid memory type or incompatible memory speed 0x51 Memory initialization error.
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Status Code Description 0xF2 Recovery process started 0xF3 Recovery firmware image is found 0xF4 Recovery firmware image is loaded 0xF5-0xF7 Reserved for future AMI progress codes Recovery Error Codes 0xF8 Recovery PPI is not available 0xF9 Recovery capsule is not found 0xFA Invalid recovery capsule 0xFB – 0xFF Reserved for future AMI error codes 8.2.
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Status Code Description 0x6C North Bridge DXE initialization (North Bridge module specific) 0x6D North Bridge DXE initialization (North Bridge module specific) 0x6E North Bridge DXE initialization (North Bridge module specific) 0x6F North Bridge DXE initialization (North Bridge module specific) 0x70 South Bridge DXE initialization is started 0x71 South Bridge DXE SMM initialization is started 0x72 South Bridge devices initialization 0x73 South Bridge DXE Initialization (South Bridge module
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Status Code Description 0xA4 SCSI initialization is started 0xA5 SCSI Reset 0xA6 SCSI Detect 0xA7 SCSI Enable 0xA8 Setup Verifying Password 0xA9 Start of Setup 0xAA Reserved for ASL (see ASL Status Codes section below) 0xAB Setup Input Wait 0xAC Reserved for ASL (see ASL Status Codes section below) 0xAD Ready To Boot event 0xAE Legacy Boot event 0xAF Exit Boot Services event 0xB0 Runtime Set Virtual Address MAP Begin 0xB1 Runtime Set Virtual Address MAP End 0xB2 Legacy Option
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Status Code Description 0xDC Reset protocol is not available 8.2.6 DXE Beep Codes # of Beeps Description 4 Some of the Architectural Protocols are not available 5 No Console Output Devices are found 5 No Console Input Devices are found 1 Invalid password 6 Flash update is failed 7 Reset protocol is not available 8 Platform PCI resource requirements cannot be met 8.2.
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9 Mechanical Information 9.1 Board-to-Board Connectors To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When 5 mm receptacles are chosen, the carrier board should be free of components. Tyco 3-1827253-6 Foxconn QT002206-2131-3H • 220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm. • This connector can be used with 5 mm through-hole standoffs (SMT type).
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9.2 Thermal Solution 9.2.1 Heat Spreaders The function of the heat spreader is to ensure an identical mechanical profile for all COM Express modules. By using a heat spreader, the thermal solution that is built on top of the module is compatible with all COM Express modules. 9.2.2 Heat Sinks A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless, depending on the thermal requirements. 9.2.
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Step 4: Use the four M2.5, L=6mm screws provided to fasten the heatsink to the module. Step 5: Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown. Then press down on the module until it is firmly seated on the carrier board. Step 6: Use the five M2.5, L=16mm screws provided to secure the COM Express module to the carrier board from the solder side. Step 7: If you are installing a heatsink with a fan, plug the fan connector into the carrier board as shown.
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9.3 Mounting Methods There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the choice of 5 mm or 8mm board-to-board connectors, there is the choice of Top and Bottom mounting. In Top mounting, the threaded standoffs are on the carrier board and the thermal solution is equipped with through-hole standoffs. In Bottom mounting, the threaded standoffs are on the thermal solution and the carrier board has through-hole standoffs.
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9.4 Standoff Types The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and throughhole standoffs are SMT type. Other types not listed are available upon request.
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Safety Instructions Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use. • Please read these safety instructions carefully. • Please keep this User‘s Manual for later reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment.
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Getting Service ADLINK Technology, Inc. Address: Tel: Fax: Email: 9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan +886-2-8226-5877 +886-2-8226-5717 service@adlinktech.com Ampro ADLINK Technology, Inc. Address: Tel: Toll Free: Fax: Email: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA +1-408-360-0200 +1-800-966-5200 (USA only) +1-408-360-0222 info@adlinktech.com ADLINK Technology (China) Co., Ltd. Address: Tel: Fax: Email: 300 Fang Chun Rd.
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ADLINK Technology, Inc. (French Liaison Office) Address: 6 allée de Londres, Immeuble Ceylan 91940 Les Ulis, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com ADLINK Technology Japan Corporation Address: KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho, Chiyoda-ku Tokyo 101-0045, Japan Tel: +81-3-4455-3722 Fax: +81-3-5209-6013 Email: japan@adlinktech.com ADLINK Technology, Inc.