CoreModuleTM 430 (PC/104 Single Board Computer) Reference Manual P/N 50-1Z006-1010
Notice Page DISCLAIMER ADLINK Technology, Incorporated makes no representations or warranties with respect to the contents of this manual or of the associated ADLINK products, and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose. ADLINK shall under no circumstances be liable for incidental or consequential damages or related expenses resulting from the use of this product, even if it has been notified of the possibility of such damages.
Contents Chapter 1 About This Manual ....................................................................................................1 Purpose of this Manual ....................................................................................................................1 References ......................................................................................................................................1 Chapter 2 Product Overview...........................................................
Contents Remote Access ...................................................................................................................... 30 Remote Access Setup ........................................................................................................ 30 Hot (Serial) Cable .............................................................................................................. 30 Watchdog Timer...........................................................................................
Contents Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 3-11. Table 3-12. Table 3-13. Table 3-14. Table 3-15. Table 3-16. Table 4-1. Table A-1. CoreModule 430 DMA Map ...............................................................................................................18 I/O Address Map ....................................................................................................19 Parallel (LPT) Interface Pin/Signal Descriptions (J4)........
Contents vi Reference Manual CoreModule 430
Chapter 1 About This Manual Purpose of this Manual This manual is for designers of systems based on the CoreModule™ 430 PC/104 single board computer (SBC) module. This manual contains information that permits designers to create an embedded system based on specific design requirements.
Chapter 1 2 About This Manual Reference Manual CoreModule 430
Chapter 2 Product Overview This introduction presents general information about the PC/104 architecture and the CoreModule 430 Single Board Computer (SBC). After reading this chapter you should understand: • PC/104 architecture • CoreModule 430 product description • CoreModule 430 features • Major components • Header definitions • Specifications PC/104 Architecture The PC/104 architecture affords a great deal of flexibility in system design.
Chapter 2 Product Overview Product Description The CoreModule 430 SBC is an exceptionally high integration, x86-based PC compatible system in the PC/104 form factor. This rugged and high quality single board system contains all the component subsystems of a PC/AT motherboard plus the equivalent of several PC/AT expansion boards. In addition, the CoreModule 430 SBC includes a comprehensive set of system extensions and enhancements that are specifically designed for embedded systems.
Chapter 2 • • • • • • Product Overview Serial Ports Provides two 10-pin headers and four buffered RS-232 serial ports with full handshaking and modem capability Provides 16C550 or 16C552 UARTs, each with a built-in 16-byte FIFO buffer Supports RS-232 or RS-485 operation on ports 1 and 2 Supports programmable word length, stop bits, and parity Supports 16-bit programmable baud-rate generator and an interrupt generator Parallel Port (LPT) Provides parallel port header Suppor
Chapter 2 Product Overview Supports fast rectangle fill engine Supports 64x64x2 bit-mapped mono hardware cursor Supports 256MB frame buffer with linear addressing VGA Interface (DB15) VGA Controller with 135 MHz triple RAMDACs for 1280 x 1024 x 75 Hz display Supports 24-bit pixel depth Interlaced or non-interlaced output TTL Interface • 6 Supports VESA Flat Panel Display interface Supports programmable panel size up to 1600x1200 pixel display resolution Supports inter
Chapter 2 Product Overview Block Diagram Figure 2-2 shows the functional components of the module.
Chapter 2 Product Overview Major Components (ICs) Table 2-1 describes the major integrated circuits (ICs) on the CoreModule 430, and Figure 2-3 shows the locations of the major ICs on the board. Table 2-1. Major Components (Chips) Descriptions and Functions 8 Chip Type Mfg. Model Description Function CPU (U1) DMP Electronics, Inc.
Chapter 2 Product Overview Key: U1 U2 U3 U5 U6 U7 U12 U13 U14 - CPU - DDR2 SDRAM - System Memory - DDR2 SDRAM - System Memory - RS232 Transceiver - COM4 - SPI Flash - Data Storage - RS232 Transceiver - COM1 and COM2 - 10/100 Ethernet Transformer - PCI Graphics Controller - DDR2 SDRAM - Video Memory U5 U7 U6 U14 U1 U13 U2 U12 CM430_comp_top_c U3 Figure 2-3.
Chapter 2 Product Overview Header, Connector, and Socket Definitions Table 2-2 describes the headers shown in Figure 2-5. Table 2-2. Header, Connector, and Socket Descriptions Jack/Plug # Access Description P1A/1B & P1C/1D – PC/104 Bus Top/ Bottom 104-pin, 0.100" (2.54mm) connectors for PC/104 (ISA) bus J2 – Ethernet Top 8-pin, 0.100" (2.54mm), right-angle header for Ethernet interface J3 – Serial 1 (COM1) Top 10-pin, 0.100" (2.
Chapter 2 Product Overview J5 J6 J9 JP5 JP6 JP7 JP8 J14 J13 JP1 J3 J19 J20 Key: J2 - Fast Ethernet J3 - COM1 J4 - Parallel J5 - Utility J6 - IDE J7 - Power J8 - GPIO J9 - COM2 J10 - USB0 J11 - TTL and VGA Video J13 - COM4 J14 - COM3 J17 - USB1 J19 - SPI 16 Mbit Data Storage JP1 - See jumper table JP2 - See jumper table JP5 - See jumper table JP6 - See jumper table JP7 - See jumper table JP8 - See jumper table P1 - PC/104 JP2 J11 J8 J4 J2 CM430_conn_top_c J7 DC AB J10 J17 P1 Figure 2-5.
Chapter 2 Product Overview Specifications Physical Specifications Table 2-4 shows the physical dimensions of the module and Figure 2-6 shows the mounting dimensions. Table 2-4. Weight and Footprint Dimensions Item Dimension Weight NOTE 0.10 kg. (0.20 lbs.) Height (upper surface) 10.99mm (0.43") See Note on page 13. Width 90.2mm (3.6") Length 95.9mm (3.8") Height is measured from the upper board surface to the highest permanent component (PC/104 connector) on the upper board surface.
Chapter 2 Product Overview NOTE All dimensions are given in inches. Pin 1 is shown as a black pin (square or round) on vertical headers or connectors in all illustrations. Black dots on rightangle headers or connectors indicate pin 2. The Compact Flash socket (J12) exceeds the PC/104 height limitation by 0.2 inches. Power Specifications Table 2-5 provides the power requirements for the 300 MHz and 800 MHz versions of the CoreModule 430. Table 2-5.
Chapter 2 14 Product Overview Reference Manual CoreModule 430
Chapter 3 Hardware Overview This chapter discusses the chips and connectors of the module features in the following order: • CPU • Graphics • Memory System Memory Video Memory SPI Flash • Memory Map • Interrupt Channel Assignments • I/O Address Map • Serial • Parallel (LPT) • Utility Keyboard Mouse Battery Reset Switch Speaker • Ethernet • USB • Video • SPI • LPC • Miscellaneous • Time of Day/RTC User GPIO Oops! Jumper (BIOS Recovery
Chapter 3 Hardware NOTE ADLINK Technology, Inc. only supports the features and options listed in this manual. The main components used on the CoreModule 430 may provide more features or options than are listed in this manual. Some of these features/options are not supported on the module and will not function as specified in the chip documentation. Only the pinout tables of non-standard headers and connectors are included in this chapter.
Chapter 3 Hardware Memory Map The following table provides the common PC/AT memory allocations. These are DOS-level addresses. The OS typically hides these physical addresses by way of memory management. Memory below 000500h is used by the BIOS. Table 3-1.
Chapter 3 Hardware Interrupt Channel Assignments The interrupt channel assignments are shown in Table 3-2. Table 3-2. Interrupt Channel Assignments Device vs IRQ No.
Chapter 3 Hardware I/O Address Map Table 3-4 shows the I/O address map. These are DOS-level addresses. The OS typically hides these physical addresses by way of memory management. Table 3-4.
Chapter 3 Hardware Parallel Interface (LPT) The Vortex x86 processor chip provides the Parallel Port interface. The Parallel Port supports the standard parallel, Bi-directional, Standard Printer Port (SPP), Enhanced Parallel Port (EPP), and Enhanced Capabilities Port (ECP) protocols. Table 3-5 describes the pin signals of the Parallel interface, which uses a 26-pin, right-angle header with 2 rows, odd/even sequence (1, 2), and 0.079" (2mm) pitch. Table 3-5.
Chapter 3 Hardware Serial Interface The Vortex CPU contains the circuitry for all four serial ports. The CoreModule 430 provides serial ports 1 and 2 through transceivers U7 and U9 (headers J3 and J9), serial port 3 through transceiver U4 (header J14) and serial port 4 through transceiver U5 (header J13).
Chapter 3 Hardware Table 3-6. Serial Ports 1 & 2 Interface Pin/Signal Descriptions (J3, J9) Pin # Signal DB9 # Description 1 DCD* 1 Data Carrier Detect – Indicates external serial device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input is driven by DTR as part of the DTR/ DSR handshake. 2 DSR* 6 Data Set Ready – Indicates external serial device is powered, initialized, and ready.
Chapter 3 Hardware Table 3-7. Serial Ports 3 & 4 Interface Pin/Signal Descriptions (J13, J14) (Continued) 4 RTS* 7 Request To Send – Indicates serial port is ready to transmit data. Used as hardware handshake with CTS for low level flow control. 5 TXD 3 Transmit Data – Serial port transmit data output is typically held to a logic 1 when no data is being sent. Typically, a logic 0 (On) must be present on RTS, CTS, DSR, and DTR before data can be transmitted on this line.
Chapter 3 Hardware Table 3-9. USB1 Interface Pin/Signal Designations (J17) (Continued) 4 GND USB1 Port ground 5 SHIELD USB1 Port shield Note: The shaded table cells denote power or ground. Utility Interface The Utility interface provides various utility and I/O signals on the module and consists of a 10-pin, 0.1" header. The Vortex CPU drives the signals on the Utility interface, and Table 3-10 provides the signal definitions.
Chapter 3 Hardware Table 3-10. Utility Interface Pin/Signal Descriptions (J5) (Continued) 9 BATV+ Real time battery voltage (3.0V Max) input 10 MCLK Mouse Clock input Notes: The shaded table cells denote power or ground. The * symbol indicates the signal is Active Low. Ethernet Interface The Ethernet solution originates from the Vortex 86SX/DX CPU and consists of both the Media Access Controller (MAC) and the physical layer (PHY) combined into a single component solution.
Chapter 3 Hardware Video (TTL/VGA) Interface The Volari Z9s graphics controller provides two graphics display ports for video signals to flat panel displays and traditional glass CRT monitors.
Chapter 3 Hardware Table 3-12. Video Interface Pin/Signal Descriptions (J11) (Continued) 12 FP5 Panel Data 5 – Refer to pin 9, FP2, for more information. 13 FP6 Panel Data 6 – Refer to pin 9, FP2, for more information. 14 FP7 Panel Data 7 – Refer to pin 9, FP2, for more information. 15 NC Not connected (FP8 = Panel Data 8) 16 NC Not connected (FP9 = Panel Data 9) 17 FP10 Panel Data 10 – Refer to pin 9, FP2, for more information.
Chapter 3 Hardware Serial Peripheral Interface (SPI) The CoreModule 430 provides an SPI header for programming the SPI Flash virtual floppy drive. Table 3-13 describes the pin signals of the SPI header, which provides a single-row of 6 pins with 0.079" (2mm) pitch. Table 3-13. SPI Interface Pin/Signal Descriptions (J19) Pin # Signal Description 1 EXT_CS* SPI Chip Select 2 EXT_CLK SPI Clock 3 EXT_DO SPI Data Out 4 EXT_DI SPI Data In 5 V.3.3 +3.
Chapter 3 Hardware User GPIO Interface The CoreModule 430 provides GPIO pins for customer use, and the signals are routed to header J8. An example of how to use the GPIO pins resides in the Miscellaneous Source Code Examples on the CoreModule 430 Support Software QuickDrive. The example program can be built by using the make.bat file. This produces a 16-bit DOS executable application, gpio.exe, which can be run on the CoreModule 430 to demonstrate the use of GPIO pins.
Chapter 3 Hardware Remote Access The CoreModule 430 BIOS supports the remote access (or console redirection) feature. This I/O function is provided by an ANSI-compatible serial terminal, or the equivalent terminal emulation software running on another system. This can be very useful when setting up the BIOS on a production line for systems that are not connected to a keyboard and display.
Chapter 3 Hardware Power Interface The CoreModule 430 requires one +5 volt DC power source. If the +5VDC power drops below ~4.65V, a low voltage reset is triggered, resetting the system. The power input header (J7) supplies the following voltages and ground directly to the module: • 5.0VDC +/- 5% @ 1.35 Amps Table 3-16 describes the pin signals of the Power interface, which uses a 10-pin, right-angle header with 2 rows, odd/even sequence (1, 2), and 0.100" (2.54mm) pitch. Table 3-16.
Chapter 3 32 Hardware Reference Manual CoreModule 430
Chapter 4 BIOS Setup Introduction This chapter assumes the user is familiar with general BIOS Setup and does not attempt to describe the BIOS functions. Refer to “BIOS Setup Screens” on page 35 in this chapter for a map of the BIOS Setup settings. If ADLINK has added to or modified any of the standard BIOS functions, these functions will be described. Entering BIOS Setup (Local Display) To access BIOS Setup using a local display for the CoreModule 430: 1.
Chapter 4 8. BIOS Setup Restore power to the CoreModule 430 and look for the screen prompt shown below. Press to update BIOS 9. Press the F4 key to enter Setup (early in the boot sequence if Quick Boot is set to [Enabled].) If Quick Boot is set to [Enabled], you may never see the screen prompt. 10. Use the key to select the screen menus listed in the Opening BIOS screen. NOTE The serial console port is not hardware protected.
Chapter 4 BIOS Setup BIOS Setup Screens This section provides illustrations of the seven main setup screens in the CoreModule 430 BIOS Setup Utility. Below each illustration is a bullet list of the screen’s submenus and setting selections. The setting selections are presented in brackets after each submenu or menu item and the optimal default settings are presented in bold. For more detailed definitions of the BIOS settings, refer to the AMIBIOS8 manual: http://www.ami.com/support/doc/MAN-EZP-80.
Chapter 4 BIOS Setup System Date (day of week, mm:dd:yyyy) – This field requires the alpha-numeric entry of the day of week, day of the month, calendar month, and all 4 digits of the year, indicating the century plus year (Fri 10/21/2011).
Chapter 4 BIOS Setup • PIO Mode – [Auto; 0; 1; 2; 3; 4] • DMA Mode – [Auto] • S.M.A.R.T. – [Auto; Disabled; Enabled] • 32Bit Data Transfer – [Disabled; Enabled] Primary IDE Slave • Type – [Not Installed; Auto; CD/DVD; ARMD] • LBA/Large Mode – [Disabled; Auto] • Block (Multi-Sector Transfer) – [Disabled; Auto] • PIO Mode – [Auto; 0; 1; 2; 3; 4] • DMA Mode – [Auto] • S.M.A.R.T.
Chapter 4 • BIOS Setup Legacy USB Support – [Disabled; Enabled; Auto] Note: If Disabled is selected, the following item disappears from the screen. • USB 2.
Chapter 4 BIOS Setup • PCI IDE BusMaster – [Disabled; Enabled] • OffBoard PCI/ISA IDE card – [Auto; PCI Slot1; PCI Slot2; PCI Slot3; PCI Slot4; PCI Slot5; PCI Slot6] • IRQ3 – [Available; Reserved] • IRQ4 – [Available; Reserved] • IRQ5 – [Available; Reserved] • IRQ6 – [Available; Reserved] • IRQ7 – [Available; Reserved] • IRQ9 – [Available; Reserved] • IRQ10 – [Available; Reserved] • IRQ11 – [Available; Reserved] • IRQ12 – [Available; Reserved] • IRQ14 – [Available; Reserved] • IRQ
Chapter 4 BIOS Setup BIOS Boot Setup Screen BIOS Setup Utility Main Advanced PCIPnP Boot Security Chipset Exit Boot Settings Boot Settings Configuration Select Screen Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit CM430_BIOS_BootScreen_a Boot Device Priority v02.xx (C) Copyright 1985-20xx, American Megatrends, Inc. Figure 4-4.
Chapter 4 BIOS Setup BIOS Security Setup Screen Main Advanced PCIPnP BIOS Setup Utility Boot Security Chipset Exit Security Settings Supervisor Password : Not installed User Password : Not installed Boot Sector Virus Protection [Disabled] Enter F1 F10 ESC Select Screen Select Item Change General Help Save and Exit Exit CM430_BIOS_SecurityScreen_a Change Supervisor Password Change User Password v02.xx (C) Copyright 1985-20xx, American Megatrends, Inc. Figure 4-5.
Chapter 4 BIOS Setup BIOS Chipset Setup Screen BIOS Setup Utility Main Advanced PCIPnP Boot Security Chipset Exit Advance Chipset Settings WARNING: Setting wrong values in below sections may cause system to malfunction. Select Screen Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit CM430_BIOS_ChipsetScreen_a NorthBridge Configuration SouthBridge Configuration v02.xx (C) Copyright 1985-20xx, American Megatrends, Inc. Figure 4-6.
Chapter 4 BIOS Setup • ISA 8bits I/O wait-state – [1 clock; 2 clock; 3 clock; 4 clock; 5 clock; 6 clock; 7 clock; 8 clock] • ISA 16bits Memory wait-state – [0 clock; 1 clock; 2 clock; 3 clock; 4 clock; 5 clock; 6 clock; 7 clock] • ISA 8bits Memory wait-state – [1 clock; 2 clock; 3 clock; 4 clock; 5 clock; 6 clock; 7 clock; 8 clock] Serial Port Configuration • SB Serial Port 1 – [Disabled; 3F8; 2F8; 3E8; 2E8; 10] - Serial Port IRQ 1 [IRQ3; IRQ4; IRQ9; IRQ10; IRQ11] - Serial Port Baud Rate [2400 B
Chapter 4 BIOS Setup • Port0 Bit6 Direction – [IN; OUT] • Port0 Bit7 Direction – [IN; OUT] • Port1 Function – [GPIO; PWM16. .PWM23] • Port1 Bit2 Direction – [IN; OUT] • Port1 Bit3 Direction – [IN; OUT] • Port1 Bit4 Direction – [IN; OUT] • Port1 Bit5 Direction – [IN; OUT] • Port1 Bit6 Direction – [IN; OUT] • Port1 Bit7 Direction – [IN; OUT] • Port2 Function – [GPIO; 8051 P2; PWM16. .
Chapter 4 BIOS Setup GPCS Configuration • GPCS0 Function – [Enabled; Disabled] • GPCS1 Function – [Enabled; Disabled] Redundancy Control Configuration • Dual Port 4 KB SRAM – [Enabled; Disabled] • SB Serial Port 9 – [Disabled; 3F8; 2F8; 3E8; 2E8; 10] • WatchDog0 Condition – [Disabled; Enabled] • WatchDog1 Condition – [Disabled; Enabled] • Invalid OPCODE Condition – [Disabled; Enabled] • KB/MS System Fail – [Normal; TRI-State] • GPIO PORT0 System Fail – [Normal; TRI-State] • GPIO PO
Chapter 4 BIOS Setup Save Changes and Exit The < F10 > key can be used for this operation. Discard Changes and Exit The < ESC > key can be used for this operation. Discard Changes The < F7 > key can be used for this operation. Load Optimal Defaults The < F9 > key can be used for this operation. Load Failsafe Defaults The < F8 > key can be used for this operation.
Appendix A Technical Support ADLINK Technology, Inc. provides a number of methods for contacting Technical Support listed in the Table A-1 below. Requests for support through the Ask an Expert are given the highest priority, and usually will be addressed within one working day. • ADLINK Ask an Expert – This is a comprehensive support center designed to meet all your technical needs. This service is free and available 24 hours a day through the Ampro By ADLINK web page at http://www.adlinktech.com/AAE/.
Appendix A Technical Support Table A-1. Technical Support Contact Information (Continued) ADLINK Technology Beijing Address: ࣫ҀᏖ⍋⎔ऎϞഄϰ䏃 1 োⲜ߯ࡼॺ E ᑻ 801 ᅸ(100085) Rm. 801, Power Creative E, No. 1, B/D Shang Di East Rd., Beijing, 100085 China Tel: +86-10-5885-8666 Fax: +86-10-5885-8625 Email: market@adlinktech.com ADLINK Technology Shenzhen Address: ⏅ഇᏖफቅऎ⾥ᡔುफऎ催ᮄफϗ䘧 ᭄ᄫᡔᴃು A1 ᷟ 2 ὐ C ऎ (518057) 2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7, High-Tech Industrial Park S.
Index A H ADLINK web site ............................................... 47 Advanced BIOS setup screen ............................. 36 assistance ............................................................ 47 header description table .......................................10 heatsink requirements ..........................................13 help ......................................................................47 Hot Cable, remote access ....................................
Index product description ............................................... 4 PS/2 keyboard and mouse ................................... 24 R Real Time Clock (RTC) ...................................... 28 references .............................................................. 1 remote access description ..................................................... 30 entering BIOS setup ...................................... 33 reset switch description and pin signal ............... 24 RS-232/RS-485 support ...
