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CoreModule

920

Single Board Computer

Reference Manual

P/N 50-1Z144-1020

Summary of content (64 pages)

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CoreModule® 920 Single Board Computer Reference Manual P/N 50-1Z144-1020
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Notice Page DISCLAIMER ADLINK Technology, Incorporated makes no representations or warranties with respect to the contents of this manual or of the associated ADLINK products, and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose. ADLINK shall under no circumstances be liable for incidental or consequential damages or related expenses resulting from the use of this product, even if it has been notified of the possibility of such damages.
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Contents Chapter 1 About This Manual ....................................................................................................1 Purpose of this Manual ....................................................................................................................1 References ......................................................................................................................................1 Chapter 2 Product Overview...........................................................
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Contents Chapter 4 BIOS Setup .............................................................................................................. 37 Introduction.................................................................................................................................... 37 Entering BIOS Setup (Local Video Display)............................................................................. 37 Entering BIOS Setup (Serial Port Console) .......................................................
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Contents Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 3-11. Table 3-12. Table 3-13. Table 3-14. Table 3-15. Table 3-16. Table 3-17. Table 3-18. Table 3-19. Table 4-1. Table A-1. CoreModule 920 USB2 and USB3 Interface Pin Signals (J25) .........................................................27 GLAN1 Interface Pin Signal Descriptions (H11) ....................................................28 GLAN2 Interface Pin Signal Descriptions (J14) .....................................................
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Contents vi Reference Manual CoreModule 920
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Chapter 1 About This Manual Purpose of this Manual This manual is for designers of systems based on the CoreModule® 920 Single Board Computer (SBC). This manual contains information that permits designers to create an embedded system based on specific design requirements.
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Chapter 1 • About This Manual SMBus Specification Version 2.0 Specification: http://smbus.org/specs/ • AMI BIOS Aptio TSE User’s Guide Data sheet: http://www.ami.com/support/doc/AMI_TSE_User_Manual_PUB.pdf Chip Specifications The following integrated circuits (ICs) are used in the CoreModule 920 SBC. • Intel Corporation and the Mobile 3rd Generation Core™i7 CPU integrated processor core and graphics memory hub Web site: http://www.intel.
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Chapter 1 About This Manual NOTE CoreModule 920 If you are unable to locate the datasheets using the links provided, search the internet using the name of the manufacturer or component model and locate the documents you need.
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Chapter 1 4 About This Manual Reference Manual CoreModule 920
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Chapter 2 Product Overview This overview presents general information about the PCI/104-Express form factor and the CoreModule 920 Single Board Computer (SBC). After reading this chapter you should understand the following points with regard to the CoreModule 920.
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Chapter 2 Product Overview Screws (4) 0.6 inch Spacers (4) PCIe/104 Module CoreModule 920 PCIe Bus Expansion Stackthrough Connectors (active heastsink exceeds height limit for stack-up capability on the CoreModule 920) PCI Bus Stackthrough Connectors 0.6 inch Spacers (4) CM920stackthru_a PCI-104 Module PCI Bus Stackthrough Connectors 0.6 inch Spacers (4) Nuts (4) or Chassis Standoffs Figure 2-1.
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Chapter 2 Product Overview Module Features • • • • • CPU  Provides a 1.
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Chapter 2 • • • USB 2.0 Interface  Provides two root USB 2.0 hubs  Provides up to six USB 2.0 ports  Supports USB bootable devices  Supports USB Keyboard and Mouse  Supports USB v2.0 EHCI and v1.
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Chapter 2 • • • Product Overview GPIO Interface  Provides two 6-pin interface headers  Supports a total of eight GPIO ports  Supports sample code in BSP QuickDrive Utility Interface  Power Button  Reset Switch  Speaker Miscellaneous  Real Time Clock (RTC) with external replaceable battery  Battery-free boot  Oops! Jumper support  Serial Console support  Watchdog Timer  Logo Screen (Splash)  SSD (Solid State Drive)  Hardware Monitor (voltage and temperature) Cor
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Chapter 2 Product Overview Block Diagram Figure 2-2 presents a functional representation of the CoreModule 920. 8x DDR3 SDRAM System Memory (2Gb each) 1333MHz, 1.5V, 2GB CPU Intel Core i7 3517UE (Dual-Core) 1.7GHz (17W) 1x DDR3 SDRAM System Memory (ECC) (2Gb each) Memory Bus (with integrated Processor Core and Graphics Memory Hub) PCIe x16 Graphics (1) [PEG], 1x16; 2x8; 1x8 & 2x4 FDI DMI SATA 3.0, Port 0 SATA0 Connector SATA1 Connector VGA SATA 3.
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Chapter 2 Product Overview Major Component (ICs) Definitions Table 2-1 lists the major ICs, including a brief description of each, on the CoreModule 920. Figures 2-3 and 2-4 show the locations of the major ICs. Table 2-1. Major Component Descriptions and Functions Chip Type Mfg. Model Description Function CPU (U1) Intel Core i7, 3517UE, 1.
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Chapter 2 Product Overview Table 2-1.
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Chapter 2 Product Overview Key: U1 - CPU U3 - DDR3 SDRAM U5 - DDR3 SDRAM U8 - DDR3 SDRAM U10 - DDR3 SDRAM U11 - DDR3 SDRAM (ECC) U12 - PCH U14 - Gigabit Ethernet PHY Transceiver U15 - Gigabit Ethernet MAC & PHY Controller U16 - Gigabit Ethernet EEPROM U17 - PCIe to PCI Bridge U48 - HDMI Level Shifter U17 U10 U1 U8 U48 U11 U12 CM920_Top_Comp_a U5 U3 U15 U14 U16 Figure 2-3.
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Chapter 2 Product Overview Header, Connector, and Socket Definitions Table 2-2 describes the headers, connectors, and socket of the CoreModule 920 shown in Figure 2-6. Table 2-2. Module Header and Connector Descriptions 14 Header # Board Access Description H11 – GLAN1 Top 10-pin, 0.100" (2.54mm) header for Gigabit Ethernet port 1 (JIH JVE, 21N22564-10S10B-01G-6/3-G) H15 – USB (0-1) Top 10-pin, 0.100" (2.54mm) header for USB 2.
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Chapter 2 Product Overview Table 2-2. Module Header and Connector Descriptions (Continued) J25 – USB 2-3 Top 10-pin, 0.079" (2mm) shrouded header for USB 2.0 ports 2-3 (HIROSE, DF11-10DP-2DSA) J26 – GPIO1 Top 6-pin, 0.079" (2mm) single-row header for GPIO1 (SAMTEC, TMM-106-03-L-S) J27 – GPIO2 Top 6-pin, 0.079" (2mm) single-row header for GPIO2 (SAMTEC, TMM-106-03-L-S) SW1 – PCIe x16 Lane Configuration Switch (see Figure 2-4 on page 13.
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Chapter 2 Product Overview J26 J27 JP2 JP1 J21 CM920_Top_Conn_b J22 J7 Key: H11 - GLAN1 H15 - USB 0-1 H16 - COM2 J2 - LED, GLAN1 (PHY Transceiver) J3 - LED, GLAN2 (Gb Controller) J5 - PCIe/104 J6 - PCIe/104 (see Bottom Component View) J7 - PCI-104 J8 - HDMI (Micro) J10 - SATA0 J12 - Battery J13 - SATA1 J14 - GLAN2 J17 - VGA J18 - COM1 J21 - Utility J22 - Fan J23 - LVDS J24 - Power J25 - USB 2-3 J26 - GPIO 5-8 J27 - GPIO 1-4 J25 J17 J12 J24 J13 H16 J8 J18 J10 H15 J23 H11 J14 J5 JP1 - LVDS Vo
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Chapter 2 Product Overview JP2 JP1 CM920_Top_jmpr_a Key: JP1 - LVDS Voltage JP2 - PCI-104 Voltage Figure 2-7. Jumper Header Locations (Top Side) Specifications Physical Specifications Table 2-4 provides the physical dimensions of the CoreModule 920. Table 2-4. Weight and Footprint Dimensions NOTE Item Dimension Weight 0.12 kg (0.25 lbs) Height (overall) 9.525mm (0.375 inches) Board thickness 2.362mm (0.093 inches) Width 96.01 mm (3.78 inches) Length 102.87 mm (4.
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Chapter 2 Product Overview 2.32in 3.25in 3.55in 59.05mm 82.55mm 90.17mm 0.3in 0.35in 7.62mm 7.62m 8.89mm 8.89m Mechanical Specifications 3.78in 95.89mm 3.78in 90.81mm m 3.58in 87.63mm m 3.45in 90.81mm 3.58in 87.63mm 3.45in 51.31mm 2.02in 40.81mm 1.61in 8.26mm CM920_Top_dmn_b 95.89mm m 3.35in 3.55in 4.05in 85.09mm 90.17mm 102.87mm 0.0mm 0.0in 0.0in 0.0in 0.0mm 0.2in 0.0mm 5.08mm 0.2in 0.33in 5.08mm 0.5in 8.26mm 0.2in 12.7mm 0.33in 5.08mm Figure 2-8.
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Chapter 2 Product Overview Power Specifications Table 2-5 provides the current measurements for the CoreModule 920. Table 2-5. Power Supply Requirements Parameter 1.7GHz CPU (3517UE) Input Type Regulated DC voltages In-Rush Peak Current and Duration See Figure 2-9 Typical Idle Current and Power 1.68A (8.41W) BIT Current and Power 4.41A (22.06W) Operating configurations: • In-rush operating configuration includes CRT monitor, 2GB memory, and power.
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Chapter 2 Product Overview Environmental Specifications Table 2-6 provides the most efficient operating and storage condition ranges required for this module. Table 2-6.
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Chapter 3 Hardware Overview This chapter discusses the chips and interfaces of the module in the following order: • CPU • Graphics • Memory • Interrupt Channel Assignments • Memory Map • I/O Address Map • Serial Port Interfaces • USB Interfaces • Ethernet Interface • Video Interfaces  VGA  LVDS  HDMI  PEG • Power Interface • GPIO Interface • Utility Interface  Power Button  Reset Switch  Speaker • System Fan Interface • Battery Interface • Ethernet LED In
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Chapter 3 Hardware NOTE ADLINK Technology, Inc. only supports the features and options listed in this manual. The main components used on the CoreModule 920 may provide more features or options than are listed in this manual. Some of these features and options are not supported on the module and will not function as specified in the chip documentation. The pin-out tables only of non-standard headers and connectors are included in this chapter.
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Chapter 3 Hardware Interrupt Channel Assignments The interrupt channel assignments are shown in Table 3-1. Table 3-1. Interrupt Channel Assignments Device vs IRQ No.
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Chapter 3 Hardware I/O Address Map Table 3-3 shows the I/O address map. These are DOS-level addresses. The OS typically hides these physical addresses by way of memory management. Table 3-3.
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Chapter 3 Hardware Serial Interfaces The CoreModule 920 provides two RS-232 serial ports. The PCH BD82QM67 contains the circuitry for both serial ports and delivers the signals through two RS-232 transceivers: one transceiver for COM1 and the second transceiver for COM2.
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Chapter 3 Hardware Table 3-4 defines the pins and corresponding signals for the Serial 2 header, which consists of 10 pins, 2 rows, odd/even sequence (1, 2), and 0.100" (2.54mm) pitch. Table 3-5. Serial 2 (COM2) Interface Pin Signal Descriptions (H16) Pin # Signal DB9 Pin # Description 1 S2_DCD* 1 COM2 Data Carrier Detect – Indicates external serial device is detecting a carrier signal (i.e., a communication channel is currently open).
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Chapter 3 Hardware USB Interface The CoreModule 920 contains two root USB hubs and six functional USB ports. Four of the six USB ports are routed through two 10-pin headers (H15 and J25), and the other two ports are routed through the PCIe/104 interface connector. The PCH provides the USB function including the following features: • Supports USB v.2.0 EHCI and USB v.1.
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Chapter 3 Hardware Ethernet Interfaces The CoreModule 920 supports two Gigabit Ethernet interfaces. The first Ethernet interface originates from the 82579LM PHY transceiver, which occupies one PCI Express lane and supports the internal MAC (Media Access Controller) in the PCH. The second Ethernet interface is implemented through the 82574IT Ethernet controller, which occupies one PCI Express lane and generates its own Gigabit Ethernet signals.
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Chapter 3 Hardware Table 3-9 describes the pin signals of the Ethernet GLAN2 interface, which consists of a two-row, 10-pin vertical header with odd/even (1,2) pin sequence, and 0.079" (2mm) pitch. Table 3-9.
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Chapter 3 Hardware • Supports DVD-Audio and Audio Return channel • Provides one 19-pin, standard HDMI micro connector PEG (PCI Express Graphics): • Supports external high-performance PCI Express graphics cards • Supports general-purpose PCI Express devices • Supports theoretical bandwidth of up to 8GT/s • Provides PCIe Gen3 compliance Table 3-10 defines the signals of the VGA interface, which consists of 10 pins, 2 rows, odd/even, (1, 2) with 0.079" (2mm) pitch. Table 3-10.
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Chapter 3 Hardware Table 3-11. LVDS Video Interface Pin Signals (J23) (Continued) Pin # Signal Description 13 LVDSA_DAT0_P LVDS A DATA Positive Line 0 14 LVDSA_DAT0_N LVDS A DATA Negative Line 0 15 LBKLT_CTL Panel Backlight Control 16 LVDD_EN Enable Panel Power 17 LDDC_CLK Display Data Channel Clock 18 LDDC_DATA Display Data Channel Data 19 LBKLT_EN Enable Backlight Inverter 20 NC Not Connected Note: The shaded table cells denote power or ground.
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Chapter 3 Hardware User GPIO Interface The CoreModule 920 provides GPIO pins for customer use, routing the signals from the PCH chipset to the J26 and J27 headers. An example test application and source code reside in each BSP directory of the CoreModule 920 Support Software QuickDrive. For instructions on using the example applications, refer to the GPIO Readme in each BSP directory of the QuickDrive. For more information about the GPIO pin operation, refer to the PCH BD82QM67 datasheet at: http://www.
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Chapter 3 Hardware Utility Interface The Utility interface provides three I/O signals on the module and consists of a 5-pin, 0.100" (2.54mm), single-row header (J21). The CPU drives the Power Button and Speaker signals on the Utility interface. A separate Power Management microprocessor drives the Reset Switch signal. Table 3-15 provides the signal definitions.
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Chapter 3 Hardware Battery Table 3-17 lists the pin signals of the External Battery Input header for backup RTC (Real Time Clock), which provides 2 pins with 0.049" (1.25mm) pitch. Table 3-17. External Battery Input Header (J12) Pin # Signal Description 1 V_BATT +3.0 volts DC 2 GND Ground Note: The shaded table cells denote power or ground. The RTC has an expected current draw of 6A at room temperature, with +3.0V. The battery is used only when power is not applied to the board.
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Chapter 3 Hardware Miscellaneous SSD (Solid State Drive) The CoreModule 920 provides an 8GB SSD, which is soldered directly onto the board. For more information refer to the SSD data sheet: http://www.greenliant.com/products/solid_state_storage.dot#sn. Real Time Clock (RTC) The CoreModule 920 contains a Real Time Clock (RTC). The RTC can be backed up with a battery. If the battery is not present, the board BIOS has a battery-less boot option to complete the boot process.
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Chapter 3 Hardware Hardware Voltage and Temperature Monitor The CoreModule 920 provides a hardware monitor to ensure the health of your embedded system with builtin support for monitoring and control of system temperatures, fan speeds, and critical module voltage levels. The ADT 7490 Hardware Monitor BIOS setting resides in the Advanced menu of the BIOS setup utility. See Chapter 4, “BIOS Setup” .
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Chapter 4 BIOS Setup Introduction This section assumes the user is familiar with general BIOS Setup and does not attempt to describe the BIOS functions. Refer to “BIOS Setup Menus ” on page 39 in this chapter for a map of the BIOS Setup settings. If ADLINK has added to or modified any of the standard BIOS functions, these functions will be described. Entering BIOS Setup (Local Video Display) To enter BIOS Setup using a local video display for the CoreModule 920: 1.
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Chapter 4 BIOS Setup 8. Restore power to the CoreModule 920. 9. Press the F2 key to enter Setup (early in the boot sequence if Fast Boot is set to [Enabled].) If Fast Boot is set to [Enabled], you may never see the screen prompt. 10. Use the key to select the screen menus listed in the Opening BIOS screen. NOTE The serial console port is not hardware protected. Diagnostic software that probes hardware addresses may cause a loss or failure of the serial console functions.
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Chapter 4 BIOS Setup BIOS Setup Menus This section provides illustrations of the six main setup screens in the CoreModule 920 BIOS Setup Utility. Below each illustration is a bullet list of the screen’s submenus and setting selections. The setting selections are presented in brackets after each submenu or menu item, and the optimal default settings are presented in bold. For more detailed definitions of the BIOS settings, refer to the AMI Aptio TSE User Manual: http://www.ami.
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Chapter 4 BIOS Setup • System Language • System Date [English] System Date (day of week, mm:dd:yyyy) – This field requires the alpha-numeric entry of the day of week, day of the month, calendar month, and all 4 digits of the year, indicating the century plus year (Fri XX/XX/20XX). • System Time System Time (hh:mm:ss) – This is a 24-hour clock setting in hours, minutes, and seconds. Advanced BIOS Setup Screen Aptio Setup Utility - Copyright (C) 20XX American Megatrends, Inc.
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Chapter 4 • BIOS Setup  Min CPU Speed XXX MHz  Processor Cores X  Intel HT Technology Supported  Intel VT-x Technology Supported  Intel SMX Technology Supported  64-bit Supported  L1 Data Cache 32 kB x 2  L1 Code Cache 32 kB x 2  L2 Cache 256 kB x 2  L3 Cache 4096 kB x2  Hyper-Threading [Disabled; Enabled]  Active Processor Cores [All; 1]  Limit CPUID Maximum [Disabled; Enabled]  Execute Disable Bit [Disabled; Enabled]  Intel Virtualization Technology
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Chapter 4 • • • BIOS Setup PCH-FW Configuration  ME FW Version X.X.XX.
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Chapter 4   BIOS Setup F81216 Serial Port 2 Configuration • Serial Port [Disabled; Enabled] • Device Settings IO=2F8h; IRQ=3; • Change Settings [Auto; IO=2E8h; IRQ=10; IO=3F8h; IRQ=3, 4, 5, 6, 7, 9, 10, 11, 12; IO=2F8h; IRQ=3, 4, 5, 6, 7, 9, 10, 11, 12; IO=3E8h; IRQ=3, 4, 5, 6, 7, 9, 10, 11, 12; IO=2E8h; IRQ=3, 4, 5, 6, 7, 9, 10, 11, 12; IO=2E0h; IRQ=3, 4, 5, 6, 7, 9, 10, 11, 12; IO=2F0h; IRQ=3, 4, 5, 6, 7, 9, 10, 11, 12] F81216 Watchdog • • Enable Watchdog [Disabled; Enabled] Serial Port
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Chapter 4  BIOS Setup COM (SOL) (Pci Bus0, Dev22, Func3) • Console Redirection [Disabled; Enabled] • Console Redirection Settings - Terminal Type [VT100; VT100+; VT-UTF8; ANSI] - Bits per second [9600; 19200; 38400; 57600; 115200] - Data Bits [7; 8] - Parity [None; Even; Odd; Mark; Space] - Stop Bits [1; 2] - Flow Control [None; Hardware RTS/CTS] - VT-UTF8 Combo Key Support [Disabled; Enabled] - Recorder Mode [Disabled; Enabled] - Resolution 100x31 [Disabled; Enabled] - Legacy OS Redirection [80x24; 8
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Chapter 4      BIOS Setup DIV-2S • DIV-2S • Not used • Maximum supported frequency XXX.XX MHz • Minimum supported frequency XXX.XX MHz • Current frequency XXX.XX MHz • Current SSC mode Down • Current SSC % X.XX% DIV3 • DIV3 • Not used • Maximum supported frequency XXX.XX MHz • Minimum supported frequency XXX.XX MHz • Current frequency XXX.XX MHz • Current SSC mode Down • Current SSC % X.XX% DIV4 • DIV4 • GFX Bending • Maximum supported frequency XXX.
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Chapter 4 • BIOS Setup Display addon PCI/PCIE at POST  • DAPP Enabled [Disabled; Enabled] CPU PPM Configuration  EIST (Intel SpeedStep) [Disabled; Enabled]  Turbo Mode [Disabled; Enabled]  Power Consumption [XXX]  CPU C3 Report [Disabled; Enabled]  CPU C6 Report [Disabled; Enabled]  CPU C7 Report [Disabled; Enabled] Chipset BIOS Setup Screen Aptio Setup Utility - Copyright (C) 20XX American Megatrends, Inc.
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Chapter 4    BIOS Setup PCI Express Configuration • Subtractive Decode [Disabled; Enabled] • PCI Express Root Port 1 [Disabled; Enabled] • PCI Express Root Port 2 [Disabled; Enabled] • PCI Express Root Port 3 [Disabled; Enabled] • PCI Express Root Port 4 [Disabled; Enabled] USB Configuration • EHCI1 [Disabled; Enabled] • EHCI2 [Disabled; Enabled] PCH Azalia Configuration •  • Azalia [Disabled; Enabled; Auto] PCH LAN Controller [Enabled; Disabled] System Agent (SA) Configuration 
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Chapter 4 BIOS Setup 1680x1050 LVDS; 1920x1200 LVDS; 1024x600 LVDS; 1280x600 LVDS; 1280x768 LVDS; 1280x800 LVDS; 1920x1080 LVDS; 2048x1536 LVDS] - Active LFP [No LVDS; Int-LVDS] - Panel Color Depth [18 Bit; 24 Bit] - GTT LVDS Backlight Control [0%; 20%; 40%; 60%; 80%; 100%] - GTT LVDS Backlight Inverter [PWM Inverted; PWM Normal]  NB PCIe Configuration • •  PEG0 XXXX - PEG0 - Gen X [Auto; Gen1; Gen2; Gen3] - PEG0 ASPM [Disabled; Auto; ASPM L0s; ASPM L1; ASPM L0sL1] Enable PEG [Disabled; Enabled
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Chapter 4 BIOS Setup Boot BIOS Setup Screen Aptio Setup Utility - Copyright (C) 20XX Amreican Megatrends, Inc. Advanced Chipset Boot Security Save & Exit [Setting Description] Boot Configuration Setup Prompt Timeout Bootup NumLock State 1 [On] Quiet Boot Fast Boot [Disabled] [Disabled] CSM16 Module Version XX.
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Chapter 4  BIOS Setup CSM parameters • Launch CSM [Always; Never] • Boot option filter [UEFI and Legacy; Legacy only; UEFI only] • Launch PXE OpROM policy [Do not launch; UEFI only; Legacy only] • Launch Storage OpROM policy [Do not launch; UEFI only; Legacy only] • Launch Video OpROM policy [Do not launch; UEFI only; Legacy only] • Other PCI device ROM priority [UEFI only; Legacy OpROM] Security BIOS Setup Screen Aptio Setup Utility - Copyright (C) 20XX American Megatrends, Inc.
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Chapter 4 BIOS Setup • HDD0: GLS85LS1008P - HDD Password Description: Allows Access to Set, Modify and Clear HardDisk User and Master Passwords. User Password need to be installed for Enabling Security. Master Password can be modified only when successfully unlocked with Master Password in POST.
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Chapter 4 • BIOS Setup Exit and Reset Options  Save Changes and Exit •  Discard Changes and Exit •  Save Changes •   Load Optimized Defaults? [Yes; No] Save as User Defaults •  Load Previous Values? [Yes; No] Restore Defaults •  Save configuration? [Yes; No] Discard Changes • Save configuration? [Yes; No] Restore User Defaults • Restore User Defaults? [Yes; No] Boot Override  SATA PS: GLS85LS1008P CS XXGB •  Save configuration and reset? [Yes; No] Launch EFI Shell from fil
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Appendix A Technical Support ADLINK Technology, Inc. provides a number of methods for contacting Technical Support listed below in Table A-1. Requests for support through the Ask an Expert are given the highest priority, and usually will be addressed within one working day. • ADLINK’s Ask an Expert – This is a comprehensive support center designed to meet all your technical needs. This service is free and available 24 hours a day through the Ampro By ADLINK web page at http://www.adlinktech.com/AAE/.
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Appendix A Technical Support Table A-1. Technical Support Contact Information (Continued) ADLINK Technology Beijing Address: ࣫ҀᏖ⍋⎔ऎϞഄϰ䏃 1 োⲜ߯ࡼ࡯໻ॺ E ᑻ 801 ᅸ(100085) Rm. 801, Power Creative E, No. 1, Shang Di East Rd., Beijing, 100085 China Tel: +86-10-5885-8666 Fax: +86-10-5885-8626 Email: market@adlinktech.com ADLINK Technology Shenzhen Address: ⏅ഇᏖफቅऎ⾥ᡔುफऎ催ᮄफϗ䘧 ᭄ᄫᡔᴃು A1 ᷟ 2 ὐ C ऎ (518057) 2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7, High-Tech Industrial Park S.
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Appendix A Technical Support Table A-1. Technical Support Contact Information (Continued) ADLINK Technology, Inc. (Israeli Liaison Office) Address: 27 Maskit St., Corex Building PO Box 12777 Herzliya 4673300, Israel Tel: +972-77-208-0230 Fax: +972-77-208-0230 Email: israel@adlinktech.
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Appendix A 56 Technical Support Reference Manual CoreModule 920
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Index A G AMI BIOS Aptio TSE User’s Guide .................... 2 Ask an Expert (on line) ....................................... 53 GPIO interface description ......................................32 interface features ..............................................9 graphics description .............................................22 B battery free boot feature .............................................. 9 interface description ...................................... 34 BIOS access to Setup Utility ..
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Index P PCH specification reference ................................. 2 PCI features ............................................................ 7 specification reference .................................... 1 PCI Express features ............................................................ 7 specification reference .................................... 1 x16 graphics features ....................................... 8 PCI/104-Express form factor ................................ 5 physical specifications ..