DAQ-/DAQe-/PXI2016/2010/2006/2005 4-CH, Simultaneous, High Performance Multi-Function Data Acquisition Card User’s Manual Manual Rev. 2.01 Revision Date: March 12, 2007 Part No: 50-11219-2000 Advance Technologies; Automate the World.
Copyright 2007 ADLINK TECHNOLOGY INC. All Rights Reserved. The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.
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Using this manual 1.1 Audience and scope This manual guides you when using ADLINK multi-function DAQ-/ DAQe-/PXI-2016/2010/2006/2005 card. The card’s hardware, signal connections, and calibration information are provided for faster application building. This manual is intended for computer programmers and hardware engineers with advanced knowledge of data acquisition and high-level programming. 1.
1.3 Conventions Take note of the following conventions used throughout the manual to make sure that you perform certain tasks and instructions properly. NOTE Additional information, aids, and tips that help you perform particular tasks. IMPORTANT Critical information and instructions that you MUST perform to complete a task. WARNING Information that prevents physical injury, data loss, module damage, program corruption etc. when trying to complete a particular task.
Table of Contents Table of Contents..................................................................... i List of Tables.......................................................................... iii List of Figures ........................................................................ iv 1 Introduction ........................................................................ 1 1.1 1.2 1.3 1.4 Features............................................................................... 2 Applications ..........
4 Operation Theory .............................................................. 29 4.1 4.2 4.3 4.4 4.5 4.6 A/D Conversion.................................................................. 29 DAQ-/DAQe-/PXI-2010 AI Data Format ....................... 30 DAQ/DAQe/PXI-2005/2006/2016 AI Data Format ........ 33 Software Conversion with Polling Data Transfer Acqui-sition Mode (Software Polling) ..................................... 34 Programmable Scan Acquisition Mode .........................
List of Tables Table Table Table Table Table Table 1-1: 1-2: 1-3: 3-1: 3-2: 3-3: Table 3-4: Table 4-1: Table 4-2: Table 4-3: Table 4-4: Table 4-5: Table 4-6: Table 4-7: Table 4-8: Table 4-9: Table 4-10: List of Tables -3dB Small Signal Bandwidth ................................... 5 System Noise ........................................................... 5 CMRR: (DC to 60 Hz) ............................................... 7 VHDCI-type (68-pin) Connector Pin Assignment ...
List of Figures Figure 2-1: DAQe-2016/2010/2006/2005 Card Layout .............. Figure 2-2: DAQ-2016/2010/2006/2005 Card Layout ................ Figure 2-3: PXI-2016/2010/2006/2005 Card Layout .................. Figure 3-1: Single-Ended Connections ...................................... Figure 3-2: Ground-referenced Source and Differential Input.... Figure 3-3: Floating Source and Differential Input ..................... Figure 4-1: Synchronous Digital Inputs Block Diagram..............
Figure 4-31: Analog Trigger Block Diagram................................. Figure 4-32: Below-Low Analog Trigger Condition ...................... Figure 4-33: Above-High Analog Trigger Condition ..................... Figure 4-34: Inside-Region Analog Trigger Condition.................. Figure 4-35: High-Hysteresis Analog Trigger Condition .............. Figure 4-36: Low-Hysteresis Analog Trigger Condition ............... Figure 4-37: External Digital Trigger ............................................
1 Introduction The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card is an advanced data acquisition card based on the 32-bit PCI or PCI Express® architecture. High performance designs and state-of-the-art technology make these cards ideal for data logging and signal analysis applications in medical, process control, etc.
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X -3dB small signal bandwidth: (Typical, 25°C) Device Input Range Bandwidth (-3dB) Input Range Bandwidth (-3dB) 2010 2005 2006 2016 ±10V 1170 kHz 0~10V 1090 kHz ±5V 1050 kHz 0~5V 1020 kHz ±2.5V 800 kHz 0~2.5V 790 kHz ±1.25V 530 kHz 0~1.25V 530 kHz ±10V 1160 kHz 0~10V 1210 kHz ±5V 1050 kHz 0~5V 1050 kHz ±2.5V 780 kHz 0~2.5V 770 kHz ±1.25V 520 kHz 0~1.25V 530 kHz ±10V 630 kHz 0~10V 640 kHz ±5V 620 kHz 0~5V 620 kHz ±2.5V 540 kHz 0~2.5V 540 kHz ±1.
Device Input Range System noise Input Range System noise 2006 2016 ±10V 1.0 LSBrms 0~10V 1.5 LSBrms ±5V 1.0 LSBrms 0~5V 1.6 LSBrms ±2.5V 1.1 LSBrms 0~2.5V 1.7 LSBrms ±1.25V 1.1 LSBrms 0~1.25V 1.8 LSBrms ±10V 1.6 LSBrms 0~10V 2.9 LSBrms ±5V 1.8 LSBrms 0~5V 3.2 LSBrms ±2.5V 1.8 LSBrms 0~2.5V 3.2 LSBrms ±1.25V 1.9 LSBrms 0~1.25V 3.
X CMRR: (DC to 60 Hz, Typical) Device Input Range CMRR Input Range CMRR 2010 2005 2006 2016 ±10V 90 dB 0~10V 89 dB ±5V 92 dB 0~5V 92 dB ±2.5V 95 dB 0~2.5V 94 dB ±1.25V 97 dB 0~1.25V 97 dB ±10V 86 dB 0~10V 85 dB ±5V 88 dB 0~5V 88 dB ±2.5V 91 dB 0~2.5V 90 dB ±1.25V 93 dB 0~1.25V 93 dB ±10V 87 dB 0~10V 86 dB ±5V 89 dB 0~5V 88 dB ±2.5V 91 dB 0~2.5V 91 dB ±1.25V 93 dB 0~1.25V 93 dB ±10V 85dB 0~10V 86dB ±5V 88dB 0~5V 88dB ±2.5V 91dB 0~2.5V 92dB ±1.
X 8 Gain error: Z Before calibration: ±0.6% of output max Z After calibration: ±0.1% of output max for DAQ-/DAQe-/ PXI-2010, ±0.
Analog Output (AO) X Number of channels: Two-channel voltage output X DA converter: LTC7545 or equivalent X Max update rate: 1 MS/s X Resolution: 12 bits X FIFO buffer size: X X Z 1k samples per channel when both channels are enabled for timed DA output Z 2k samples when only one channel is used for timed DA output Data transfers: Z Programmed I/O Z Bus-mastering DMA with scatter/gather Output range: Z Bipolar: ±10V or ±AOEXTREF Z Unipolar: 0~10V or 0~AOEXTREF X Settling time: 3μS t
X Gain error: Z Before calibration: ±0.8% of output max Z After calibration: ±0.02% of output max X General Purpose Digital I/O (G.P. DIO, 82C55A) X Number of channels: 24 programmable input/output X Compatibility: TTL/CMOS X Input voltage: X Z Logic Low: VIL=0.8V max; IIL=0.2mA max Z High: VIH=2.0V max; IIH=0.02mA max Output voltage: Z Low: VOL=0.5V max; IOL=8mA max Z High: VOH=2.
Analog Trigger (A.Trig) X Source: Z All analog input channels Z External analog trigger (EXTATRIG) X Level: ±Full-scale, internal; ±10 V external X Resolution: 8 bits X Slope: Positive or negative (software-selectable) X Hysteresis: Programmable X Bandwidth: 400 kHz External Analog Trigger Input (EXTATRIG) X Input Impedance: Z 40 kΩ for DAQ-/DAQe-/PXI-2010 Z 2 kΩ for DAQ-/DAQe-/PXI-2005/2006/2016 X Coupling: DC X Protection: Continuous ±35 V maximum Digital Trigger (D.
Physical X X Dimensions: Z 175mm by 107mm for DAQ-/DAQe-2010/2000 Z Standard CompactPCI form factor for PXI-2010/2000 I/O connector: 68-pin female VHDCI type (e.g. AMP787254-1) Power Requirement (typical) X X X +5VDC Z 1.82 A for DAQ-/PXI-2010 Z 2.04 A for DAQ-/PXI-2005 Z 1.82 A for DAQ-/PXI-2006 Z 2.52 A for DAQ-/PXI-2016 +12 VDC Z 550 mA for DAQe-2005 Z 460 mA for DAQe-2006 Z 448 mA for DAQe-2010 Z 569 mA for DAQe-2016 +3.3 VDC Z 1.02 A for DAQe-2005 Z 1.
1.4 Software Support ADLINK provides versatile software drivers and packages for users’ different approach to building up a system. ADLINK not only provides pro-gramming libraries such as DLL for most Windowsbased systems, but also provide drivers for other software packages such as LabVIEW®. All software options are included in the ADLINK CD. Non-free software drivers are protected with licensing codes.
DAQ-LVIEW PnP: LabVIEW Driver DAQ-LVIEW PnP contains the VIs, which are used to interface with NI’s LabVIEW software package. The DAQ-LVIEW PnP supports Windows 98/NT/2000/XP. The LabVIEW drivers is shipped free with the card. You can install and use them without a license. For detailed information about DAQ-LVIEW PnP, refer to the user’s guide in the CD.
2 Installation This chapter describes how to install the DAQ-/DAQe-/PXI-2016/ 2010/2006/2005 card. The contents of the package and unpacking information that you should be aware of are outlined first. The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card performs an automatic configuration of the IRQ and port address. You can use the PCI_SCAN software utility to read the system configuration. 2.
Again, inspect the module for damages. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module place on a firm flat surface. You are now ready to install your DAQ-/DAQe-/PXI-2016/2010/ 2006/2005 card. NOTE 16 DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED.
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DAQ-2016/2010/2006/2005 Figure 2-2: DAQ-2016/2010/2006/2005 Card Layout PXI-2016/2010/2006/2005 Figure 2-3: PXI-2016/2010/2006/2005 Card Layout 18 Installation
2.4 PCI Configuration Plug and Play With support for plug and play, the card requests an interrupt number via its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These system parameters are determined by the installed drivers and the hardware load seen by the system. Configuration The board configuration is done on a board-by-board basis for all PCI boards in the system.
20 Installation
3 Signal Connections This chapter describes DAQ-/DAQe-/PXI-2016/2010/2006/2005 card connectors and the signal connection between the DAQ-/ DAQe-/PXI-2016/2010/2006/2005 card and external devices. 3.1 Connectors Pin Assignment The DAQe-/PXI-2016/2010/2006/2005 card is equipped with one 68-pin VHDCI-type connector (AMP-787254-1). It is used for digital input/output, analog input/output, timer/counter signals, etc.
VHDCI-type (68-pin) Connector CH0+ CH1+ CH2+ CH3+ EXTATRIG DA1OUT DA0OUT AOEXTREF SDI3_1 / NC* SDI2_1 / NC* SDI1_1 / NC* SDI0_1 / NC* AO_TRIG_OUT AI_TRIG_OUT GPTC1_SRC GPTC0_SRC GPTC0_GATE GPTC0_OUT GPTC0_UPDOWN EXTTIMEBASE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 CH0CH1CH2CH3AIGND AOGND AOGND AOGND SDI3_0 / NC* SDI2_0 / NC* SDI1_0 / NC* SDI0_0 / NC* EXTWFTRG EXTDTRIG DGND DGND GPTC1_GATE GPTC1_OUT GPTC1_UPDOWN DGND Table 3-1: VHDCI-t
Legend: Pin # Signal Name Reference Direction Description 1~4 CH<0..3>+ CH0<0..3>- Input Differential positive input for AI channel <0..3> 5 EXTATRIG AIGND Input External AI analog trigger 6 DA0OUT AOGND Output AO channel 0 7 DA1OUT AOGND Output AO channel 1 8 AOEXTREF AOGND Input External reference for AO channels 9~12 SDI<3..
Pin # Signal Name Reference Direction 35~38 CH<0..3>- -------- Input Description Differential negative input for AI channel <0..3> 39 AIGND -------- -------- Analog ground for AI 40~42 AOGND -------- -------- Analog ground for AO 43~46 SDI<3..
SSI Connector (J3) SSI_TIMEBASE 1 2 DGND SSI_ADCONV 3 4 DGND SSI_DAWR 5 6 DGND SSI_SCAN_START 7 8 DGND RESERVED 9 10 DGND SSI_AD_TRIG 11 12 DGND SSI_DA_TRIG 13 14 DGND RESERVED 15 16 DGND RESERVED 17 18 DGND RESERVED 19 20 DGND Table 3-3: SSI Connector (JP3) Pin Assignment for DAQ Models Legend: SSI timing signal Functionality SSI_TIMEBASE SSI master: send the TIMEBASE out SSI slave: accept the SSI_TIMEBASE to replace the internal TIMEBASE signal.
3.2 Analog Input Signal Connection The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card provides 4 differential analog input channels. The analog signal can be converted to digital values by the A/D converter. To avoid ground loops and get more accurate measurements from the A/D conversion, it is quite important to understand the signal source type and how to connect the analog input signals.
Figure 3-1: Single-Ended Connections In single-ended configurations, more electrostatic and magnetic noise couples into the single connections than in differential configurations. Therefore, the single-ended connection is not recommended unless minimal wire connections are necessary. Differential Measurements Differential Sources Connection for Grounded-Reference Signal The differential analog input provides two inputs that respond to the signal voltage difference between them.
Differential Connection for Floating Signal Sources Figure 3-3 shows how to connect a floating signal source to DAQ-/DAQe-/PXI-2016/2010/2006/2005 card in differential input mode. For floating signal sources, you need to add a resistor at each channel to provide a bias return path. The resistor value should be about 100 times the equivalent source impedance.
4 Operation Theory The operation theory of the DAQ-/DAQe-/PXI-2016/2010/2006/ 2005 card functions are described in this chapter. The functions include the A/D conversion, D/A conversion, digital I/O, and general purpose counter/timer. The operation theory can help you understand how to configure and program the DAQ-/DAQe-/PXI2016/2010/2006/2005 card.
DAQ-/DAQe-/PXI-2010 AI Data Format Synchronous Digital Inputs (DAQ-/DAQe-/PXI-2010 only) When each A/D conversion is completed, the 14-bits converted digital data accompanied with 2 bits of SDI<1..0>_X per channel from J5 will be latched into the 16-bit register and data FIFO as shown in Figure 4-1 and Figure 4-2. Therefore, you can simultaneously sample one analog signal with four digital signals. The data format of every acquired 16-bit data is as follows: D13, D12, D11 .......
NOTE Since the analog signal is sampled when an A/D conversion starts (falling edge of A/D_conversion signal), while SDI<1..0> are sam-pled right after an A/D conversion completes (rising edge of nADBUSY signal). Precisely SDI<1..0> are sampled within 220 to 400ns lag to the analog signal, due to the variation of the conversion time of the A/D converters. Table 4-1and Table 4-2 illustrate the ideal transfer characteristics of various input ranges of DAQ/DAQe/PXI-2000/2010 Series card.
Description Full-scale Range Least significant bit FSR-1LSB Midscale +1LSB Midscale Midscale –1LSB -FSR Unipolar Analog Input Range 0V to 10V 0 to +5V 0 to +2.5V 0 to +1.25V 0.61mV 0.305mV 0.153mV 9.9994V 4.9997V 2.9999V 5.00061V 2.50031V 1.25015V 5V 2.5V 1.25V 4.99939V 2.49970V 1.24985V 0V 0V Digital code 0V 76.3uV 1.2499V 1FFF 625.08mV 0001 625mV 0000 624.
DAQ/DAQe/PXI-2005/2006/2016 AI Data Format The data format of the acquired 16-bit A/D data is binary coding. Table 4-3 and Table 4-4 illustrate the valid input ranges and the ideal transfer characteristics. The converted digital codes for DAQ/ DAQe/PXI-2005/2006/2016 are 16-bit and direct binary, and here the codes were presented as hexadecimal numbers. Description Full-scale Range Least significant bit FSR-1LSB Bipolar Analog Input Range Digital code ±10V ±5V ±2.5V ±1.25V 305.2uV 152.6uV 76.
Software Conversion with Polling Data Transfer Acquisition Mode (Software Polling) This is the easiest way to acquire a single A/D data. The A/D converter starts one conversion whenever the dedicated software command is executed. Then the software would poll the conversion status and read the A/D data back when it is available. This method is very suitable for applications that needs to process A/D data in real time. Under this mode, the timing of the A/D conversion is fully controlled by the software.
Programmable Scan Acquisition Mode Scan Timing and Procedure It's recommended that this mode be used if your applications need a fixed and precise A/D sampling rate. You can accurately program the period between conversions of individual channels. There are at least two counters which need to be specified: SI_counter (24 bit):Specify the Scan Interval = SI_counter / TIMEBASE PSC_counter (24 bit):Specify Post Scan Counts, i.e.
while the minimum should be 1 MHz. Refer to section 4.6 for information on user-controllable timing signals. Figure 4-3: Scan Timing There are four trigger modes to start the scan acquisition. Refer to section 4.1 for details. The data transfer mode is discussed in the following section. NOTES The maximum A/D sampling rate is 2 MHz for DAQ/ DAQe/PXI-2010, 500 kHz for DAQ/DAQe/PXI-2005, 250 kHz for DAQ/DAQe/PXI-2006 and 800 kHz for DAQ/ DAQe/PXI-2016.
Trigger Modes The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card provides four trigger sources (internal software trigger, external analog trigger, external digital trigger, and SSI trigger signals). You must select one of them as the source of the trigger event. A trigger event occurs when the specified condition is detected on the selected trigger source. For example, a rising edge on the external digital trigger input. Refer to section 4.6 for more information on SSI signals.
Figure 4-4: Pre-trigger Note that If the trigger event occurs when a conversion is in progress, the data acquisition will not stop until this conversion is completed and the stored M scans of data include the last scan, as illustrated in Figure 4-5, where M_counter = M = 3, PSC_counter = 0.
When the trigger signal occurs before the first M scans of data are converted, the amount of stored data could be fewer than the originally specified amount M_counter, as illustrated in Figure 4-6. This situation can be avoided by setting M_enable. If M_enable is set to 1, the trigger signal will be ignored until the first M scans of data are converted, and it assures the user M scans of data under pre-trigger mode, as illustrated in Figure 4-7.
Figure 4-7: Pre-trigger with M_enable=1 NOTE The PSC_counter is set to 0 in pre-trigger acquisition mode. Middle-Trigger Acquisition Use middle-trigger acquisition in applications where you want to collect data before and after a trigger event. The number of scans (M) stored before the trigger is specified in M_counter, while the number of scans (N) after the trigger is specified in PSC_counter.
Figure 4-8: Middle-Trigger with M_enable = 1 If the trigger event occurs when a scan is in progress, the stored N scans of data would include this scan, as illustrated in Figure 4-9.
NOTE The M_counter defined in Middle-Trigger is different from that of the Pre-Trigger. In Middle-Trigger, M_Counter ends counting before the trigger event while in Pre-Trigger, M_Counter ends counting right at or before trigger event. Refer to Figure 4-6 and Figure 4-9. Post-Trigger Acquisition Use post-trigger acquisition in applications where you want to collect data after a trigger event. The number of scans after the trigger is specified in PSC_counter, as illustrated in Figure 4-10.
Delay Trigger Acquisition Use delay trigger acquisition in applications where you want to delay the data collection after the occurrence of a specified trigger event. The delay time is controlled by the value, which is pre-loaded in the Delay_counter (16-bit). The counter counts down on the rising edge of the Delay_counter clock source after the trigger condition is met. The clock source can be software-programmed either by the TIMEBASE clock (40 MHz) or A/D sampling clock (TIMEBASE / SI_counter).
Post-Trigger or Delay-trigger Acquisition with re-trigger Use post-trigger or delay-trigger acquisition with re-trigger function in applications where you want to collect data after several trigger events. The number of scans after each trigger is specified in PSC_counter, and users could program Retrig_no to specify the re-trigger numbers. Figure 4-12 illustrates an example.
Bus-mastering DMA Data Transfer PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize the maximum PCI bandwidth. The bus-mastering controller, which is built in the PLX IOP-480 PCI controller, controls the PCI bus when it becomes the master of the bus. Bus mastering reduces the size of the on-board memory and reduces the CPU loading because data is directly transferred to the computer’s memory without host CPU intervention.
list for the input DMA channel or the output DMA channel. Figure 4-13 shows a linked list that is constructed by three DMA descriptors. Each descriptor contains a PCI address, a local address, a transfer size, and the pointer to the next descriptor. You can allocate many small size memory blocks and chain their associative DMA descriptors altogether by their application programs.
4.2 D/A Conversion There are two 12-bit D/A output channels available in the DAQ-/ DAQe-/PXI-2016/2010/2006/2005 card. When using D/A converters, you should assign and control the D/A converter reference sources for the D/A operation mode and D/A channels. You could also set the output polarity to unipolar or bipolar. The reference selection control lets you utilize in full the multiplying characteristics of the D/A converters.
Digital Code Analog Output 111111111111 Vref * (4095/4096) 100000000000 Vref * (2048/4096) 000000000001 Vref * (1/4096) 000000000000 0V Table 4-6: Unipolar Output Code Table The D/A conversion is initiated by a trigger source. You must decide how to trigger the D/A conversion. The data output will start when a trigger condition is met. Before the start of D/A conversion, D/A data is transferred from the computer’s main memory to a buffering Data FIFO.
Timed Waveform Generation This mode can provide your applications with a precise D/A output with a fixed update rate. It can be used to generate an infinite or finite waveform. You can accurately program the update period of the D/A converters. The D/A output timing is provided through a combination of counters in the FPGA on board. There are a total of five counters to be specified.
Figure 4-14: Typical D/A Timing of Waveform Generation NOTE 50 The maximum D/A update rate is 1 MHz. Therefore, the minimum setting of the UI_counter is 40 while using an internal TIMEBASE (40 MHz).
Trigger Modes Post-Trigger Generation Use post-trigger when you want to perform DA waveform right after a trigger event occurs. In this trigger mode DLY1_Counter is ignored and not be specified. Figure 4-15 shows a single waveform generated right after a trigger signal is detected assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, and 4V. The trigger signal could come from a software command, an analog trigger or a digital trigger. Refer to section 4.5 for detailed information.
DLY1_Counter * UI_counter/TIMEBASE), so the delay time can reach a wider range. Figure 4-16: Delay Trigger Waveform Generation Post-Trigger or Delay-Trigger with Re-trigger Use post-trigger or delay-trigger with re-trigger function when you want to generate waveform after more than one trigger events. The re-trigger function can be enabled or disabled by software setting. In Figure 4-17, each trigger signal will initiate a waveform generation assuming the data in the data buffer are 2V, 4V, 2V, and 0V.
Iterative Waveform Generation Set IC_Counter in order to generate iterative waveforms from the data of a single waveform. The counter stores the iteration number and the iterations may be finite (Figure 4-18) or infinite (Figure 4-19). Both figures assume that the data in the data buffer are 2V, 4V, 2V, and 0V. A data FIFO on board is used to buffer the digital data for DA output.
Figure 4-19: Infinite Iterative Waveform Generation with Post-trigger and DLY2_Counter = 0 NOTES When running infinite iterative waveform generation, setting IC_Counter is ineffective to the waveform generation. It only makes a difference when setting Stop mode III. Refer to Figure 4-22. Setting finite and infinite iterative waveform generation is not discussed in this manual. Refer to software documentation for related information.
Stop Modes of Scan Update You can call software stop function to stop waveform generation when it is still in progress. Three stop modes are provided for timed waveform generation meant to stop the waveform generation. You can apply these three modes to stop waveform generation no matter infinite or finite waveform generation mode is selected. Figure 4-20 illustrates an example for stop mode I, assuming the data in the data buffer are 2V, 4V, 2V, and 0V.
Figure 4-21: Stop Mode II Figure 4-22: Stop Mode III 56 Operation Theory
4.3 Digital I/O The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card contains 24 lines of general-purpose digital I/O (GPIO) which is provided through the 82C55A chip. The 24-line GPIO are separated into three ports: Port A, Port B and Port C. High nibble (bit[7…4]), and low nibble (bit[3…0]) of each port can be programmed individually to be either inputs or outputs. Upon system startup or reset, all the GPIO pins are reset to high impedance inputs.
GPTC_UPDOWN input controls whether the counter counts up or down. The GPTC_GATE input is a control signal which acts as a counter enable or a counter trigger signal under different applications. The output of timer/counter is GPTC_OUT. After power-up, GPTC_OUT is pulled high by a pulled-up resister about 10K ohms. Then GPTC_OUT goes low after the DAQ-/DAQe-/PXI2016/2010/2006/2005 card is initialized. All the polarities of input/output signals can be programmed by software.
Mode 2: Single Period Measurement In this mode, the counter counts the period of the signal on GPTC_GATE in terms of GPTC_CLK. Initial count can be loaded from software. After the software-start, the counter counts the number of active edges on GPTC_CLK between two active edges of GPTC_GATE. After the completion of the period interval on GPTC_GATE, GPTC_OUT outputs high and then current count value can be read-back by software. Figure 4-24 illustrates the operation where initial count = 0, count-up mode.
Figure 4-25: Mode 3 Operation Mode 4: Single Gated Pulse Generation This mode generates a single pulse with programmable delay and programmable pulse-width following the software-start. The two programmable parameters could be specified in terms of periods of the GPTC_CLK input by software. GPTC_GATE is used to enable/disable counting. When GPTC_GATE is inactive, the counter halts the current count value.
Mode 5: Single Triggered Pulse Generation This function generates a single pulse with programmable delay and pro-grammable pulse-width following an active GPTC_GATE edge. You could specify these programmable parameters in terms of periods of the GPTC_CLK input. Once the first GPTC_GATE edge triggers the single pulse, GPTC_GATE takes no effect until the software-start is re-executed. Figure 4-27 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four.
Mode 7: Single Triggered Continuous Pulse Generation This mode is similar to Mode 5 except that the counter generates continuous periodic pulses with programmable pulse interval and pulse-width following the first active edge of GPTC_GATE. Once the first GPTC_GATE edge triggers the counter, GPTC_GATE takes no effect until the software-start is re-executed. Figure 4-29 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three.
4.5 Trigger Sources ADLINK provides flexible trigger selections in the DAQ-/DAQe-/ PXI-2010/2000 Series products. In addition to the internal software trigger, the DAQ-/DAQe-/PXI-2016/2010/2006/2005 card also supports external analog, digital triggers, and SSI triggers. You can configure the trigger source by software for A/D and D/A processes individually. Note that the A/D and the D/A conversion share the same analog trigger. Software-Trigger This trigger mode does not need any external trigger source.
Figure 4-31: Analog Trigger Block Diagram Trigger level digital setting Trigger voltage 0xFF 9.92V 0xFE 9.84V --- --- 0x81 0.08V 0x80 0 0x7F -0.08V --- --- 0x01 -9.92V Table 4-7: Analog Trigger SRC1 (EXTATRIG) Ideal Transfer Characteristic The trigger signal is generated when the analog trigger condition is satisfied. There are five analog trigger conditions in the DAQ-/ DAQe-/PXI-2016/2010/2006/2005 card.
Below-Low Analog Trigger Condition Figure 4-32 shows the below-low analog trigger condition, the trigger signal is generated when the input analog signal is less than the Low_Threshold voltage, and the High_Threshold setting is not used in this trigger condition.
NOTE The High_Threshold setting should be always higher than the Low_Threshold voltage setting. Figure 4-34: Inside-Region Analog Trigger Condition High-Hysteresis analog trigger condition Figure 4-35 shows the high-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is greater than the High_Threshold voltage, and the Low_Threshold voltage determines the hysteresis duration.
Low-Hysteresis analog trigger condition Figure 4-36 shows the low-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is less than the Low_Threshold voltage, and the High_Threshold voltage determines the hysteresis duration. Note the High_Threshold setting should be always higher then the Low_Threshold voltage setting.
4.6 User-controllable Timing Signals In order to meet the requirements for user-specific timing and requirements for synchronizing multiple cards, the DAQ-/DAQe-/ PXI-2016/2010/2006/2005 card provides flexible user-controllable timing signals to connect to external circuitry or additional cards. The whole DAQ timing of the DAQ-/DAQe-/PXI-2016/2010/2006/ 2005 card is composed of a bunch of counters and trigger signals in the FPGA.
Timing signal category Corresponding functionality SSI/PXI signals Multiple cards synchronization AFI signals Control DAQ-2000 by external timing signals AI_Trig_Out, AO_Trig_Out Control external circuitry or boards Table 4-8: User-controllable Timing Signals and Functionalities DAQ timing signals The user-controllable internal timing-signals contain (refer to section 4.1 for the internal timing signal definition): 1.
should be TTL-compatible and the minimum pulse width is 20 ns. 5. DA_TRIG, the trigger signal for the D/A operation, which could be derived from external digital trigger, analog trigger, internal software trigger, and SSI_AD_TRIG. Refer to section 4.5 for detailed description. 6. DAWR, the update signal to initiate a single D/A conversion, which could be derived from internal counter, AFI[1] or SSI_DAWR. Note that this signal is edge-sensitive.
Category Multifunction input Timing signal AFI[0] (Dual functions) Functionality Constraints Replace the internal ADCONV 1. TTL-compatible Replace the internal SCAN_START 1. TTL-compatible 2. Minimum pulse width = 20ns 3. Rising–edge sensitive only 2. Minimum Pulse width > 2/ TIMEBASE 1. TTL-compatible AFI[1] Replace the internal DAWR 2. Minimum pulse width = 20ns 3.
ple the data according to external events. In this mode, the Trigger signal and trigger mode settings are not available. AFI[0] could also be used as SCAN_START signal for A/D operations. Refer to section 4.1 and section 4.6 for detailed descriptions of the SCAN_START signal. When using external signal (AFI[0]) to replace the internal SCAN_START signal, the pulse width of the AFI[0] must be greater than two time of the period of Timebase.
SSI timing signal Functionality SSI master: send the TIMEBASE out SSI_TIMEBASE SSI slave: accept the SSI_TIMEBASE to replace the internal TIMEBASE signal. Note: Affected on both A/D and D/A operations SSI master: send the internal AD_TRIG out SSI_AD_TRIG SSI slave: accept the SSI_AD_TRIG as the digital trigger signal. SSI master: send the ADCONV out SSI_ADCONV SSI slave: accept the SSI_ADCONV to replace the internal ADCONV signal.
The six internal timing signals could be routed to the SSI or the PXI trigger bus through software drivers. Refer to section 4.6 for detailed information on the six internal timing signals. Physically the signal routings are accomplished in the FPGA. Cards that are connected together through the SSI or the PXI trigger bus, will still achieve synchronization on the six timing signals. The mechanism of the SSI/PXI X We adopt master-slave configuration for SSI/PXI.
Note that when power-up or reset, the DAQ timing signals are reset to use the internal generated timing signals. AI_Trig_Out and AO_Trig_Out AI_Trig_Out (or AO_Trig_Out) is the signal output following one of the four trigger sources: software trigger, analog trigger, digital trigger, and SSI trigger selected by the user. That is, AI_Trig_Out follows the A/D trigger source, and AO_Trig_Out follows the D/A trigger source.
76 Operation Theory
5 Calibration This chapter introduces the calibration process to minimize AD measurement errors and DA output errors. 5.1 Loading Calibration Constants The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card is factory-calibrated before shipment. The associated calibration constants of the TrimDACs firmware to the onboard EEPROM. TrimDACs are devices containing multiple DACs within a single package. TrimDACs do not have memory capability.
5.2 Auto-calibration Through the DAQ-/DAQe-/PXI-2016/2010/2006/2005 card autocalibration feature, the calibration software measures and corrects almost all calibration errors without any external signal connections, reference voltage, or measurement devices. The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card comes with an onboard calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured in the production line through a digital potentiometer and compensated in the software.
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