Express-CVC User’s Manual Manual Revision: 2.
Revision History Revision Description Date By 2.00 Initial release 2013-08-30 JC 2.01 Remove Industrial Temp.
Preface Copyright 2013-14 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.
Table of Contents Revision History ............................................................................................................ 2 Preface............................................................................................................................ 3 1. Introduction ......................................................................................................... 7 2. Specifications........................................................................................
3.3.11. Miscellaneous..................................................................................................................................22 3.3.12. SMBus..............................................................................................................................................23 3.3.13. I2C Bus .............................................................................................................................................23 3.3.14.
.3.9. Serial Port Console Redirection .........................................................................................................59 6.3.10. PPM Configuration ..........................................................................................................................61 6.4. Chipset Setup ......................................................................................................................... 62 6.4.1. Host Bridge Configuration ..............................
1. Introduction The Express-CVCis a low power, low cost, COM Express Type 2, COM.0 R2.1 module in Compact form factor that is specially designed to facilitate speedy development of semi custom designs. The COM Express standard embodies the convergence of the latest technology standards based on serial differential signaling such as PCI Express, USB 2.0, SATA and LVDS implemented on a compact size Computer on Module.
2. Specifications 2.1. Core System ¾ CPU: Intel® Atom® Processor, 2-core with Integrated Graphics, FCBGA559 type • • • Dual-Core Intel® Atom™ Processor N2600 1.66Gz (1MB L2 cache, 3.5W) Dual-Core Intel® Atom™ Processor N2800 1.86Gz (1MB L2 cache, 6.5W) Dual-Core Intel® Atom™ Processor D2550 1.86Gz (1MB L2 cache, 10W) ¾ Cache: 1MB to 16MB LLC cache depending on CPU type ¾ Memory: Single SODIMM socket supporting non-ECC DDR3 at 1066 MHz on N2800 and D2550 (max. 4 GB), at 800 MHz on N2600 (max.
2.4. Audio ¾ Integrated: Intel® HD Audio integrated in NM10 ¾ Audio Codec: Realtek ALC888 or 886 on Express-BASE 2.5. Ethernet ¾ Controller: Intel® Ethernet Controller I210 ¾ Connection: PCIe x1 ¾ Interface: 10/100/1000 GbE connection 2.6. Multi I/O and Storage ¾ USB ports: 8 ports USB 1.1/2.0 ¾ SATA ports: 1 ports SATA 3 Gb/s (SATA0) optional 2 ports SATA 3 Gb/s (SATA0, SATA1) by removing PATA solution ¾ PATA port: single PATA port through Jmicron JM330 SATA to PATA Bridge 2.7.
2.10. TPM (Trusted Platform Module) ¾ Chipset: Atmel AT97SC3204T, LPC type (optional) ¾ Type: TPM 1.2 2.11. Fan Control ¾ Control Source: Temperature Sensor ¾ Location : 4-pin Mini connector on module: 5V for smart fan 2.12. Power Specifications ¾ Power Modes: AT and ATX mode (AT mode controlled by SEMA BC) ¾ Wide Voltage Input: ATX mode : 5~20V & 5Vsb +/- 5% or AT mode : 5 ~20V ¾ Power Management: ACPI 3.0 compliant, Smart Battery support.
2.15. Functional Diagram VGA LVDS 24-bit eDP/DP 800/1067 MHz 1~4 GB DDR3 N2600 N2800 D2550 CH7511 DMI DP SATA 3Gb/s (port 0) SATA 3Gb/s (port1) SATA JM330 3x PCIe x1 (port 0,1,2) PATA IDE PCIe x1 (port 3) i210 PCI Bus 8x USB 2.
2.16.
3. COM Express Pinouts and Signal Descriptions The following information is a summary of the most important information regarding pinout and signal description in the official PICMG COM.0 Rev 2.0 (soon 2.1) The pinout is noted here to emphazise issues that have not been followed in the past. The following might have small inacuaracies so in case of doubt the offical design guide of PICMG should be consulted. 3.1.
A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 Page 14 USB6USB6+ USB_6_7_OC# USB4USB4+ GND (FIXED) USB2USB2+ USB_2_3_OC# USB0USB0+ VCC_RTC EXCD0_PERST# EXCD0_CPPE# LPC_SERIRQ GND (FIXED) PCIE_TX5+ PCIE_TX5GPI0 PCIE_TX4+ PCIE_TX4GND PCIE_TX3+ PCIE_TX3GND (FIXED) PCIE_TX2+ PCIE_TX2GPI1 PCIE_TX1+ PCIE_TX1GND GPI2 PCIE_TX0+ PCIE_TX0GND (FIXED) LVDS_A0+ LVDS_A
A86 A87 A88 A89 A90 A91 A92 A93 A94 A95 A96 A97 A98 A99 A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 KBD_RST# KBD_A20GATE PCIE0_CK_REF+ PCIE0_CK_REFGND (FIXED) SPI_POWER SPI_MISO GPO0 SPI_CLK SPI_MOSI GND TYPE10# RSVD RSVD GND (FIXED) RSVD RSVD RSVD VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V GND (FIXED) Express-CVC B86 B87 B88 B89 B90 B91 B92 B93 B94 B95 B96 B97 B98 B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 VCC_5V_SBY VCC_5V_SBY BIOS_DIS1# VGA_RED GND (FIXED) VGA_GRN VGA_
3.2. Signal Description Terminology The following terms are used in the COM Express AB/CD Signal Descriptions below. Page 16 I Input to the Module O Output from the Module I/O Bi-directional input / output signal OD Open drain output I 3.3V Input 3.3V tolerant I 5V Input 5V tolerant O 3.3V Output 3.3V signal level O 5V Output 5V signal level I/O 3.3V Bi-directional signal 3.3V tolerant I/O 5V Bi-directional signal 5V tolerant I/O 3.3Vsb Input 3.
3.3. AB Signal Descriptions 3.3.1. Audio Signals Signal Pin Description I/O AC_RST# / HDA_RST# A30 Reset output to CODEC, active low. O 3.3VSB AC_SYNC / HDA_SYNC A29 Sample-synchronization signal to the CODEC(s). O 3.3V AC_BITCLK / HDA_BITCLK A32 Serial data clock generated by the external CODEC(s). I/O 3.3V AC _SDOUT / HDA_SDOUT A33 Serial TDM data output to the CODEC. O 3.3V AC _SDIN[2:0] HDA_SDIN[2:0] B28B30 Serial TDM data inputs from up to 3 CODECs. I/O 3.3VSB 3.3.2.
3.3.3.
3.3.5. Serial ATA Signal Pin Description I/O SATA0_TX+ SATA0_TX- A16 A17 Serial ATA channel 0, Transmit Output differential pair. O SATA AC coupled on Module SATA0_RX+ SATA0_RX- A19 A20 Serial ATA channel 0, Receive Input differential pair. I SATA AC coupled on Module SATA1_TX+ SATA1_TX- B16 B17 Serial ATA channel 1, Transmit Output differential pair. O SATA AC coupled on Module SATA1_RX+ SATA1_RX- B19 B20 Serial ATA channel 1, Receive Input differential pair.
3.3.6. PCI Express Signal Pin Description I/O PCIE_TX0+ PCIE_TX0- A68 A69 PCI Express channel 0, Transmit Output differential pair. O PCIE AC coupled on Module PCIE_RX0+ PCIE_RX0- B68 B69 PCI Express channel 0, Receive Input differential pair. I PCIE AC coupled off Module PCIE_TX1+ PCIE_TX1- A64 A65 PCI Express channel 1, Transmit Output differential pair. O PCIE AC coupled on Module PCIE_RX1+ PCIE_RX1- B64 B65 PCI Express channel 1, Receive Input differential pair.
3.3.8. LPC bus Signal Pin Description I/O LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V LPC_DRQ0# LPC_DRQ1# B8 B9 LPC serial DMA request I 3.3V LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V LPC_CLK B10 LPC clock output - 33MHz nominal O 3.3V 3.3.9. PU/PD Comment PU 8k2 3.3V USB Signal Pin Description I/O USB0+ USB0- A46 A45 USB differential data pairs for Port 0 I/O 3.
3.3.10. SPI (BIOS only) Signal Pin Description I/O PU/PD Comment SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V.
3.3.12. SMBus Signal Pin Description I/O PU/PD SMB_CK B13 System Management Bus bidirectional clock line. Power sourced through 5V standby rail and main power rails. I/O OD 3.3VSB PU 2k2 3.3VSB SMB_DAT# B14 System Management Bus bidirectional data line. Power sourced through 5V standby rail and main power rails. I/O OD 3.3VSB PU 2k2 3.3VSB SMB_ALERT# B15 System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system.
3.3.15. Power And System Management Signal Pin Description I/O PU/PD PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge. I 3.3VSB PU 10k 3.3VSB SYS_RESET# B49 Reset button input. Active low request for module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used. I 3.3VSB PU 10k 3.3VSB CB_RESET# B50 Reset output from module to Carrier Board.
3.3.16. Power and Ground Signal Pin Description I/O VCC_12V A104-A109 Primary power input: +12V nominal (5 ~ 19V). See section 7 “Electrical Specifications“ for allowable input range. All available VCC_12V pins on the connector(s) shall be used. P B104-B109 VCC_5V_SBY B84-B87 Standby power input: +5.0V nominal. See section 7 “Electrical P Specifications“ for allowable input range. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used.
3.4. CD Signal Descriptions 3.4.1. PATA IDE Signal Pin Description I/O IDE_D0 IDE_D1 IDE_D2 IDE_D3 IDE_D4 IDE_D5 IDE_D6 IDE_D7 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15 D7 C10 C8 C4 D6 D2 C3 C2 C6 C7 D3 D4 D5 C9 C12 C5 Bidirectional data to / from IDE device. I/O 3.3V IDE_A0 D13 Address lines to IDE device. O 3.3V IDE_A1 D14 Address lines to IDE device. O 3.3V IDE_A2 D15 Address lines to IDE device. O 3.3V IDE_IOW# D9 I/O write line to IDE device.
3.4.2. PCI Signal Pin PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 C24 PCI bus multiplexed address and data lines D22 C25 D23 C26 D24 C27 D25 C28 D27 C29 D28 C30 D29 C32 D30 D37 C39 D38 C40 D39 C42 D40 C43 D42 C45 D43 C46 D44 C47 D45 C48 I/O 3.
PCI_LOCK# C35 PCI Lock control line, active low. I/O 3.3V PU 8k2 3.3V PCI_SERR# D33 System Error: SERR# may be pulsed active by any PCI device that detects a system error condition. I/O 3.3V PU 8k2 3.3V PCI_PME# C15 PCI Power Management Event: PCI peripherals drive PME# to wake system from low-power states S1–S5. I 3.3VSB PCI_CLKRUN# D48 Bidirectional pin used to support PCI clock run protocol for mobile systems. I/O 3.3V PU 10k 3.
3.4.3.
Signal Pin Description I/O PEG_TX14PEG_TX15+ PEG_TX15- D99 D101 D102 PEG_LANE_RV# PEG_ENABLE# PU/PD D54 PCI Express Graphics lane reversal input strap. Pull low on the Carrier board to reverse lane order. I 1.05V D97 Strap to enable PCI Express x16 external graphics interface. Pull low to enable the x16 interface. I 3.3V Comment Not supported PU 10k 3.
3.4.4. Module Type Definition Pin Pin Name SDVO TYPE0# TYPE1# TYPE2# C54 C57 D57 The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are no-connects (NC). For Pinout Type 1, these pins are don’t care (X).
4. Non PICMG Connectors on the Module This connector is a low height flex-edge connector. The overall board real estate required is significantly smaller than the 60-pin XDP debug port connector. Compared to the 60-pin XDP debug port connector, the 26-pin XDP-SFF connector supports fewer DFX features. This is the connector recommended for OEM/ODM designs.
5. System Resources 5.1.
5.3.
Hex Range Device CFC-CFF PCI configuration data register F00 Smbus base address for SB. 500 GPIO Base Address for SB 400 PM (ACPI) Base Address for SB 460 Alias for ICH TCO base address. 0A00~0AFF Reserved for SIO functions base address (ex: PME /GPIO etc) 000-01F DMA controller 020-02D and 030-03F Interrupt controller 5.4.
APIC Mode IRQ# Typical Intterupt Resource Connected to Pin Available 0 Counter 0 N/A No 1 Keyboard controller N/A No 2 Cascade interrupt from slave PIC N/A No 3 Serial Port 2 (COM2) / PCI IRQ3 via SERIRQ / PIRQ Note 4 Serial Port 1 (COM1) / PCI IRQ4 via SERIRQ / PIRQ Note 5 Generic Generic No 6 Floppy Drive Controller IRQ6 via SERIRQ / PIRQ Note 7 Smbus Controller SMBus Controller / PIRQ Note 8 Real-time clock N/A No 9 Generic IRQ9 via SERIRQ / PIRQ Note 10 Gener
5.5. PCI Configuration Space Map Bus Number Device Number Function Number Routing Description 00h 00h 00h N/A Intel Host Processor Bridge 00h 02h 00h Internal Intel P.E.G.
5.6. PCI Interrupt Routing Map INT Line P.E.G Root Port INT0 INTA:16 INT1 SATA Controller SMBUS Controller UHCI 0 UHCI 1 UHCI 2 UHCI 3 INTH:23 INTD:19 INTD:19 EHCI Controller #1 HDA Controller INTH:23 INTG:22 INTD:19 INT2 INTC:18 INT3 INTA:16 INT Line PCIE Port 0 PCIE Port 1 PCIE Port 2 GbE Controller INT0 INTA:16 INTB:17 INTD:19 INTA:16 INT1 INTB:17 INTC:18 INTA:16 INTB:17 INT2 INTC:18 INTD:19 INTB:17 INTC:18 INT3 INTD:19 INTA:16 INTC:18 INTD:19 5.7.
6. BIOS Setup The following chapter describes basic navigation for the AMIBIOS®EFI BIOS setup utility. 6.1. Starting the BIOS To enter the setup screen, follow these steps: 1. Power on the motherboard 2. Press the < Delete > key on your keyboard when you see the following text prompt: < Press DEL to run Setup > 3. After you press the < Delete > key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu, such as Chipset and Power menus.
6.1.1. Setup Menu The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user’s guide. The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. “Grayed” options cannot be configured, “Blue” options can be. The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white.
6.1.2. Navigation The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process. These keys include < F1 >, < F10 >, < Enter >, < ESC >, < Arrow > keys, and so on. There is a hot key legend located in the right frame on most setup screens. →← ↑↓ +Tab Express-CVC Left/Right. The Left and Right < Arrow > keys allow you to select a setup screen.
Hot Key Description Enter The < Enter > key allows you to display or change the setup option listed for a particular setup item. The < Enter > key can also allow you to display the setup sub-screens. F1 The < F1 > key allows you to display the General Help screen. Press the < F1 > key to open the General Help screen. F2 The < F2 > key on your keyboard is the previous values key. It is not displayed on the key legend by default.
F4 ESC The < F4 > key allows you to save any changes you have made and exit Setup. Press the < F4 > key to save your changes. The following screen will appear: Press the < Enter > key to save the configuration and exit. You can also use the < Arrow > key to select Cancel and then press the < Enter > key to abort this function and return to the previous screen. The < Esc > key allows you to discard any changes you have made and exit the Setup.
6.2.
6.2.1. System Management Power-Up Mode Turn On:The machine starts automatically when the power supply is turned on. Remain Off: To start the machine the power button has to be pressed. Last State:The machine will return to the last state on power up. ECO Mode Reduces the power consumption of the system.
Power-Up Watchdog The Power-Up Watchdog resets the system after a certain amount of time after power-up. System & Board Info The Main BIOS setup screen reports board information. ¾ Project Version Displays the current BIOS version. ¾ Build Data Displays the BIOS build data. System Date/System Time Use this option to change the system time and date. Highlight System Time or System Date using the < Arrow > keys. Enter new values using the keyboard.
6.3. Advanced Setup 6.3.1. PCI Subsystem Settings PCI Latency Timer Value to be programmed into the PCI Latency Timer Register. VGA Palette Snoop Enables or Disables VGA Palette Registers Snooping. PERR# Generation Enables or Disables PCI Device to Generate PERR#. SERR# Generation Enables or Disables PCI Device to Generate SERR#.
6.3.2. ACPI Settings Enable APIC Auto Configuration BIOS ACPI Auto Configuration. Set this value to Enabled/Disabled. Enable Hibernation Controls system's ability to hibernate (OS/S4 Sleep State). Set this value to Enabled/Disabled. ACPI Sleep State Select the highest ACPI sleep state the system will enter, when the SUSPEND button is pressed. Set this value to Suspend Disable, S1, S3, Both S1 and S3.
6.3.3. Trusted Computing Security Device Support Enables or Disables BIOS support for security device. OS will not show Security Device.TCG EFI protocol and INT1A interface will not be available. 6.3.4. CPU Configuration Hyper-threading Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for HyperThreading Technology). When disabled, only one thread per enabled core is enabled.
Execute Disable Bit XD can prevent certain classes of malicious buffer overflow attacks when combined with a supporting OS (Windows Server 2003 SP1, Windows XP SP2, SuSE Linux 9.2, Red Hat Enterprise 3 Update 3.) Limit CPUID Maximum When the computer boots, the operating system executes its CPUID instruction to identify the processor and its capabilities. Before it can do so, it must first query the processor to find out the highest input value the CPUID recognizes.
CPU Thermal Configuration DTS SMM Enabled: ACPI thermal management uses DTS SMM mechanism to obtain CPU temperature values. CPU Temperature Display current CPU temperature.
Platform Thermal Configuration Critical Trip Point This value controls the temperature of the ACPI Critical Trip Point - the point at which the OS will shut the system off. NOTE: 100°C is the Plan of Record (POR) for all Intel mobile processors. Active Trip Point Lo Fan Speed This value controls the temperature of the ACPI Active Trip Point - the point at which the OS will turn the processor fan to low.
6.3.6. IDE Configuration SATA Controller(s) Enables or disables SATA Controller. SATA-to-PATA controller Enable if system uses PATA drive; Disable will reduce hard drive detection time when no PATA drive. Note: To use two SATA ports (SATA0/1), this setting must be enabled Configure SATA as Select a configuration IDE/AHCI for SATA Controller.
Configure SATA as “AHCI” Port0/1 Speed Limit Select Port0/1 AHCI Speed Limit. SATA Port 0/1 Enable or Disable SATA Port 0/1. SATA Port 0/1 Hot Plug Designates this port 0/1 as hot pluggable.
6.3.7. USB Configuration Legacy USB Support Enables Legacy USB support. AUTO option, disables legacy support if no USB devices are connected. DISABLE option will keep USB devices available only for EFI applications. Set this value to Enable/Disable/Auto. EHCI Hand-off This is a workaround for OSes without EHCI hand-off support. The EHCI ownership change should be claimed by EHCI driver. Set this value to Enabled/Disabled. USB transfer time-out The time-out value for Control, Bulk, and Interrupt transfers.
6.3.8. W8362DHG Super IO Configuration Floppy Disk Controller Configuration Change Settings This option specifies the base I/O port address and interrupt request address of serial port 0,1 (COMA,B). Configuration options: Auto, 3F0.
Device Mode Change mode of Floppy Disk Controller. Select 'Read Write' for normal operation. Select 'Write Protect' mode for read only operation. Serial Port 0/1 Configuration Set Parameters of Serial Port 0/1 (COMA/B) Change Settings This option specifies the base I/O port address and interrupt request address of serial port 0,1 (COMA,B). Configuration options: Auto, 3F8, 3E8, 2F8, 2E8.
Parallel Port Set Parameters of Parallel Port. Set this value to Enabled/Disabled. Change Settings This option specifies the base I/O port address and interrupt request address of parallel port. Configuration options: Auto, 378, 278, 3BC. Device Mode Change the printer port mode.
6.3.9. Serial Port Console Redirection Console Redirection Console Redirection Enable or Disable. Console Redirection Setttings The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.
Terminal Type VT100+ is the preferred terminal type for out-of-band management. Configuration options: VT100, VT100+, VT-UTF8 , ANSI. Bits per second Select the bits per second you want the serial port to use for console redirection. The options are 115200, 57600, 38400, 19200, 9600. Data Bits Select the data bits you want the serial port to use for console redirection. Set this value to 7 / 8. Parity Set this option to select Parity for console redirection.
6.3.10. PPM Configuration EIST Allows the clock speed of the processor to be dynamically changed. Set this value to Enabled/Disabled. C-States Enable or Disable C2 and above. Set this value to Enabled/Disabled. Enhanced C state Enable/Disable Enhanced CPU C state CPU Hard C4E Enable/Disable CPU Hard C4E function CPU C6 state Enable/Disable CPU C6 state C4 Exit Timing This option controls a programmable time for the CPU voltage to stabilize when exiting from a C4 state.
6.4. Chipset Setup 6.4.1.
Intel IGD Configuration IGFX-Boot Type Select the boot display device. Set this value to CRT, LFP, CRT+LFP. LCD Panel Type When LVDS is selected from Boot Display Device, this option allows you to select resolution settings as below: Backlight Control Choose BMC/Chipset to control backligh.
LVDS Backlight Control LVDS Backlight control. Active LFP Select the boot display device.
6.4.2. South Bridge TPT Device Enable/Disable Intel IO Controller Hub Devices. Azalia Controller The audio controller. Set this value to Disabled, HD Auto.
Azalia Vci Enable Azalia supports 1 extended VC, which, when enabled, overrides ICH VCp settings Select USB Mode Select USB mode to control USB ports. UHCI #1-4 Controller The UHCI controller. Set this value to Enabled/Disabled. USB2.0 Controller The EHCI controller. Set this value to Enabled/Disabled. SMBus Controller The SMBus controller. Set this value to Enabled/Disabled. LAN Controller Enable/Disable OnChip NIC Controller. SMBus Controller Enable/Disable OnChip SMBus Controller.
SLP_S4 Assertion Width Select a minimum assertion width of the SLP_S4# signal. LAN Controller Enable or disable the Ethernet Controller. PHY of LAN Enable or disable the PHY of LAN.
6.5. Boot Setup Setup Prompt Timeout Number of seconds to wait for setup activation key. 65535 (0xFFFF) means indefinite waiting. Bootup Numlock State Select the keyboard NumLock state. Quiet Boot Enable or disables Quiet Boot option. CSM parameters Launch PXE OpROM policy This Controls the execution of UEFI and Legacy PXE OpROM. Launch storage OpROM This Controls the execution of UEFI and Legacy PXE OpROM.
6.6.
6.7. Save & Exit Menu Save Changes and Exit Exit system setup after saving the changes. Discard Changes and Exit Exit system setup without saving any changes. Save changes and Reset Reset the system after saving the changes. Discard changes and Reset Reset system setup without saving any changes. Save changes Save Changes done so far to any of the setup options. Discard Changes Discard Changes done so far to any of the setup options. Restore Defaults Restore/Load Default values for all the setup options.
Safety Instructions Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use. • Please read these safety instructions carefully. • Please keep this User‘s Manual for later reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment.
Getting Service ADLINK Technology, Inc. Address: Tel: Fax: Email: 9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan +886-2-8226-5877 +886-2-8226-5717 service@adlinktech.com Ampro ADLINK Technology, Inc. Address: Tel: Toll Free: Fax: Email: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA +1-408-360-0200 +1-800-966-5200 (USA only) +1-408-360-0222 info@adlinktech.com ADLINK Technology (China) Co., Ltd. Address: Tel: Fax: Email: 300 Fang Chun Rd.
ADLINK Technology, Inc. (French Liaison Office) Address: Tel: Fax: Email: 15 rue Emile Baudot, 91300 Massy CEDEX, France +33 (0) 1 60 12 35 66 +33 (0) 1 60 12 35 66 france@adlinktech.com ADLINK Technology Japan Corporation Address: Tel: Fax: Email: KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho, Chiyoda-ku, Tokyo 101-0045, Japan +81-3-4455-3722 +81-3-5209-6013 japan@adlinktech.com ADLINK Technology, Inc.
