Express-HL2 User’s Manual Manual Revision: 1.
Revision History Revision Description Date By 1.00 Initial release 2014-08-29 JC 1.
Preface Copyright 2014 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.
Table of Contents Revision History ............................................................................................................ 2 Preface............................................................................................................................ 3 1 Introduction ............................................................................................................ 6 2 Specifications ......................................................................................
Smart Embedded Management Agent (SEMA) ................................................ 37 5.1 6 Board Specific SEMA Functions ................................................................................................. 38 System Resources ................................................................................................. 40 6.1 System Memory Map................................................................................................................. 40 6.
1 Introduction The Express-HL2 is a COM Express® COM.0 R2.1 Type 2 module supporting the 64-bit 4th Generation Intel® Core™ i7/i5/3 processor with mobile Intel® QM87 Chipset or 4th Generation Intel® Celeron® processor with mobile Intel® HM86 Chipset. The Express-HL2 is specifically designed for customers who need high-level processing and graphics performance in a long product life solution.
2 Specifications 2.1 Core System ¾ CPU: 4th Generation Intel® Core™ and Intel® Celeron® Processors - 22nm (formerly “Haswell”) • • • • • • • • Intel® Core™ i7-4860EQ 1.8 GHz (3.2 GHz Turbo), 47W (4C/GT3) Intel® Core™ i7-4700EQ 2.4/1.7 GHz (3.4 GHz Turbo), 47/37W (4C/GT2) Intel® Core™ i5-4400E 2.7 GHz (3.3 GHz Turbo), 37W (2C/GT2) Intel® Core™ i5-4402E 1.6 GHz (2.7 GHz Turbo), 25W (2C/GT2) Intel® Core™ i3-4100E 2.4 GHz (no Turbo) 3MB, 37W (2C/GT2) Intel® Core™ i5-4102E 1.
2.5 LAN ¾ Integrated: LAN MAC integrated in PCH QM87/HM86 ¾ Intel PHY: Intel® Ethernet Controller i217LM ¾ Interface: 10/100/1000 GbE connection 2.6 Multi I/O and Storage ¾ Integrated in Intel® QM87/HM86 Express Chipset ¾ USB ports: 8 ports USB 2.
2.10 Power Specifications ¾ Power Modes: ¾ Standard Voltage Input: ATX = 12V±5% / 5Vsb ±5% or AT = 12V ±5% ¾ Wide Voltage Input: ¾ Power Management: ACPI 4.0 compliant, Smart Battery support ¾ Power States: supports C1-C6, S0, S1, S4, S3, S5, S5 ECO mode (Wake on USB S3/S4, WOL S3/S4/S5) 2.11 AT and ATX mode (AT mode start controlled by SEMA) ATX = 8.5~20 V / 5Vsb ±5% or AT = 8.
2.
2.16 Mechanical Drawing connector on bottom side All tolerances ± 0.05 mm Other tolerances ± 0.
3 Pinouts and Signal Descriptions 3.1 AB / CD Pin Definitions The Express-HL2 is a Type 2 module supporting PCI and PATA on the CD connector All pins in the COM Express specification are described, including those not supported on the Express-HL2. Those not supported on the Express-HL2 module are crossed out Row A Row B Row C Row D Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 USB4USB4+ GND (FIXED) USB2USB2+ USB_2_3_OC# USB0USB0+ VCC_RTC EXCD0_PERST# EXCD0_CPPE# LPC_SERIRQ GND (FIXED) PCIE_TX5+ PCIE_TX5GPI0 PCIE_TX4+ PCIE_TX4GND PCIE_TX3+ PCIE_TX3GND (FIXED) PCIE_TX2+ PCIE_TX2GPI1 PCIE_TX1+ PCIE_TX1GND GPI2 PCIE_TX0+ PCIE_TX0GND (FIXED) LVDS_A0+ LVDS_A0LVDS_A1+ LVDS_A1LVDS_A2+ LVDS_
A89 A90 A91 A92 A93 A94 A95 A96 A97 A98 A99 A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 PCIE0_CK_REFGND (FIXED) SPI_POWER SPI_MISO GPO0 SPI_CLK SPI_MOSI GND TYPE10# RSVD RSVD GND (FIXED) RSVD RSVD RSVD VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V GND (FIXED) B89 B90 B91 B92 B93 B94 B95 B96 B97 B98 B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 VGA_RED GND (FIXED) VGA_GRN VGA_BLU VGA_HSYNC VGA_VSYNC VGA_I2C_CK VGA_I2C_DAT SPI_CS# RSVD RSVD GND (FIXED) RSVD RSVD RSVD VCC_12V VCC_1
3.2 Signal Description Terminology The following terms are used in the COM Express AB/CD Signal Descriptions below. I Input to the Module O Output from the Module I/O Bi-directional input / output signal OD Open drain output I 3.3V Input 3.3V tolerant I 5V Input 5V tolerant O 3.3V Output 3.3V signal level O 5V Output 5V signal level I/O 3.3V Bi-directional signal 3.3V tolerant I/O 5V Bi-directional signal 5V tolerant I/O 3.3Vsb Input 3.
3.3 AB Signal Descriptions 3.3.1 Audio Signals Signal Pin # Description I/O AC_RST# / HDA_RST# A30 Reset output to codec, active low. O 3.3VSB AC_SYNC / HDA_SYNC A29 Sample-synchronization signal to the codec(s). O 3.3V AC_BITCLK / HDA_BITCLK A32 Serial data clock generated by the external codec(s). I/O 3.3V AC _SDOUT / HDA_SDOUT A33 Serial TDM data output to the codec. O 3.3V AC _SDIN[2:0] HDA_SDIN[2:0] B28 B30 Serial TDM data inputs from up to 3 codecs. I/O 3.3V 3.3.
3.3.
3.3.5 Serial ATA Signal Pin # Description I/O PU/PD Comment SATA0_TX+ SATA0_TX- A16 A17 Serial ATA channel 0, Transmit Output differential pair. O SATA AC coupled on Module SATA0_RX+ SATA0_RX- A19 A20 Serial ATA channel 0, Receive Input differential pair. I SATA AC coupled on Module SATA1_TX+* SATA1_TX-* B16 B17 Serial ATA channel 1, Transmit Output differential pair. O SATA AC coupled on Module SATA1_RX+* SATA1_RX-* B19 B20 Serial ATA channel 1, Receive Input differential pair.
3.3.6 PCI Express Signal Pin # Description I/O PCIE_TX0+ PCIE_TX0- A68 A69 PCI Express channel 0, Transmit Output differential pair. O PCIE AC coupled on Module PCIE_RX0+ PCIE_RX0- B68 B69 PCI Express channel 0, Receive Input differential pair. I PCIE AC coupled off Module PCIE_TX1+ PCIE_TX1- A64 A65 PCI Express channel 1, Transmit Output differential pair. O PCIE AC coupled on Module PCIE_RX1+ PCIE_RX1- B64 B65 PCI Express channel 1, Receive Input differential pair.
3.3.9 USB Signal Pin # Description I/O USB0+ USB0- A46 A45 USB differential data pairs for Port 0 I/O 3.3VSB USB 1.1/ 2.0 compliant USB1+ USB1- B46 B45 USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant USB2+ USB2- A43 A42 USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant USB3+ USB3- B43 B42 USB differential data pairs for Port 2 I/O 3.3VSB USB 1.1/ 2.0 compliant USB4+ USB4- A40 A39 USB differential data pairs for Port 3 I/O 3.
3.3.
3.3.11 SPI (BIOS only) Signal Pin # Description I/O SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V. The Module shall provide a minimum of 100mA on SPI_POWER.
3.3.14 I2C Bus Signal Pin # Description I/O PU/PD I2C_CK B33 General purpose I²C port clock output/input I/O OD 3.3VSB PU 2k2 3.3VSB I2C_DAT B34 General purpose I²C port data I/O line I/O OD 3.3VSB PU 2k2 3.3VSB 3.3.15 Comment General Purpose I/O (GPIO) Signal Pin # Description I/O PU/PD Comment GPO[0] A93 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET output low GPO[1] B54 General purpose output pins. O 3.3V PU 10K 3.
3.3.17 Power and System Management Signal Pin # Description I/O PU/PD PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge. I 3.3VSB PU 10k 3.3VSB SYS_RESET# B49 Reset button input. Active low request for module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used. I 3.3VSB PU 10k 3.
3.4 CD Signal Descriptions 3.4.1 PATA IDE Signal Pin # Description I/O IDE_D0 IDE_D1 IDE_D2 IDE_D3 IDE_D4 IDE_D5 IDE_D6 IDE_D7 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15 D7 C10 C8 C4 D6 D2 C3 C2 C6 C7 D3 D4 D5 C9 C12 C5 Bidirectional data to / from IDE device. I/O 3.3V IDE_A0 D13 Address lines to IDE device. O 3.3V IDE_A1 D14 Address lines to IDE device. O 3.3V IDE_A2 D15 Address lines to IDE device. O 3.3V IDE_IOW# D9 I/O write line to IDE device.
Signal Pin # PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 D29 C32 D30 D37 C39 D38 C40 D39 C42 D40 C43 D42 C45 D43 C46 D44 C47 D45 C48 Description I/O PCI_C/BE0# PCI_C/BE1# PCI_C/BE2# PCI_C/BE3# D26 C33 C38 C44 PCI bus byte enable lines, active low I/O 3.3V PCI_DEVSEL# C36 PCI bus Device Select, active low. I/O 3.3V PU 8k2 3.
Signal Pin # PCI_IRQB# PCI_IRQC# PCI_IRQD# C50 D46 D47 PCI_CLK D50 3.4.3 Description I/O PU/PD Comment 3.3V PCI 33MHz clock output O 3.3V Module Type Definition Signal Pin # TYPE0# TYPE1# TYPE2# C54 C57 D57 Description I/O The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are noconnects (NC). For Pinout Type 1, these pins are don’t care (X).
4 Connector Pinouts on Module This chapter describes connectors and pinouts, LEDs and switches that are used on the module but are not included in the PICMG standard specification Connector and LED Locations LED1 LED2 LED3 ¾ Page 28 Express-HL2
4.
40-pin Debug Connector Pin Definition on the COM Express Module ¾ Pin Interface Signal Remark Pin Interface Signal 1 SPI Program interface VCC_SPI_IN SPI Power Input from flash tool to module.
4.2 Status LEDs To facilitate easier maintenance, status LEDs are mounted on the board. ¾ LED Descriptions Name Color Connection Function LED1 Blue BMC output Power Sequence Status Code (BMC) Power Changes, RESET (see 5.1.
4.3 XDP Debug header The debug port is a connection into a target-system environment that provides access to JTAG, run control, system control, and observation resources. The XDP target system connector is a Samtec™ 60-pin BSH-030-01 series connector.
4.4 Fan Connector ¾ Connector Type: JVE 24W1125A-04M00 ¾ Pin Assignment Name Signal Description 1 BMC_FAN_OUT FAN_PWMOUT 2 BMC_FAN_PWM_IN FAN_TACHIN 3 GND Ground 4 P5V_S 5V 4.5 BIOS Setup Defaults Reset Button To perform a hardware reset of BIOS default settings, perform the following steps: 1. Shut down the system. 2. Press the BIOS Setup Defaults RESET Button continuously and boot up the system. You can release the button when the BIOS prompt screen appears 3.
4.6 Express-HL2 Switch Settings 4.6.
4.6.2 SW1: PCI Express Configuration Switch Switch SW1 allows you to configure the PCI Express x16 lanes from the CPU as 1 PCIe x16, 2 PCIe x8, or 1 PCIe x8 + 2 PCIe x4. Mode 4.6.3 Pin 1 Pin 2 1x PCIe x16 (default) Off Off 2x PCIe x8 On Off 1x PCIe x8 + 2x PCIe x4 On On Reserved Off On SW4: LVDS Panel Configuration Switch Switch SW4 allows you to set the LVDS panel mode to 18-bit or 24-bit. Mode 4.6.
4.7 PCIe x16-to-two-x8 Adapter Card The Express-HL can be used with the PCIe x16-to-two-x8 Adapter Card on the Express-BASE6 Reference Carrier to support bifurbication of the CPU's PEG interface (PCIe x16). The card reroutes the PCIe x16 to two x8 and allows testing of two independent PCIe add-on cards with x8/x4/x2/x1 width. To use the card, set SW1 to "2 x8 PCI Express" as above. PCIex16-to-two-x8 Adapter Card (Model: P16TO28, Part No.
5 Smart Embedded Management Agent (SEMA) The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality. The microcontroller communicates via the System Management Bus with the CPU/chipset. The following functions are implemented: • Total operating hours counter. Counts the number of hours the module has been run in minutes. • On-time minutes counter. Counts the seconds since last system start.
5.1 Board Specific SEMA Functions 5.1.1 Voltages The BMC of the Express-HL2 implements a voltage monitor and samples several onboard voltages. The voltages can be read by calling the SEMA function “Get Voltages”. The function returns a 16-bit value divided into high-byte (MSB) and low-byte (LSB). 5.1.2 ADC Channel Voltage Name Voltage Formula [V] 0 --- --- 1 +V3.3S (MSB<<8 + LSB) x 1.100 x 3.3 / 1024 2 +V1.05S (MSB<<8 + LSB) x 3.3 / 1024 3 +V3.3A (MSB<<8 + LSB) x 1.100 x 3.
5.1.4 Exception Codes In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore, a “Clear Exception Code” command is not needed or supported.
6 System Resources 6.1 System Memory Map Address Range (decimal) Address Range (hex) Size Description (4GB-2MB) FFE00000 – FFFFFFFF 2 MB High BIOS Area (4GB-18MB) – (4GB-17MB-1) FEE00000 – FEEFFFFF 1 MB MSI Interrupts (4GB-20MB) – (4GB-19MB-1) FEC00000 – FECFFFFF 1 MB APIC Configuration Space 15MB – 16MB F00000 – FFFFFF 1 MB ISA Hole 1MB -15MB 100000 - EFFFFF 14MB Main Memory 0K –1MB 00000 – FFFFFF 1MB DOS Compatibility Memory 6.
6.
I/O Map (cont'd) Hex Range Device 3BC-3BE Reserved for parallel port 3C0-3DF VGA registers 3E0-3EF Available 3F0-3F7 Floppy Disk Controller 3F8-3FF Serial port 1 4D0 Master PIC Edge/Level Trigger register 4D1 Slave PIC Edge/Level Trigger register CF8-CFB PCI configuration address register (32 bit I/O only) CF9 Reset Control register (8 bit I/O) CFC-CFF PCI configuration data register 580 Smbus base address for SB.
6.
APIC Mode (cont'd) IRQ# Typical Intterupt Resource Connected to Pin Available 16 N/A Intel HDA, PCIE Port 0/1/2/3/4/5/6, EHCI Conterller #2 ,P.E.G Root Port, I.G.D Note (1) 17 N/A PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port, Note (1) 18 N/A PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port, SMBus Controller, EHCI Controller #2,PCI Port 0 Note (1) 19 N/A PCIE Port 0/1/2/3/4/5/6, P.E.
6.5 PCI Configuration Space Map Bus Number Device Number Function Number Routing Description 00h 00h 00h N/A Intel host Bridge 00h 02h 00h Internal Intel I.G.
6.6 PCI Interrupt Routing Map INT Line P.E.
7 BIOS Setup 7.1 Menu Structure This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.
7.2 Main The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below the screen shot of this menu for details of the submenus and settings. 7.2.1 System Information Feature Options Description BIOS Version Info only ADLINK BIOS version. Build Date and Time Info only ADLINK date the BIOS was build. 7.2.2 Processor Information Feature Options Description CPU Brand String Info only Display CPU Brand Name.
7.2.4 System Management 7.2.4.1 System Management > Board Information Board Information Info only SMC Firmware Read only Display SMC Firmware. Build Date Read only Display SMC firmware build date. SMC Boot loader Read only Display SMC boot loader. Build Date Read only Display SMC boot loader build date. Hardware Version Read only Display SMC hardware Version. Serial Number Read only Display SMC serial Number. Manufacturing Date Read only Display SMC manufacturing date.
Feature Options Description AIN0 Read only Display actual voltage of AIN0 V3.30 Read only Display actual voltage of 3.30 V V1.05 Read only Display actual voltage of 1.05 V V3.30 Read only Display actual voltage of 3.30 V V1.35 Read only Display actual voltage of 1.35 V V5.00 Read only Display actual voltage of 5.00 V VIN Read only Display actual voltage of VIN AIN7 Read only Display actual voltage of AIN7 7.2.4.
7.2.4.6 System Management > Power Up Feature Options Power Up Info only Power Up watchdog Attention: F12 disables the Power Up Watchdog. Enabled Disabled The Power-Up Watchdog resets the system after a certain amount of time after power-up. Disabled Enable Reduces the power consumption of the system. Turn on Remain off Last State Turn On: The machine starts automatically when the power supply is turned on. Remain Off :To start the machine the power button has to be pressed.
7.2.
7.3 Advanced This menu contains the settings for most of the user interfaces in the system 7.3.1 CPU Feature Options Description CPU Info only Manufacturer, model, speed CPU Signature Info only Display CPU Signature. Processor Family Info only Display Processor Family. Microcode Patch Info only Display Microcode Patch. FSB Speed Info only Display FSB Speed Max CPU speed Info only Display Max CPU speed. Min CPU speed Info only Display Min CPU speed.
Feature Options Description Enabled CPU C3 Report Disabled Enabled Enable/Disable CPU C3 report to OS. CPU C6 Report Disabled Enabled Enable/Disable CPU C6 report to OS. CPU C7 Report Disabled CPU C7 CPU C7S Enable/Disable CPU C7 report to OS. ACPI T State Disabled Enabled Enable/Disable ACPI T state support. CPU DTS Disabled Enabled Enable/Disable CPU DTS. Feature Options Description Memory RC Version Info only Display Memory Reference Code Version.
7.3.3 Graphics Feature Options Graphics Configuration Info only IGFX VBIOS Version Info only Display VBIOS Version. IGfx Frequency Info only Display IGfx Frequency. Graphics Turbo IMON Current Number entry field Graphics turbo IMON current values supported (14-31). Primary Display Auto IGFX PEG PCIE Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select SG for Switchable Gfx.
Feature Options Description LCD Panel Type VBIOS Default 640X480 800X600 1024X768 1280X1024 1400X1050 1600X1200 1366X768 1680X1050 1920X1200 1440X900 1600X900 1024X768 LVDS2 1280X800 1920X1080 2048X1536 Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item. Active LFP No LVDS Edp Port-A Select the Active LFP Configuration.
Feature Options Description Gen3 Intel ® Rapid Start Technology Submenu SATA Port Configuration Submenu Software Feature Mask Configuration Info only RAID0 Enabled Disabled Enable/Disable RAID0 feature. RAID1 Enabled Disabled Enable/Disable RAID1 feature. RAID10 Enabled Disabled Enable/Disable RAID10 feature. RAID5 Enabled Disabled Enable/Disable RAID5 feature. Intel Rapid Recovery Technology Enabled Disabled Enable/Disable Intel Rapid Recovery Technology.
7.3.4.2 SATA > SATA Port Configuration (IDE) Feature Options SATA Port Configuration Info only Serial ATA Port x Info only SATA Port x information Software Preserve Info only Designates this port as software preserve SATA-to-PATA Info only PATA devices information 7.3.5 Description USB Feature Options USB Module Version Info only USB Devices Info only X Drive, X Keyboards, X Mouse, X Hubs Legacy USB Support Enabled Disabled Auto Enables legacy USB support.
Feature Options Description Enabled faster enumeration. USB Port #0~13 Disabled Enabled Control each of the USB ports (0~13) disabling. USB30 Port #0~5 Disabled Enabled Enable or Disable USB 3.0 Port. 7.3.6 Network Feature Options Description Network Stack Info only Network Stack Enabled Disabled Enable/Disable UEFI network stack. PCH LAN Controller Enabled Disabled Enable/Disable onboard NIC. Wake on LAN Enabled Disabled Enable/Disable integrated LAN to wake the system.
7.3.
Feature Restore PCIE Registers Options Description Enabled Disabled On non-PCI Express aware OS's (Pre Windows Vista) some devices may not be correctly reinitialized after S3. Enabling this restors PCI Express device configurations on S3 resume. Warning: Enabling this may cause issues with other hardware after S3 resume. PEG Configuration (System Agent) Submenu PCH-PCIe Configuration Submenu 7.3.7.
7.3.7.2 PCI and PCIe > PCH-PCIe Configuration Feature Options PCH-PCIe Configuration Info only Description PCI Express Clock Gating Disabled Enable Enable/Disable PCI Express Clock Gating for each root port. DMI Link ASPM Control Disabled Enable The control of Active State Power Management on both NB side and SB side of the DMI Link. DMI Link Extended Synch Control Disabled Enable The control of Extended Synch on SB side of the DMI Link.
Feature Options Description SECE Disabled Enable Enable/Disable Root PCI Express System Error on Correctable Error. PME SCI Disabled Enable Enable/Disable PCI Express PME SCI. Hot Plug Disabled Enable Enable/Disable PCI Express Hot Plug. PCIe Speed Auto Gen1 Gen2 Select PCI Express port speed. Detect Non-Compiance Disabled Enable Detect Non-Compliance PCI Express Device. If enabled, it will take more time at POST time.
Feature Change Settings N5104D Super IO Configuration Serial Port 1 Configuration Serial Port Options Description Auto IO=2F8h; IRQ=3 IO=3F8h; IRQ=3,4,5,6,7,10,11,12 IO=2F8h; IRQ=3,4,5,6,7,10,11,12 IO=3E8h; IRQ=3,4,5,6,7,10,11,12 IO=2E8h; IRQ=3,4,5,6,7,10,11,12 Select an optimal setting for Super IO device. Info only Enabled Disabled Enable/Disable Serial Port (COM). Device Settings IO=240h; IRQ=10 Fixed configuration of serial port.
7.3.10 Sound Feature Options Sound Info only Azalia Disabled Enabled Auto Control Detection of the Azalia device. Disabled = Azalia will be unconditionally disabled. Enabled = Azalia will be unconditionally enabled. Auto = Azalia will be enabled if present, disabled other. Azalia Docking Support Enabled Disabled Enable/Disable Azalia Docking Support of Audio Controller. Azalia PME Enabled Disabled Enable/Disable Power Management capability of Audio Controller.
Feature Options Description Data Bits 7 8 Select Data Bits. Parity None Even Odd Mark Space Select Parity. Stop Bits 1 2 Select number of stop bits. Flow Control None Hardware RTS/CTS Select flow control. VT-UTF8 Combo Key Support Disabled Enable Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals. Recorder Mode Disabled Enable With this mode enabled only text will be sent. This is to capture Terminal data.
7.3.13 Thermal Feature Options Thermal Info only Automatic Thermal Reporting Enabled Disabled Configure _CRT, _PSV and _AC0 automatically based on values recommended in BWG’s Thermal Reporting for Thermal Management settings. Set to Disabled for manual conmfiguration. Critical Trip Point Disabled 85 C 95 C This value controls the temperature of the ACPI Critical Trip Point the point in which the OS will shut the system off. NOTE: 100C is the Plan Of Record (POR) for all Intel mobile processors.
Feature Options Description GPIO Lock Enabled Disabled Enable or Disable the GPIO lockdown BIOS Interface Lock Enabled Disabled Enable or Disable the BIOS interface lockdown RTC RAM Lock Enabled Disabled Enable or Disable bytes 38h-2Fh in the upper and lower 128byte bank of the RTC RAM lockdown 7.3.14.2 Miscellaneous > Trusted Computing Feature Options Description Security Device Support Enabled Disabled Enables or Disables BIOS support for security device.
7.4 Boot 7.4.1 Boot Configuration Feature Options Description Boot Configuration Info only Setup Prompt Timeout 1 Enable/Disable the onboard SATA controllers. Bootup NumLock State On Select SATA controller mode. Quiet Boot Disabled Enabled Enable/Disable the PATA port. In fact this enables or disables the SATA channel on which the onboard SATA to PATA converter is attached.
7.5 Security 7.5.1 Password Description Feature Options Administrator Password Enter password User Password Enter password Secure Boot menu Submenu 7.5.2 Description Secure Boot Menu Feature Options Description System Mode Setup Secure Boot Info only Secure Boot Support Disabled Enabled Secure Boot can be enabled if 1.System running in User mode with enrolled Platform Key(PK) 2.CSM function is disabled. Secure Boot Mode Standard Custom Secure Boot mode selector.
8 BIOS Checkpoints, Beep Codes This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions. Checkpoints and Beep Codes Definition A checkpoint is either a byte or word value output to I/O port 80h.
8.1 Status Code Ranges Status Code Range Description 0x01 – 0x0F SEC Status Codes & Errors 0x10 – 0x2F PEI execution up to and including memory detection 0x30 – 0x4F PEI execution after memory detection 0x50 – 0x5F PEI errors 0x60 – 0xCF DXE execution up to BDS 0xD0 – 0xDF DXE errors 0xE0 – 0xE8 S3 Resume (PEI) 0xE9 – 0xEF S3 Resume errors (PEI) 0xF0 – 0xF8 Recovery (PEI) 0xF9 – 0xFF Recovery errors (PEI) 8.2 Standard Status Codes 8.2.
8.2.2 SEC Beep Codes None 8.2.
Status Code Description 0x4F DXE IPL is started PEI Error Codes 0x50 Memory initialization error. Invalid memory type or incompatible memory speed 0x51 Memory initialization error. SPD reading has failed 0x52 Memory initialization error. Invalid memory size or memory modules do not match. 0x53 Memory initialization error. No usable memory detected 0x54 Unspecified memory initialization error.
8.2.4 PEI Beep Codes # of Beeps Description 1 Memory not Installed 1 Memory was installed twice (InstallPeiMemory routine in PEI Core called twice) 2 Recovery started 3 DXEIPL was not found 3 DXE Core Firmware Volume was not found 7 Reset PPI is not available 4 Recovery failed 4 S3 Resume failed 8.2.
Status Code Description 0x77 South Bridge DXE Initialization (South Bridge module specific) 0x78 ACPI module initialization 0x79 CSM initialization 0x7A – 0x7F Reserved for future AMI DXE codes 0x80 – 0x8F OEM DXE initialization codes 0x90 Boot Device Selection (BDS) phase is started 0x91 Driver connecting is started 0x92 PCI Bus initialization is started 0x93 PCI Bus Hot Plug Controller Initialization 0x94 PCI Bus Enumeration 0x95 PCI Bus Request Resources 0x96 PCI Bus Assign Resou
Status Code Description 0xAF Exit Boot Services event 0xB0 Runtime Set Virtual Address MAP Begin 0xB1 Runtime Set Virtual Address MAP End 0xB2 Legacy Option ROM Initialization 0xB3 System Reset 0xB4 USB hot plug 0xB5 PCI bus hot plug 0xB6 Clean-up of NVRAM 0xB7 Configuration Reset (reset of NVRAM settings) 0xB8 – 0xBF Reserved for future AMI codes 0xC0 – 0xCF OEM BDS initialization codes DXE Error Codes 0xD0 CPU initialization error 0xD1 North Bridge initialization error 0xD2 So
8.2.7 ACPI/ASL Checkpoint Status Code Description 0x01 System is entering S1 sleep state 0x02 System is entering S2 sleep state 0x03 System is entering S3 sleep state 0x04 System is entering S4 sleep state 0x05 System is entering S5 sleep state 0x10 System is waking up from the S1 sleep state 0x20 System is waking up from the S2 sleep state 0x30 System is waking up from the S3 sleep state 0x40 System is waking up from the S4 sleep state 0xAC System has transitioned into ACPI mode.
9 Mechanical Information 9.1 Board-to-Board Connectors To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When 5 mm receptacles are chosen, the carrier board should be free of components. Tyco 3-1827253-6 Foxconn QT002206-2131-3H • 220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm. • This connector can be used with 5 mm through-hole standoffs (SMT type).
9.2 Thermal Solution 9.2.1 Heat Spreaders The function of the heat spreader is to ensure an identical mechanical profile for all COM Express modules. By using a heat spreader, the thermal solution that is built on top of the module is compatible with all COM Express modules. 9.2.2 Heat Sinks A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless, depending on the thermal requirements. 9.2.
Step 4: Use the four M2.5, L=6mm screws provided to fasten the heatsink to the module. Step 5: Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown. Then press down on the module until it is firmly seated on the carrier board. Step 6: Use the five M2.5, L=16mm screws provided to secure the COM Express module to the carrier board from the solder side. Step 7: If you are installing a heatsink with a fan, plug the fan connector into the carrier board as shown.
9.3 Mounting Methods There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the choice of 5 mm or 8mm board-to-board connectors, there is the choice of Top and Bottom mounting. In Top mounting, the threaded standoffs are on the carrier board and the thermal solution is equipped with through-hole standoffs. In Bottom mounting, the threaded standoffs are on the thermal solution and the carrier board has through-hole standoffs.
9.4 Standoff Types The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and throughhole standoffs are SMT type. Other types not listed are available upon request.
Safety Instructions Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use. • Please read these safety instructions carefully. • Please keep this User‘s Manual for later reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment.
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