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Express-IB

User’s Manual

Manual Revision: 2.03

Revision Date: December 3, 2014

Part Number: 50-1J044-1030

Summary of content (80 pages)

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Express-IB User’s Manual Manual Revision: 2.
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Revision History Revision Description Date By 2.00 Initial release 2013-08-30 JC 2.01 Correct CPU support spec (Intel® Core™ i7-3615QE); correct GBE0_MDI0- pin description 2013-10-25 JC 2.02 Add Celeron® SKUs; update PCIe expansion specifications 2014-07-04 JC 2.03 Add BIOS beep codes; remove Industrial Temp.
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Preface Copyright 2013-14 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.
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Table of Contents Revision History ............................................................................................................ 2 Preface............................................................................................................................ 3 1. Introduction ......................................................................................................... 7 2. Specifications........................................................................................
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3.3.9. USB...................................................................................................................................................21 3.3.10. SPI (BIOS only) .............................................................................................................................22 3.3.11. Miscellaneous..............................................................................................................................22 3.3.12. SMBus..............................
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7.1.1. Setup Menu......................................................................................................................................42 7.1.2. Navigation ........................................................................................................................................43 7.2. Main Setup ............................................................................................................................ 46 7.3. Advanced Setup...............................
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1. Introduction The Express-IB is a COM Express® COM.0 R2.1 Type 6 module supporting the 64-bit 3rd Generation Intel® Core™ i7/i5/3 and Celeron® processor with CPU, memory controller, and graphics processor on the same chip. Based on the latest Mobile Intel® QM77 Express chipset, the Express-IB is specifically designed for customers who need high-level processing and graphics performance in a long product life solution.
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2. Specifications 2.1. Core System ¾ CPU: 3rd Generation Intel® Core™, Celeron® Processor, 2/4-core mobile processor with Integrated Graphics, BGA 1023 type • • • • • • • • • • Intel® Core™ i7-3615QE Intel® Core™ i7-3612QE Intel® Core™ i7-3555LE Intel® Core™ i7-3517UE Intel® Core™ i5-3610ME Intel® Core™ i3-3120ME Intel® Core™ i3-3127UE Intel® Celeron® 1020E Intel® Celeron® 1047UE Intel® Celeron® 927UE quad-core 2.3 GHz (3.3/3.1 GHz Turbo), 6MB L3 cache, 45W quad-core 2.1 GHz (3.1/2.
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¾ Display Types • • • VGA Interface support with 300 MHz DAC Analog monitor support up to QXGA (2048 x 1536) LVDS Interface Dual channel 18/24-bit LVDS Three Digital Display Ports DDI0 supporting HDMI / DisplayPort / SDVO DDI1 supporting HDMI / DisplayPort DDI2 supporting HDMI / DisplayPort 2.4. Audio ¾ Integrated: Intel® HD Audio integrated in PCH QM77 ¾ Audio Codec: Realtek ALC888/886 on Express-BASE6 2.5.
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2.11. TPM (Trusted Platform Module) ¾ Chipset: Infineon SLB9635TT1.2 ¾ Type: TPM 1.2 2.12. Fan Control ¾ Control Source: Temperature Sensor ¾ Location • • ¾ On AB connector (B101/102): PWM and TACH 12V based on carrier 4-pin Mini connector on module: PWM and TACH 5V based on module Connection: route single source to dual locations 2.13. Debug ¾ JTAG: SFF connector for XDP to CPU ¾ LPC header: for mounting POST CODE assembly 2.14.
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2.17.
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2.18.
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3. Pinouts and Signal Descriptions The following information is a summary of the most important information regarding pinout and signal description in the official PICMG COM.0 Rev 2.0 (soon 2.1) The pinout is noted here to emphazise issues that have not been followed in the past. The following might have small inacuaracies so in case of doubt the offical design guide of PICMG should be consulted. 3.1. AB / CD Pin Definitions The Express-IB is a Type 6 module supporting USB3.
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Row A Row B Row C Row D Pin Name Pin Name Pin Name Pin Name A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 USB6USB6+ USB_6_7_OC# USB4USB4+ GND (FIXED) USB2USB2+ USB_2_3_OC# USB0USB0+ VCC_RTC EXCD0_PERST# EXCD0_CPPE# LPC_SERIRQ GND (FIXED) PCIE_TX5+ PCIE_TX5GPI0 PCIE_TX4+ PCIE_TX4GND PCIE_TX3+ PCIE_TX3GND (FIXED) PCIE_TX2+ PCIE_TX2GPI1 PCIE_TX1+ PCIE_TX1GND GPI2 PC
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Row A Row B Row C Row D Pin Name Pin Name Pin Name Pin Name A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94 A95 A96 A97 A98 A99 A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 LVDS_A_CK+ LVDS_A_CKLVDS_I2C_CK LVDS_I2C_DAT GPI3 RSVD RSVD PCIE0_CK_REF+ PCIE0_CK_REFGND (FIXED) SPI_POWER SPI_MISO GPO0 SPI_CLK SPI_MOSI TPM_PP TYPE10# SER0_TX SER0_RX GND (FIXED) SER1_TX SER1_RX LID# VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V GND (FIXED) B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91
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3.2. Signal Description Terminology The following terms are used in the COM Express AB/CD Signal Descriptions below. Page 16 I Input to the Module O Output from the Module I/O Bi-directional input / output signal OD Open drain output I 3.3V Input 3.3V tolerant I 5V Input 5V tolerant O 3.3V Output 3.3V signal level O 5V Output 5V signal level I/O 3.3V Bi-directional signal 3.3V tolerant I/O 5V Bi-directional signal 5V tolerant I/O 3.3Vsb Input 3.
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3.3. AB Signal Descriptions 3.3.1. Audio Signals Signal Pin # Description I/O AC_RST# / HDA_RST# A30 Reset output to CODEC, active low. O 3.3VSB AC_SYNC / HDA_SYNC A29 Sample-synchronization signal to the CODEC(s). O 3.3V AC_BITCLK / HDA_BITCLK A32 Serial data clock generated by the external CODEC(s). I/O 3.3V AC _SDOUT / HDA_SDOUT A33 Serial TDM data output to the CODEC. O 3.3V AC _SDIN[2:0] HDA_SDIN[2:0] B28 B30 Serial TDM data inputs from up to 3 CODECs. I/O 3.3VSB 3.3.2.
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Signal Pin # Description I/O LVDS_B1+ LVDS_B1LVDS_B2+ LVDS_B2LVDS_B3+ LVDS_B3- B73 B74 B75 B76 B77 B78 LVDS_B_CK+ LVDS_B_CK- B81 B82 LVDS Channel B differential clock O LVDS LVDS_VDD_EN A77 LVDS panel power enable O 3.3V LVDS_BKLT_EN B79 LVDS panel backlight enable O 3.3V LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3.3V LVDS_I2C_CK A83 DDC lines used for flat panel detection and control. O 3.3V PU 2k2 3.
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3.3.5. Serial ATA Signal Pin # Description I/O SATA0_TX+ SATA0_TX- A16 A17 Serial ATA channel 0, Transmit Output differential pair. O SATA AC coupled on Module SATA0_RX+ SATA0_RX- A19 A20 Serial ATA channel 0, Receive Input differential pair. I SATA AC coupled on Module SATA1_TX+ SATA1_TX- B16 B17 Serial ATA channel 1, Transmit Output differential pair. O SATA AC coupled on Module SATA1_RX+ SATA1_RX- B19 B20 Serial ATA channel 1, Receive Input differential pair.
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3.3.6. PCI Express Signal Pin # Description I/O PCIE_TX0+ PCIE_TX0- A68 A69 PCI Express channel 0, Transmit Output differential pair. O PCIE AC coupled on Module PCIE_RX0+ PCIE_RX0- B68 B69 PCI Express channel 0, Receive Input differential pair. I PCIE AC coupled off Module PCIE_TX1+ PCIE_TX1- A64 A65 PCI Express channel 1, Transmit Output differential pair. O PCIE AC coupled on Module PCIE_RX1+ PCIE_RX1- B64 B65 PCI Express channel 1, Receive Input differential pair.
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3.3.8. LPC bus Signal Pin # Description I/O LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V LPC_DRQ0# LPC_DRQ1# B8 B9 LPC serial DMA request I 3.3V LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V LPC_CLK B10 LPC clock output - 33MHz nominal O 3.3V 3.3.9. PU/PD Comment PU 8k2 3.3V USB Signal Pin # Description I/O USB0+ USB0- A46 A45 USB differential data pairs for Port 0 I/O 3.
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3.3.10. SPI (BIOS only) Signal Pin # Description I/O PU/PD Comment SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V.
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3.3.13. I2C Bus Signal Pin # Description I/O PU/PD Comment I2C_CK B33 General purpose I²C port clock output/input I/O OD 3.3VSB PU 2k2 3.3VSB I2C_DAT B34 General purpose I²C port data I/O line I/O OD 3.3VSB PU 2k2 3.3VSB PU/PD Comment 3.3.14. General Purpose I/O (GPIO) Signal Pin # Description I/O GPO[0] A93 General purpose output pins. O 3.3V GPO[1] B54 General purpose output pins. O 3.3V GPO[2] B57 General purpose output pins. O 3.
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Signal Pin # Description I/O PU/PD WAKE1# B67 General purpose wake up signal. May be used to implement wake-up on PS/2 keyboard or mouse activity. I 3.3VSB PU 10k 3.3VSB BATLOW# A27 Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low, or may be used to signal some other external power-management event. I 3.3VSB PU 10k 3.3VSB LID# LID button. Low active signal used by the ACPI operating system for a LID switch. I OD 3.
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3.4. CD Signal Descriptions 3.4.1. USB 3.
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3.4.3.
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DDI 2 Signal Pin Description DDI2_PAIR0+ D39 Digital Display Interface2 differential pairs DDI2_PAIR0- D40 DDI2_PAIR1+ D42 DDI2_PAIR1- D43 DDI2_PAIR2+ D46 DDI2_PAIR2- D47 DDI2_PAIR3+ D49 DDI2_PAIR3- D50 DDI2_HPD D44 DDI2_CTRLCLK_AUX+ C32 DDI2_CTRLCLK_AUX- DDI2_DDC_AUX_SEL C33 I/O PU/PD Comment IF DDI2_DDC_AUX_SEL is floating I/O PCIe DP2_AUX+ IF DDI2_DDC_AUX_SEL pulled high I/O OD 3.
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3.4.4.
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3.4.5.
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Signal Pin PEG_TX15+ PEG_TX15- D101 D102 PEG_LANE_RV# D54 3.4.6. Description I/O PU/PD Comment AC coupled off Module PCI Express Graphics lane reversal input strap. Pull low on the Carrier board to reverse lane order. I 1.05V Module Type Definition Signal Pin # Description I/O TYPE0# TYPE1# TYPE2# C54 C57 D57 The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are noconnects (NC).
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4. Module Configuration 4.1. PCI Express Configuration Switch (SW1) Switch SW1 allows you to configure the PCI Express x16 lanes from the CPU as 1 PCIe x16, 2 PCIe x8, or 1 PCIe x8 + 2 PCIe x4. Mode Pin 1 Pin 2 1 PCIe x8 + 2 PCIe x4 On On Reserved On Off 2 x8 PCI Express Off On 1 x16 PCI Express (Default) Off Off 4.2.
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5. Embedded Functions All embedded board functions on ADLINK’s Computer on Modules are supported at the operating system level using the ADLINK Intelligent Device Interface (AIDI) library. The AIDI API programming interface is compatible and identical across all ADLINK Computer on Modules and all supported operating systems. The AIDI library includes a demo program to demonstrate the library’s functionallity. 5.1.
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5.2. GPIO GPIO library support is limited to GPIO signals that originate from the Computer on Module and extend to the carrier board. COM Express modules support 4 GPO and 4 GPI signals. Some of ADLINK’s COM Express boards can configure all 8 ports for GPI or GPO use. GPIO signals can be monitored and controlled by using the ADLINK Intelligent Device Interface (AIDI) library that is compatible and identical across all ADLINK COM Express modules and all supported operating systems.
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5.3. Hardware Monitoring To ensure system health of your embedded system ADLINK’s COM Express modules come with built in support for monitoring and control of CPU and system temperatures, fan speed and critical module voltage levels. The AIDI Library provides simple APIs at the application level to support these functions and adds alarm functions when voltage or temperature levels exceed the upper or lower limit set by the user.
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6. System Resources 6.1.
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6.3.
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Hex Range Device 2F8-2FF Serial Port 2 300-36F Available 370-377 Alt.
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6.4.
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IRQ# Typical Intterupt Resource Connected to Pin Available 20 N/A PCH internal GBE controller Note (1) 21 N/A UHCI Controller 5 Note (1) 22 N/A PCH HDA Note (1) 23 N/A UHCI Controller , EHCI Controller Note (1) Note (1): These IRQs can be used for PCI devices when onboard device is disabled. If IRQ is from ISA, user must reserve IRQ for ISA in BIOS setup menu. 6.5.
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6.6. PCI Interrupt Routing Map INT Line LPC Interface Bridge SATA SATA SMBUS XHCI EHCI EHCI Controller Controller Controller Controller Controller Controller #0 #1 #0 #1 INTA:16 INTH:23 Int0 INTF:21 Int1 INTD:19 Int2 INTC:18 Int3 INTA:16 INT Line Manageme PCIE Root nt Engine Port#0 Int0 INTA:16 INTA:16 Int1 INTD:19 INTB:17 Int2 INTC:18 INTC:18 Int3 INTB:17 INTD:19 INT I.G.F.
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7. BIOS Setup The following chapter describes basic navigation for the AMIBIOS®EFI BIOS setup utility. 7.1. Starting the BIOS To enter the setup screen, follow these steps: 1. Power on the motherboard 2. Press the < Delete > key on your keyboard when you see the following text prompt: < Press DEL to run Setup > 3. After you press the < Delete > key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu, such as Chipset and Power menus.
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7.1.1. Setup Menu The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user’s guide. The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. “Grayed” options cannot be configured, “Blue” options can be. The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white.
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7.1.2. Navigation The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process. These keys include < F1 >, < F10 >, < Enter >, < ESC >, < Arrow > keys, and so on. There is a hot key legend located in the right frame on most setup screens. →← ↑↓ +Tab Express-IB Left/Right. The Left and Right < Arrow > keys allow you to select a setup screen.
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Hot Key Description Enter The < Enter > key allows you to display or change the setup option listed for a particular setup item. The < Enter > key can also allow you to display the setup sub-screens. F1 The < F1 > key allows you to display the General Help screen. Press the < F1 > key to open the General Help screen. F2 The < F2 > key on your keyboard is the previous values key. It is not displayed on the key legend by default.
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F4 ESC The < F4 > key allows you to save any changes you have made and exit Setup. Press the < F4 > key to save your changes. The following screen will appear: Press the < Enter > key to save the configuration and exit. You can also use the < Arrow > key to select Cancel and then press the < Enter > key to abort this function and return to the previous screen. The < Esc > key allows you to discard any changes you have made and exit the Setup.
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7.2. Main Setup System & Board Info The Main BIOS setup screen reports board information. ¾ Project Version Displays the current BIOS version. ¾ Build Data Displays the BIOS build data. System Date/System Time Use this option to change the system time and date. Highlight System Time or System Date using the < Arrow > keys. Enter new values using the keyboard. Press the < Tab > key or the < Arrow > keys to move between fields. The date must be entered in MM/DD/YY format.
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7.3. Advanced Setup 7.3.1. ACPI Settings ACPI Sleep State Select the highest ACPI sleep state the system will enter, when the SUSPEND button is pressed Emulation AT/ATX Select Emulation AT or ATX function.If this option set to [Emulation AT], BIOS will report no suspend functions to ACPI OS. In Windows XP, it will make the OS show a shutdown message during system shutdown.
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7.3.2. Trusted Computing Security Device Support Enables or Disables BIOS support for security device. OS will not show Security Device.TCG EFI protocol and INT1A interface will not be available.
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7.3.3. CPU Configuration Hyper-threading Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for HyperThreading Technology). When disabled, only one thread per enabled core is enabled. Limit CPUID Maximum Disabled for Windows XP. Execute Disable Bit XD can prevent certain classes of malicious buffer overflow attacks when combined with a supporting OS (Windows Server 2003 SP1, Windows XP SP2, SuSE Linux 9.
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7.3.4. SATA Configuration SATA Controller(s) Enables or disable SATA Device. SATA Mode Selection Determines how SATA controller(s) operate. 7.3.5.
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7.3.6. PCH-FW Configuration MDES BIOS Status Code Enable/Disable MDES BIOS Status Code. Firmware Update Configuration Configure Management Engine Technology Parameters.
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7.3.7. Intel Anti-Theft Technology Configuration Intel(R) Anti-Theft Technology Enable/Disable Intel(R) AT in BIOS for testing only. Intel(R) Anti-Theft Technology Rec 3 Set the number of times Recovery attemped will be allowed.
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7.3.8. AMT Configuration Intel AMT Enable/Disable Intel Active Management Technology BIOS Extension. Note: iAMT H/W is always enabled. This option just controls the BIOS extension execution. If enabled, this requires additional firmware in the SPI device BIOS Hotkey Pressed OEMFlag Bit 1: Enable/Disable BIOS hotkey press. MEBx Selection Screen OEMFlag Bit 2: Enable/Disable MEBX selection screen.
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PET Progress User can Enable/Disable PET Events progress to receive PET event or not. WatchDog Enable/Disable WatchDog Timer. 7.3.9. USB Configuration Legacy USB Support Enables Legacy USB support. AUTO option, disables legacy support if no USB devices are connected. DISABLE option will keep USB devices available only for EFI applications. USB3.0 Support Enable/Disable USB3.0(XHCI) Controller support. XHCI Hand-off This is a workaround for OSes without XHCI hand-off support.
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7.3.10. ADT 7490 H/W Monitor Smart Fan Mode Configuration Smart Fan Mode Select. 7.3.11.
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7.3.12. Serial Port Console Redirection Console Redirection Console Redirection Enable or Disable. Console Redirection Setttings The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.
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7.3.13. CPU PPM Configuration EIST Enable/Disable Intel SpeedStep Turbo Mode Turbo Mode.
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7.4. Chipset Setup 7.4.1.
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PCI Express Configuration PCI Express Clock Gat Enable or disable PCI Express Clock Gating for each root port. DMI Link ASPM Control The control of Active State Power Management on both NB side and SB side of the DMI Link. DMI Link Etended Syn The control of Extended Synch on SB side of the DMI Link. PCIe-USB Glitch W/A PCIe-USB Glitch W/A for bad USB device(s) connected behind PCIE/PEG Port.
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USB Configuration XHCI Pre-Boot Driver Enable or disable xHCI Pre-Boot Driver support. xHCI Mode Mode of operation of XHCI Controller. HS Port #1/2/3 Switcchable Allows for HS port switching between xHCI and EHCI.\n\nIf disabled, port is routed to EHCI.\n\nIf HS port is routed to xHCI, the corresponding SS port is enabled. xHCI Streams Enable or disable xHCI Maximum Primary Stream Array Size. EHCI1/2 Control the USB EHCI (USB 2.0) functions. One EHCI controller must always be enabled.
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7.4.2. System Agent (SA) Configuration Graphics Configuration Graphics Turbo IMON Current Graphics turbo IMON current values supported (14-31) Primary Display Select which of IGFX/PEG/PCI Graphics device should be Primary Display, or select SG for Switchable Gfx. Internal Graphics Keep IGD enabled based on the setup options.
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GTT Size Select the GTT Size Aperture Size Select the Aperture Size DVMT Pre-Allocated Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device. DVMT Total Gfx Mem Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device. Gfx Low Power Mode This option is applicable for SFF only. Graphics Performance Enable or disable Intel Graphics Performance Analyzers Counters.
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GTT LVDS Backlight Control GTT LVDS Backlight Control. Note: This setting will be reset by the Graphics Driver. DDI function choose DDI function set to Display Port or HDMI. BIA Auto: GMCH use VBT default. Level n: Enabled with selected aggressiveness level. Spread Spectrum clock Hardware: Spread is controlled by chip. Software: Spread is controlled by BIOS.
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Enable PEG Enable or disable the PEG. Detect Non-Compliance Detect Non-Compliant PCI Express Device in PEG. De-emphasis Control Configure the De-emphasis control on PEG PEG Sampler Calibrate Enable or disable PEG Sampler Calibrate. Auto means Disabled for SNB MB/DT, Enabled for IVB A0 B0. Swing Control Perform PEG Swing Control, on IVB C0 and later. Gen3 Equalization Perform PEG Gen3 Equalization steps.
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Memory Configuration DIMM profile Select DIMM timing profile that should be used. Memory Frequency Limiter Maximum Memory Frequency Selections in MHz. ECC Support Enable or disable DDR ECC Support. Max TOLUD Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic controller. NMode Support NMode support option. Memory Scrambler Enable or disable Memory Scrambler support. MRC Fast Boot Enable or disable MRC fast boot.
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Memory Remap Enable or disable memory remap above 4G. Memory Alias Check Enable or disable memory Alias Check. Channel A DIMM Control Enable or disable DIMMs on Channel A. Channel B DIMM Control Enable or disable DIMMs on Channel B.
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7.5. Boot Setup Setup Prompt Timeout Number of seconds to wait for setup activation key. 65535 (0xFFFF) means indefinite waiting. Bootup Numlock State Select the keyboard NumLock state Quiet Boot Enable or disables Quiet Boot option Fast Boot Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot options. GateA20 Active Upon Request - GA20 can be disabled using BIOS services.
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7.6.
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7.7. Save & Exit Menu Save Changes and Exit Exit system setup after saving the changes. Discard Changes and Exit Exit system setup without saving any changes. Save changes and Reset Reset the system after saving the changes. Discard changes and Reset Reset system setup without saving any changes. Save changes Save Changes done so far to any of the setup options. Discard Changes Discard Changes done so far to any of the setup options. Restore Defaults Restore/Load Default values for all the setup options.
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8. BIOS Checkpoints, Beep Codes This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions. Checkpoints and Beep Codes Definition A checkpoint is either a byte or word value output to I/O port 80h.
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8.1. Status Code Ranges Status Code Range Description 0x01 – 0x0F SEC Status Codes & Errors 0x10 – 0x2F PEI execution up to and including memory detection 0x30 – 0x4F PEI execution after memory detection 0x50 – 0x5F PEI errors 0x60 – 0xCF DXE execution up to BDS 0xD0 – 0xDF DXE errors 0xE0 – 0xE8 S3 Resume (PEI) 0xE9 – 0xEF S3 Resume errors (PEI) 0xF0 – 0xF8 Recovery (PEI) 0xF9 – 0xFF Recovery errors (PEI) 8.2. Standard Status Codes 8.2.1.
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8.2.2. SEC Beep Codes None 8.2.3.
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Status Code Description 0x4F DXE IPL is started PEI Error Codes 0x50 Memory initialization error. Invalid memory type or incompatible memory speed 0x51 Memory initialization error. SPD reading has failed 0x52 Memory initialization error. Invalid memory size or memory modules do not match. 0x53 Memory initialization error. No usable memory detected 0x54 Unspecified memory initialization error.
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8.2.4. PEI Beep Codes # of Beeps Description 1 Memory not Installed 1 Memory was installed twice (InstallPeiMemory routine in PEI Core called twice) 2 Recovery started 3 DXEIPL was not found 3 DXE Core Firmware Volume was not found 7 Reset PPI is not available 4 Recovery failed 4 S3 Resume failed 8.2.5.
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Status Code Description 0x77 South Bridge DXE Initialization (South Bridge module specific) 0x78 ACPI module initialization 0x79 CSM initialization 0x7A – 0x7F Reserved for future AMI DXE codes 0x80 – 0x8F OEM DXE initialization codes 0x90 Boot Device Selection (BDS) phase is started 0x91 Driver connecting is started 0x92 PCI Bus initialization is started 0x93 PCI Bus Hot Plug Controller Initialization 0x94 PCI Bus Enumeration 0x95 PCI Bus Request Resources 0x96 PCI Bus Assign Resou
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Status Code Description 0xAF Exit Boot Services event 0xB0 Runtime Set Virtual Address MAP Begin 0xB1 Runtime Set Virtual Address MAP End 0xB2 Legacy Option ROM Initialization 0xB3 System Reset 0xB4 USB hot plug 0xB5 PCI bus hot plug 0xB6 Clean-up of NVRAM 0xB7 Configuration Reset (reset of NVRAM settings) 0xB8 – 0xBF Reserved for future AMI codes 0xC0 – 0xCF OEM BDS initialization codes DXE Error Codes 0xD0 CPU initialization error 0xD1 North Bridge initialization error 0xD2 So
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8.2.7. ACPI/ASL Checkpoint Status Code Description 0x01 System is entering S1 sleep state 0x02 System is entering S2 sleep state 0x03 System is entering S3 sleep state 0x04 System is entering S4 sleep state 0x05 System is entering S5 sleep state 0x10 System is waking up from the S1 sleep state 0x20 System is waking up from the S2 sleep state 0x30 System is waking up from the S3 sleep state 0x40 System is waking up from the S4 sleep state 0xAC System has transitioned into ACPI mode.
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Safety Instructions Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use. • Please read these safety instructions carefully. • Please keep this User‘s Manual for later reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment.
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Getting Service ADLINK Technology, Inc. Address: Tel: Fax: Email: 9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan +886-2-8226-5877 +886-2-8226-5717 service@adlinktech.com Ampro ADLINK Technology, Inc. Address: Tel: Toll Free: Fax: Email: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA +1-408-360-0200 +1-800-966-5200 (USA only) +1-408-360-0222 info@adlinktech.com ADLINK Technology (China) Co., Ltd. Address: Tel: Fax: Email: 300 Fang Chun Rd.
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ADLINK Technology, Inc. (French Liaison Office) Address: 6 allée de Londres, Immeuble Ceylan 91940 Les Ulis, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com ADLINK Technology Japan Corporation Address: KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho, Chiyoda-ku Tokyo 101-0045, Japan Tel: +81-3-4455-3722 Fax: +81-3-5209-6013 Email: japan@adlinktech.com ADLINK Technology, Inc.