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Express-IBE2

User’s Manual

Manual Revision: 2.02

Revision Date: December 3, 2014

Part Number: 50-1J045-1020

Summary of content (83 pages)

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Express-IBE2 User’s Manual Manual Revision: 2.
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Revision History Revision Description Date By 2.00 Initial release 2013-08-30 JC 2.01 Correct CPU models, GBE0_MDI0- pin description; remove "Type 6", "USB 3.0", "QNX"; update Functional Diagram 2014-02-10 JC 2.02 Add BIOS beep codes; remove Industrial Temp.
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Preface Copyright 2013-14 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.
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Table of Contents Revision History ............................................................................................................ 2 Preface............................................................................................................................ 3 1. Introduction ......................................................................................................... 7 2. Specifications........................................................................................
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3.3.11. Miscellaneous..............................................................................................................................23 3.3.12. SMBus..........................................................................................................................................24 3.3.13. I2C Bus.........................................................................................................................................24 3.3.14. General Purpose I/O (GPIO) ...........
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.3.9. AMT Configuration...........................................................................................................................55 6.3.10. USB Configuration .......................................................................................................................56 6.3.11. W8362DHG Super IO Configuration............................................................................................57 6.3.12. Serial Port Console Redirection..................................
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1. Introduction The Module Computing Product Segment (MCPS) is pleased to introduce its latest COM Express® Type 2 Module with Intel® Core™ i7/i5/i3 Processor and QM77 Chipset, the Express-IBE2. The Express-IBE2 is a COM Express® COM.0 R2.1 Type 2 module with a 3rd Generation Intel® Core™ i7/i5/3 processor and support for error-correcting code (ECC) memory.
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2. Specifications 2.1. Core System • CPU: 3rd Generation Intel® Core™ Processor, 2-core and 4-core mobile processor with Integrated Graphics, BGA 1023 type • Intel® Core™ i7-3615QE Quad-Core at 2.3 GHz (3.3/3.1 GHz Turbo), 6MB L3 cache, 45W • Intel® Core™ i7-3612QE Quad-Core at 2.1 GHz (3.1/2.8 GHz Turbo), 6MB L3 cache, 35W • Intel® Core™ i7-3555LE Dual-Core at 2.5 GHz (3.2/3.1 GHz Turbo), 4MB L3 cache, 25W • Intel® Core™ i7-3517UE Dual-Core at 1.7 GHz (2.8/2.
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2.2. Expansion Busses • PCI Express Gen 3.0 Graphics (PEG) Port x16 supporting up to 8GT/Sec transactions Configurable as 1 x16 , 2 x8 or 1 x8-lane and 2 x4-lane • AB Connenctor PCI Express Gen 2.0 Ports 8 x1 from PCH, 5 x1 free for use (lane 7 to GbE LAN, lane 6 to PCI bridge, lane 5 to PATA bridge) Port 0/1/2/3/4 configurable as 5 x1 or 1 x4 and 1 x1 • LPC bus, SPI bus (BIOS only) • SMBus (system) , I2C (user) 2.3.
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2.7. Super I/O (on carrier using LPC -bus) • Chipset: Winbond W83627HG-AW and W83627DHG-P, without keyboard A20 line • Parallel Port: LPT1 • Serial Ports: COM1 / COM2 (with console redirection) 2.8. GPIO • Chipset: NXP PCA9535 • Description: 16-bit I2C-bus and SMBus, low power I/O port with interrupt • GPO: 4 ports • GPI: 4 ports with interrupt 2.9.
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2.12. Power Specifications • Power Modes: • Standard Voltage Input: ATX = 12V±5% / 5Vsb or AT = 12V±5% • Wide Voltage Input: ATX = 8.5~19V / 5Vsb or AT = 8.5 ~19V • Power Management: ACPI 3.0 compliant, Smart battery support. • Power States: AT and ATX mode (AT mode start controlled by ADMT) supports C1-C6, S0, S1, S4, S3, S5 (Wake on USB S3/S4, WOL S3/S4/S5) 2.13. Mechanical and Environmental • Standard Operating Temperature: 0 to 60°C 2.14. Specification Compliance • PICMG COM.0: Rev 2.
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2.15.
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2.16.
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3. COM Express Pinouts and Signal Descriptions The following information is a summary of the most important information regarding pinout and signal description in the official PICMG COM.0 Rev 2.0 (soon 2.1) The pinout is described here to emphazise issues that have not been followed in the past. The following description may still contain small inacuaracies; in case of doubt, the offical design guide of PICMG should be consulted. 3.1.
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A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 USB6+ USB_6_7_OC# USB4USB4+ GND (FIXED) USB2USB2+ USB_2_3_OC# USB0USB0+ VCC_RTC EXCD0_PERST# EXCD0_CPPE# LPC_SERIRQ GND (FIXED) PCIE_TX5+ PCIE_TX5GPI0 PCIE_TX4+ PCIE_TX4GND PCIE_TX3+ PCIE_TX3GND (FIXED) PCIE_TX2+ PCIE_TX2GPI1 PCIE_TX1+ PCIE_TX1GND GPI2 PCIE_TX0+ PCIE_TX0GND (FIXED) LVDS_A0+ LVDS_A0LVDS_A1+
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A88 A89 A90 A91 A92 A93 A94 A95 A96 A97 A98 A99 A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 Page 16 PCIE0_CK_REF+ PCIE0_CK_REFGND (FIXED) SPI_POWER SPI_MISO GPO0 SPI_CLK SPI_MOSI GND TYPE10# RSVD RSVD GND (FIXED) RSVD RSVD RSVD VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V GND (FIXED) B88 B89 B90 B91 B92 B93 B94 B95 B96 B97 B98 B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 BIOS_DIS1# VGA_RED GND (FIXED) VGA_GRN VGA_BLU VGA_HSYNC VGA_VSYNC VGA_I2C_CK VGA_I2C_DAT SPI_CS# RSVD RSV
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3.2. Signal Description Terminology These terms are used in the COM Express AB/CD Signal Descriptions which follow. I Input to the Module O Output from the Module I/O Bi-directional input/output signal OD Open drain output I 3.3V Input 3.3V tolerant I 5V Input 5V tolerant O 3.3V Output 3.3V signal level O 5V Output 5V signal level I/O 3.3V Bi-directional signal 3.3V tolerant I/O 5V Bi-directional signal 5V tolerant I/O 3.3Vsb Input 3.
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3.3. AB Signal Descriptions 3.3.1. Audio Signals Signal Pin Description I/O AC_RST# / HDA_RST# A30 Reset output to CODEC, active low. O 3.3VSB AC_SYNC / HDA_SYNC A29 Sample-synchronization signal to the CODEC(s). O 3.3V AC_BITCLK / HDA_BITCLK A32 Serial data clock generated by the external CODEC(s). I/O 3.3V AC _SDOUT / HDA_SDOUT A33 Serial TDM data output to the CODEC. O 3.3V AC _SDIN[2:0] HDA_SDIN[2:0] B28 B30 Serial TDM data inputs from up to 3 CODECs. I/O 3.3VSB 3.3.2.
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3.3.3.
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3.3.5. Serial ATA Signal Pin Description I/O SATA0_TX+ SATA0_TX- A16 A17 Serial ATA channel 0, Transmit Output differential pair. O SATA AC coupled on Module SATA0_RX+ SATA0_RX- A19 A20 Serial ATA channel 0, Receive Input differential pair. I SATA AC coupled on Module SATA1_TX+ SATA1_TX- B16 B17 Serial ATA channel 1, Transmit Output differential pair. O SATA AC coupled on Module SATA1_RX+ SATA1_RX- B19 B20 Serial ATA channel 1, Receive Input differential pair.
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3.3.6. PCI Express Signal Pin Description I/O PCIE_TX0+ PCIE_TX0- A68 A69 PCI Express channel 0, Transmit Output differential pair. O PCIE AC coupled on Module PCIE_RX0+ PCIE_RX0- B68 B69 PCI Express channel 0, Receive Input differential pair. I PCIE AC coupled off Module PCIE_TX1+ PCIE_TX1- A64 A65 PCI Express channel 1, Transmit Output differential pair. O PCIE AC coupled on Module PCIE_RX1+ PCIE_RX1- B64 B65 PCI Express channel 1, Receive Input differential pair.
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3.3.8. LPC bus Signal Pin Description I/O LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V LPC_DRQ0# LPC_DRQ1# B8 B9 LPC serial DMA request I 3.3V LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V LPC_CLK B10 LPC clock output - 33MHz nominal O 3.3V 3.3.9. PU/PD Comment PU 8k2 3.3V USB Signal Pin Description I/O USB0+ USB0- A46 A45 USB differential data pairs for Port 0 I/O 3.
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3.3.10. SPI (BIOS only) Signal Pin Description I/O PU/PD Comment SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V.
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3.3.12. SMBus Signal Pin Description I/O PU/PD SMB_CK B13 System Management Bus bidirectional clock line. Power sourced through 5V standby rail and main power rails. I/O OD 3.3VSB PU 2k2 3.3VSB SMB_DAT# B14 System Management Bus bidirectional data line. Power sourced through 5V standby rail and main power rails. I/O OD 3.3VSB PU 2k2 3.3VSB SMB_ALERT# B15 System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system.
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3.3.15. Power And System Management Signal Pin Description I/O PU/PD PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge. I 3.3VSB PU 10k 3.3VSB SYS_RESET# B49 Reset button input. Active low request for module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is unable to reestablish control of the system, PWR_OK or a power cycle may be used. I 3.3VSB PU 10k 3.3VSB CB_RESET# B50 Reset output from module to Carrier Board.
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3.3.16. Power and Ground Signal Pin Description I/O VCC_12V A104-A109 Primary power input: +12V nominal (5 ~ 19V). See section 7 “Electrical Specifications“ for allowable input range. All available VCC_12V pins on the connector(s) shall be used. P B104-B109 VCC_5V_SBY B84-B87 Standby power input: +5.0V nominal. See section 7 “Electrical P Specifications“ for allowable input range. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used.
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3.4. CD Signal Descriptions 3.4.1. PATA IDE Signal Pin Description IDE_D0 IDE_D1 IDE_D2 IDE_D3 IDE_D4 IDE_D5 IDE_D6 IDE_D7 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15 D7 Bidirectional data to / from IDE device. C10 C8 C4 D6 D2 C3 C2 C6 C7 D3 D4 D5 C9 C12 C5 I/O 3.3V IDE_A0 D13 Address lines to IDE device. O 3.3V IDE_A1 D14 Address lines to IDE device. O 3.3V IDE_A2 D15 Address lines to IDE device. O 3.3V IDE_IOW# D9 O 3.3V IDE_IOR# C14 I/O read line to IDE device.
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3.4.2. PCI Signal Pin PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 C24 PCI bus multiplexed address and data lines D22 C25 D23 C26 D24 C27 D25 C28 D27 C29 D28 C30 D29 C32 D30 D37 C39 D38 C40 D39 C42 D40 C43 D42 C45 D43 C46 D44 C47 D45 C48 I/O 3.
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Signal Pin PCI_LOCK# I/O PU/PD C35 PCI Lock control line, active low. I/O 3.3V PU 8k2 3.3V PCI_SERR# D33 System Error: SERR# may be pulsed active by any PCI device that detects a system error condition. I/O 3.3V PU 8k2 3.3V PCI_PME# C15 PCI Power Management Event: PCI peripherals drive PME# to wake system from low-power states S1–S5. I 3.3VSB PCI_CLKRUN# D48 Bidirectional pin used to support PCI clock run protocol for mobile systems. I/O 3.3V PU 10k 3.
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3.4.3.
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Signal Pin PEG_TX14PEG_TX15+ PEG_TX15- D99 D101 D102 Description I/O PEG_LANE_RV# PEG_ENABLE# PU/PD Comment D54 PCI Express Graphics lane reversal input strap. Pull low on the Carrier board to reverse lane order. I 1.05V D97 Strap to enable PCI Express x16 external graphics interface. Pull low to enable the x16 interface. I 3.3V PU 10k 3.3V Connect to switch SDVO / PEG Signal Pin Description I/O SDVOB_RED+ SDVOB_RED- D52 D53 Serial Digital Video B red output differential pair.
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3.4.4. Module Type Definition Signal Pin Description I/O TYPE0# TYPE1# TYPE2# C54 C57 D57 The TYPE pins indicate to the Carrier Board the Pin-out Type which is implemented on the module. The pins are tied on the module to either ground (GND) or are noconnects (NC). For Pinout Type 1, these pins are undefined (X).
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4. Module Configuration 4.1. PCI Express Configuration Switch (SW1) Switch SW1 allows you to configure the PCI Express x16 lanes from the CPU as 1 PCIe x16, 2 PCIe x8, or 1 PCIe x8 + 2 PCIe x4. Mode Pin 1 Pin 2 1 PCIe x8 + 2 PCIe x4 On On Reserved On Off 2 x8 PCI Express Off On 1 x16 PCI Express (Default) Off Off 4.2.
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5. System Resources 5.1.
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5.3.
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5.4.
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APIC Mode IRQ# Typical Intterupt Resource Connected to Pin Available 0 Counter 0 N/A No 1 Keyboard controller N/A No 2 Cascade interrupt from slave PIC N/A No 3 Serial Port 2 (COM2) / PCI IRQ3 via SERIRQ / PIRQ Note (1) 4 Serial Port 1 (COM1) / PCI IRQ4 via SERIRQ / PIRQ Note (1) 5 Generic IRQ5 via SERIRQ / PIRQ Note (1) 6 Floppy Drive Controller IRQ6 via SERIRQ / PIRQ No 7 Generic IRQ7 via SERIRQ / PIRQ Note (1) 8 Real-time clock N/A No 9 Generic IRQ9 via SERIRQ /
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5.5.
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5.6. PCI Interrupt Routing Map INT Line LPC Interface Bridge XHCI Controller EHCI Controller #0 EHCI Controller #1 HD Audio GbE Controller Int0 INTF:21 INTA:16 INTH:23 INTA:16 INTG:22 INTE:20 Int1 INTD:19 Int2 INTC:18 Int3 INTA:16 INT Line Managem ent Engine PCIE Root Port#0 PCIE Root Port#1 PCIE Root Port#2 PCIE Root Port#3 PCIE Root Port#4 Marvell IDE controller TI PCI to I.G.F.
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6. BIOS Setup The following chapter describes basic navigation for the AMIBIOS®EFI BIOS setup utility. 6.1. Starting the BIOS To enter the setup screen, follow these steps: 1. Power on the motherboard 2. Press the < Delete > key on your keyboard when you see the following text prompt: < Press DEL to run Setup > 3. After you press the < Delete > key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu, such as Chipset and Power menus.
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6.1.1. Setup Menu The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user’s guide. The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. “Grayed” options cannot be configured, “Blue” options can be. The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white.
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6.1.2. Navigation The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process. These keys include < F1 >, < F10 >, < Enter >, < ESC >, < Arrow > keys, and so on. There is a hot key legend located in the right frame on most setup screens. →← ↑↓ +Tab Page 42 Left/Right. The Left and Right < Arrow > keys allow you to select a setup screen.
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Hot Key Description Enter The < Enter > key allows you to display or change the setup option listed for a particular setup item. The < Enter > key can also allow you to display the setup sub-screens. F1 The < F1 > key allows you to display the General Help screen. Press the < F1 > key to open the General Help screen. F2 The < F2 > key on your keyboard is the previous values key. It is not displayed on the key legend by default.
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F4 ESC The < F4 > key allows you to save any changes you have made and exit Setup. Press the < F4 > key to save your changes. The following screen will appear: Press the < Enter > key to save the configuration and exit. You can also use the < Arrow > key to select Cancel and then press the < Enter > key to abort this function and return to the previous screen. The < Esc > key allows you to discard any changes you have made and exit the Setup.
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6.2.
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6.2.1. System Management Power-Up Mode Turn On:The machine starts automatically when the power supply is turned on. Remain Off: To start the machine the power button has to be pressed. Last State:The machine will return to the last state on power up. ECO Mode Reduces the power consumption of the system.
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Power-Up Watchdog The Power-Up Watchdog resets the system after a certain amount of time after power-up. System & Board Info The Main BIOS setup screen reports board information. ¾ Project Version Displays the current BIOS version. ¾ Build Data Displays the BIOS build data. System Date/System Time Use this option to change the system time and date. Highlight System Time or System Date using the < Arrow > keys. Enter new values using the keyboard.
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6.3. Advanced Setup LVDS Backlight Mode Configure LVDS Backlight to GTT or BMC Mode. 6.3.1.
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Emulation AT/ATX Select Emulation AT or ATX function.If this option set to [Emulation AT], BIOS will report no suspend functions to ACPI OS. In Windows XP, it will make the OS show a shutdown message during system shutdown. 6.3.2. Trusted Computing Security Device Support Enables or Disables BIOS support for security device. OS will not show Security Device.TCG EFI protocol and INT1A interface will not be available.
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6.3.3. CPU Configuration Hyper-threading Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for HyperThreading Technology). When disabled, only one thread per enabled core is enabled. Limit CPUID Maximum Disabled for Windows XP. Execute Disable Bit XD can prevent certain classes of malicious buffer overflow attacks when combined with a supporting OS (Windows Server 2003 SP1, Windows XP SP2, SuSE Linux 9.
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6.3.4. SATA Configuration SATA Controller(s) Enables or disable SATA Device. SATA Mode Selection Determines how SATA controller(s) operate. 6.3.5.
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Platform Thermal Configuration Critical Trip Point This value controls the temperature of the ACPI Critical Trip Point - the point at which the OS will shut the system off. NOTE: 100°C is the Plan of Record (POR) for all Intel mobile processors. Active Cooling Trip Point Default Active Cooling Trip Point 15 C. Passive Trip Point This value controls the temperature of the ACPI Passive Trip Point - the point in which the OS will begin throttling the processor.
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6.3.6. Intel TXT(LT) Configuration 6.3.7. PCH-FW Configuration MDES BIOS Status Code Enable/Disable MDES BIOS Status Code. Firmware Update Configuration Configure Management Engine Technology Parameters.
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6.3.8. Intel Anti-Theft Technology Configuration Intel(R) Anti-Theft Technology Enable/Disable Intel(R) AT in BIOS for testing only. Intel(R) Anti-Theft Technology Rec 3 Set the number of times Recovery attemped will be allowed.
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6.3.9. AMT Configuration Intel AMT Enable/Disable Intel Active Management Technology BIOS Extension. Note: iAMT H/W is always enabled. This option just controls the BIOS extension execution. If enabled, this requires additional firmware in the SPI device BIOS Hotkey Pressed OEMFlag Bit 1: Enable/Disable BIOS hotkey press. MEBx Selection Screen OEMFlag Bit 2: Enable/Disable MEBX selection screen.
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PET Progress User can Enable/Disable PET Events progress to receive PET event or not. WatchDog Enable/Disable WatchDog Timer. 6.3.10. USB Configuration Legacy USB Support Enables Legacy USB support. AUTO option, disables legacy support if no USB devices are connected. DISABLE option will keep USB devices available only for EFI applications. EHCI Hand-off This is a workaround for OSes without EHCI hand-off support. The EHCI ownership change should be claimed by EHCI driver.
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6.3.11.
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6.3.12. Serial Port Console Redirection Console Redirection Console Redirection Enable or Disable. Console Redirection Setttings The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.
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6.3.13. CPU PPM Configuration EIST Enable/Disable Intel SpeedStep Turbo Mode Turbo Mode.
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6.4. Chipset Setup 6.4.1.
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PCI Express Configuration PCI Express Clock Gat Enable or disable PCI Express Clock Gating for each root port. DMI Link ASPM Control The control of Active State Power Management on both NB side and SB side of the DMI Link. DMI Link Etended Syn The control of Extended Synch on SB side of the DMI Link. PCIe-USB Glitch W/A PCIe-USB Glitch W/A for bad USB device(s) connected behind PCIE/PEG Port.
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USB Configuration EHCI1/2 Control the USB EHCI (USB 2.0) functions. One EHCI controller must always be enabled. USB Ports Per-Port Disable Control each of the USB ports (0~13) disabling. PCH Azalia Configuration Azalia Control Detection of the Azalia device. Disabled = Azalia will be unconditionally disabled. Enabled = Azalia will be unconditionally Enabled. Auto = Azalia will be enabled if present, disabled otherwise.
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Azalia Docking Support Enable or disable Azalia Docking Support of Audio Controller. Azalia PME Enable or disable Power Management capability of Audio Controller. Azalia Internal HDMI Codec Enable or disable internal HDMI codec for Azalia. BIOS Security Configuration SMI Lock Enable or disable SMI lockdown. BIOS Lock Enable or disable BIOS lock enable (BLE) bit. GPIO Lock Enable or disable GPIO lockdown. BIOS Interface Lock Enable or disable BIOS Interface lockdown.
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6.4.2. System Agent (SA) Configuration Graphics Configuration Graphics Turbo IMON Current Graphics turbo IMON current values supported (14-31) Primary Display Select which of IGFX/PEG/PCI Graphics device should be Primary Display, or select SG for Switchable Gfx. Internal Graphics Keep IGD enabled based on the setup options.
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GTT Size Select the GTT Size Aperture Size Select the Aperture Size DVMT Pre-Allocated Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device. DVMT Total Gfx Mem Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device. Gfx Low Power Mode This option is applicable for SFF only. Graphics Performance Enable or disable Intel Graphics Performance Analyzers Counters.
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Backlight Control Back Light Control Setting GTT LVDS Backlight Control GTT LVDS Backlight Control. Note: This setting will be reset by the Graphics Driver. DDI function choose DDI function set to Display Port or HDMI. BIA Auto: GMCH use VBT default. Level n: Enabled with selected aggressiveness level. Spread Spectrum clock Hardware: Spread is controlled by chip. Software: Spread is controlled by BIOS. ALS Support Valid only for ACPI. Legacy = ALS Support through the IGD INT10 function.
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Enable PEG Enable or disable the PEG. PEG Link Disabled Enable or disable PCIe link disable mechanism for additional power saving. Fast PEG Init Enable or disable Fast PEG Init, Some optimization if no PEG devices present in cold boot. RxCEM Loop back Enable or disable RxCEM Loop back. PCIe Gen3 RxCTLEp Set The range of the setting is (0~15) This setting has to be specified based on platform design and following the guideline.
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Memory Configuration DIMM profile Select DIMM timing profile that should be used. Memory Frequency Limiter Maximum Memory Frequency Selections in MHz. ECC Support Enable or disable DDR ECC Support. Max TOLUD Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic controller. NMode Support NMode support option. Memory Scrambler Enable or disable Memory Scrambler support. MRC Fast Boot Enable or disable MRC fast boot.
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DIMM Exit Mode DIMM Exit Mode control Power Down Mode Power Down Mode control. Scrambler Seed Generation off Control Memory Scrambler Seed Generation. Enable - do not generate scrambler seed. Disable - Generate scrambler seed always. Memory Remap Enable or disable memory remap above 4G. Memory Alias Check Enable or disable memory Alias Check. Channel A DIMM Control Enable or disable DIMMs on Channel A. Channel B DIMM Control Enable or disable DIMMs on Channel B.
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6.5. Boot Setup Setup Prompt Timeout Number of seconds to wait for setup activation key. 65535 (0xFFFF) means indefinite waiting. Bootup Numlock State Select the keyboard NumLock state Quiet Boot Enable or disables Quiet Boot option Fast Boot Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot options. GateA20 Active Upon Request - GA20 can be disabled using BIOS services.
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6.6.
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6.7. Save & Exit Menu Save Changes and Exit Exit system setup after saving the changes. Discard Changes and Exit Exit system setup without saving any changes. Save changes and Reset Reset the system after saving the changes. Discard changes and Reset Reset system setup without saving any changes. Save changes Save Changes done so far to any of the setup options. Discard Changes Discard Changes done so far to any of the setup options. Restore Defaults Restore/Load Default values for all the setup options.
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7. BIOS Checkpoints, Beep Codes This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions. Checkpoints and Beep Codes Definition A checkpoint is either a byte or word value output to I/O port 80h.
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7.1. Status Code Ranges Status Code Range Description 0x01 – 0x0F SEC Status Codes & Errors 0x10 – 0x2F PEI execution up to and including memory detection 0x30 – 0x4F PEI execution after memory detection 0x50 – 0x5F PEI errors 0x60 – 0xCF DXE execution up to BDS 0xD0 – 0xDF DXE errors 0xE0 – 0xE8 S3 Resume (PEI) 0xE9 – 0xEF S3 Resume errors (PEI) 0xF0 – 0xF8 Recovery (PEI) 0xF9 – 0xFF Recovery errors (PEI) 7.2. Standard Status Codes 7.2.1.
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7.2.2. SEC Beep Codes None 7.2.3.
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Status Code Description 0x4F DXE IPL is started PEI Error Codes 0x50 Memory initialization error. Invalid memory type or incompatible memory speed 0x51 Memory initialization error. SPD reading has failed 0x52 Memory initialization error. Invalid memory size or memory modules do not match. 0x53 Memory initialization error. No usable memory detected 0x54 Unspecified memory initialization error.
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7.2.4. PEI Beep Codes # of Beeps Description 1 Memory not Installed 1 Memory was installed twice (InstallPeiMemory routine in PEI Core called twice) 2 Recovery started 3 DXEIPL was not found 3 DXE Core Firmware Volume was not found 7 Reset PPI is not available 4 Recovery failed 4 S3 Resume failed 7.2.5.
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Status Code Description 0x77 South Bridge DXE Initialization (South Bridge module specific) 0x78 ACPI module initialization 0x79 CSM initialization 0x7A – 0x7F Reserved for future AMI DXE codes 0x80 – 0x8F OEM DXE initialization codes 0x90 Boot Device Selection (BDS) phase is started 0x91 Driver connecting is started 0x92 PCI Bus initialization is started 0x93 PCI Bus Hot Plug Controller Initialization 0x94 PCI Bus Enumeration 0x95 PCI Bus Request Resources 0x96 PCI Bus Assign Resou
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Status Code Description 0xAF Exit Boot Services event 0xB0 Runtime Set Virtual Address MAP Begin 0xB1 Runtime Set Virtual Address MAP End 0xB2 Legacy Option ROM Initialization 0xB3 System Reset 0xB4 USB hot plug 0xB5 PCI bus hot plug 0xB6 Clean-up of NVRAM 0xB7 Configuration Reset (reset of NVRAM settings) 0xB8 – 0xBF Reserved for future AMI codes 0xC0 – 0xCF OEM BDS initialization codes DXE Error Codes 0xD0 CPU initialization error 0xD1 North Bridge initialization error 0xD2 So
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7.2.7. ACPI/ASL Checkpoint Status Code Description 0x01 System is entering S1 sleep state 0x02 System is entering S2 sleep state 0x03 System is entering S3 sleep state 0x04 System is entering S4 sleep state 0x05 System is entering S5 sleep state 0x10 System is waking up from the S1 sleep state 0x20 System is waking up from the S2 sleep state 0x30 System is waking up from the S3 sleep state 0x40 System is waking up from the S4 sleep state 0xAC System has transitioned into ACPI mode.
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Safety Instructions Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use. • Please read these safety instructions carefully. • Please keep this User‘s Manual for later reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment.
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Getting Service ADLINK Technology, Inc. Address: Tel: Fax: Email: 9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan +886-2-8226-5877 +886-2-8226-5717 service@adlinktech.com Ampro ADLINK Technology, Inc. Address: Tel: Toll Free: Fax: Email: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA +1-408-360-0200 +1-800-966-5200 (USA only) +1-408-360-0222 info@adlinktech.com ADLINK Technology (China) Co., Ltd. Address: Tel: Fax: Email: 300 Fang Chun Rd.
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ADLINK Technology, Inc. (French Liaison Office) Address: 6 allée de Londres, Immeuble Ceylan 91940 Les Ulis, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com ADLINK Technology Japan Corporation Address: KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho, Chiyoda-ku Tokyo 101-0045, Japan Tel: +81-3-4455-3722 Fax: +81-3-5209-6013 Email: japan@adlinktech.com ADLINK Technology, Inc.