NuDAQ® PCI-7442/7443/7444 128-CH/64-CH Isolated Digital I/O Cards User’s Manual Manual Rev. 2.50 Revision Date: May 7, 2013 Part No: 50-11218-2010 Advance Technologies; Automate the World.
Revision History Revision Release Date Description of Change(s) 2.01 2007/03/12 Initial Release 2.50 2013/05/07 Updated Package Contents Copyright 2013 ADLINK TECHNOLOGY INC. All Rights Reserved. The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.
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Using this manual 1.1 Audience and scope This manual guides you when using ADLINK NuDAQ® digital input/output PCI cards. The card’s hardware and register information are provided for faster application building. This manual is intended for computer programmers and hardware engineers with advanced knowledge of data acquisition and high-level programming. 1.
1.3 Conventions Take note of the following conventions used throughout the manual to make sure that you perform certain tasks and instructions properly. NOTE Additional information, aids, and tips that help you perform particular tasks. IMPORTANT Critical information and instructions that you MUST perform to complete a task. WARNING Information that prevents physical injury, data loss, module damage, program corruption etc. when trying to complete a particular task.
List of Tables.......................................................................... iii List of Figures ........................................................................ iv 1 Introduction ........................................................................ 1 1.1 1.2 1.3 1.4 1.5 Features............................................................................... 2 Applications ......................................................................... 2 Specifications.......................
4 Register Format ................................................................ 33 4.1 4.2 4.3 4.4 PCI-7442 I/O Registers...................................................... 33 Isolated Digital Input Register ....................................... 33 COS Interrupt Control Registers ................................... 34 Interrupt Status, COS INT Control Read Back Registers 36 COS Setup/Latch Registers .......................................... 37 TTL IO Setup, Status, DO and DI Registers .........
List of Tables Table 2-1: TTL/IO (JP3) Connector Pin Assignments ............. 25 Table 2-2: TTL/IO (JP4) Connector Pin Assignments ............. 25 Table 2-3: Board ID Settings ...................................................
iv List of Tables
List of Figures Figure 2-1: Figure 2-2: Figure 2-3: Figure 2-4: Figure 2-5: Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: iv PCI-7442 Layout........................................................ 9 PCI-7443 Layout...................................................... 10 PCI-7444 Layout...................................................... 11 PCI-7440 Series Card Bracket ................................ 12 PCI-7440 Series Connector Pin Reference ............. 12 Photo Coupler............................
v List of Figures
1 Introduction The ADLINK PCI-7442, PCI-7443, and PCI-7444 cards are highdensity isolated digital I/O cards featuring 128 or 64 channels of digital input, 128 or 64 channels of digital output, and up to 32 TTL channels for a wide range of PCI bus-based industrial applications.
1.1 Features Refer to the comparison table below for the card series features. Features PCI-7442 PCI-7443 PCI-7444 32-bit 3.
1.3 Specifications Optical isolated digital input (PCI-7442/PCI-7443 only) Input channels 64 (PCI-7442) 128 (PCI-7443) (Note: Use an efficient cooling system and pay particular attention to the card and chassis temperature when using the digital input channels.) Input voltage High: 5 V – 28 V, non-polarity Low: 0 V – 1.5 V, non-polarity Input resistance 4.
Safety functions (PCI-7442/PCI-7444 only) • Programmable power-up DO initial status • Programmable safety DO status function even during WDT interruption • Digital output value retention after hot system reset General specifications Dimensions 174.7 mm (L) x 106.
1.4 Unpacking Checklist Before unpacking, check the shipping carton for any damage. If the shipping carton and/or contents are damaged, inform your dealer immediately. Retain the shipping carton and packing materials for inspection. Obtain authorization from your dealer before returning any product to ADLINK. Check if the following items are included in the package.
1.5 Software Support ADLINK provides versatile software drivers and packages to address different approaches in building a system. Aside from programming libraries such as DLLs for many Windows® -based systems, ADLINK also provides drivers for other software packages including LabVIEW®. All software options may be found in the ADLINK All-in-One CD.
DAQBenchTM: ActiveX Controls It is recommended for programmers familiar with ActiveX controls and VB/VC++ programming to use the DAQBench™ ActiveX Control component library for developing applications. The DAQBench™ is designed under Windows® NT/98 environment. For more information about DAQBench™, refer to the user’s guide in the All-in-One CD.
8 Introduction
2 Hardware Information This chapter provides information on the PCI-7442/7443/7444 card layout, connectors, and pin assignments. 2.1 Card Layout Figure 2-1 shows the location of the PCI-7442 connectors, switch, and jumpers.
Figure 2-2 shows the location of the PCI-7443 connectors and DIP switch.
Figure 2-3 shows the location of the PCI-7444 connectors and DIP switch.
Bracket Layout CN2B CN2A CN1B CN1A Figure 2-4: PCI-7440 Series Card Bracket Connector Pin Reference Terminal B68 Terminal B34 Terminal B68 Terminal B34 Terminal A1 Terminal A35 Terminal A1 Terminal A35 CN2B Terminal B35 Terminal B1 CN2A Terminal A68 Terminal A34 CN1B CN1A Terminal B35 Terminal B1 Terminal A68 Terminal A34 Figure 2-5: PCI-7440 Series Connector Pin Reference 12 Hardware Information
2.
Pin Definition Pin 14 Definition IDO_n Isolated digital output channel n VDD1 common VDD junction for input channel 0-7 VDD2 common VDD junction for input channel 8-15 VDD3 common VDD junction for input channel 16-23 VDD4 common VDD junction for input channel 24-31 VDD5 common VDD junction for input channel 32-39 VDD6 common VDD junction for input channel 40-47 VDD7 common VDD junction for input channel 48-55 VDD8 common VDD junction for input channel 56-63 IGND Ground return path for
CN1 Connector CN1B CN1A N/C B68 B34 N/C IDI_0 A1 A35 IDI_8 COM8 B67 B33 COM7 IDI_1 A2 A36 IDI_9 COM8 B66 B32 COM7 IDI_2 A3 A37 IDI_10 COM8 B65 B31 COM7 IDI_3 A4 A38 IDI_11 COM8 B64 B30 COM7 IDI_4 A5 A39 IDI_12 COM8 B63 B29 COM7 IDI_5 A6 A40 IDI_13 COM8 B62 B28 COM7 IDI_6 A7 A41 IDI_14 COM8 B61 B27 COM7 IDI_7 A8 A42 IDI_15 COM8 B60 B26 COM7 COM1 A9 A43 COM2 IDI_63 B59 B25 IDI_55 COM1 A10 A44 COM2 IDI_62 B58 B24 IDI_54 COM1
Pin Definition Pin IDI_n Isolated digital input channel n COM1 common junction for input channel 0-7 COM2 common junction for input channel 8-15 COM3 common junction for input channel 16-23 COM4 common junction for input channel 24-31 COM5 common junction for input channel 32-39 COM6 common junction for input channel 40-47 COM7 common junction for input channel 48-55 COM8 common junction for input channel 56-63 N/C 16 Definition No Connect Hardware Information
2.
Pin Definition Pin IDI_n Isolated digital input channel n COM9 common junction for input channel 64-71 COM10 common junction for input channel 72-79 COM11 common junction for input channel 80-87 COM12 common junction for input channel 88-95 COM13 common junction for input channel 96-103 COM14 common junction for input channel 104-111 COM15 common junction for input channel 112-119 COM16 common junction for input channel 120-127 N/C 18 Definition No Connect Hardware Information
CN1 Connector CN1B CN1A N/C B68 B34 N/C IDI_0 A1 A35 IDI_8 COM8 B67 B33 COM7 IDI_1 A2 A36 IDI_9 COM8 B66 B32 COM7 IDI_2 A3 A37 IDI_10 COM8 B65 B31 COM7 IDI_3 A4 A38 IDI_11 COM8 B64 B30 COM7 IDI_4 A5 A39 IDI_12 COM8 B63 B29 COM7 IDI_5 A6 A40 IDI_13 COM8 B62 B28 COM7 IDI_6 A7 A41 IDI_14 COM8 B61 B27 COM7 IDI_7 A8 A42 IDI_15 COM8 B60 B26 COM7 COM1 A9 A43 COM2 IDI_63 B59 B25 IDI_55 COM1 A10 A44 COM2 IDI_62 B58 B24 IDI_54 COM1
Pin Definition Pin IDI_n Isolated digital input channel n COM1 common junction for input channel 0-7 COM2 common junction for input channel 8-15 COM3 common junction for input channel 16-23 COM4 common junction for input channel 24-31 COM5 common junction for input channel 32-39 COM6 common junction for input channel 40-47 COM7 common junction for input channel 48-55 COM8 common junction for input channel 56-63 N/C 20 Definition No Connect Hardware Information
2.
Pin Definition Pin IDO_n Isolated digital output channel n VDD9 common VDD junction for input channel 64-71 VDD10 common VDD junction for input channel 72-79 VDD11 common VDD junction for input channel 80-87 VDD12 common VDD junction for input channel 88-95 VDD13 common VDD junction for input channel 96-103 VDD14 common VDD junction for input channel 104-111 VDD15 common VDD junction for input channel 112-119 VDD16 22 Definition common VDD junction for input channel 120-127 IGND Ground
CN1 Connector CN1B CN1A N/C B68 B34 N/C IDO_0 A1 A35 IDO_8 IGND B67 B33 IGND IDO_1 A2 A36 IDO_9 IGND B66 B32 IGND IDO_2 A3 A37 IDO_10 IGND B65 B31 IGND IDO_3 A4 A38 IDO_11 IGND B64 B30 IGND IDO_4 A5 A39 IDO_12 IGND B63 B29 IGND IDO_5 A6 A40 IDO_13 IGND B62 B28 IGND IDO_6 A7 A41 IDO_14 IGND B61 B27 IGND IDO_7 A8 A42 IDO_15 VDD8 B60 B26 VDD7 VDD1 A9 A43 VDD2 IDO_63 B59 B25 IDO_55 IGND A10 A44 IGND IDO_62 B58 B24 IDO_54 IGND
Pin Definition Pin IDO_n Isolated digital output channel n VDD1 common VDD junction for input channel 0-7 VDD2 common VDD junction for input channel 8-15 VDD3 common VDD junction for input channel 16-23 VDD4 common VDD junction for input channel 24-31 VDD5 common VDD junction for input channel 32-39 VDD6 common VDD junction for input channel 40-47 VDD7 common VDD junction for input channel 48-55 VDD8 common VDD junction for input channel 56-63 IGND Ground return path for isolated output c
2.
2.6 Board ID (S1) The Board ID feature helps you identify the modules when two or more PCI-7440 Series cards are installed in one system. According to a DIP switch configuration located in the S1, you can assign a specific board ID to a designated card and access it correctly through simple software programming. The table below shows all the switch settings. 1 means DIP is at ON position; 0 means that the DIP is OFF. Board ID Note: 1 = ON, 0 = OFF Default setting is 1111 or Board ID = 0 Switch No.
3 Operation theory 3.1 Isolated digital input The PCI-7442/7443 card comes with 64/128 opto-isolated digital input channels. The circuit diagram of the isolated input channel is shown in Figure 3-1. Figure 3-1: Photo Coupler The digital input is routed first through a photo-coupler (PC3H4) so that the connection are not polarly sensitive whether using positive or negative voltage. The normal input voltage range for high state is from 5 V to 28 V.
3.2 Change of State (COS) interrupt Overview The COS (Change of State) means either the input state (logic level) changes from low to high, or from high to low. The COS detection circuit will detect the edge of level change. In the PCI7442/7443 card, the COS detection circuit is applied to all the input channels. When any channel changes its logic level, the COS detection circuit generates an interrupt request to PCI controller. COS detection Figure 3-2 is an example of an 8-CH COS operation.
COS detection architecture The COS interrupt system is used in PCI-7442/7443. COS interrupt occurs when the any of enabled DI line sense the status changes either from HIGH to LOW or from LOW to HIGH. The COS interrupt system can generate an interrupt request signal and the software can service this request with ISR.
3.3 Isolated digital output channels The common ground connection of isolated digital output is shown in the figure below. When the isolated digital output goes ON, the sink current will be conducted through the power MOSFETs. When the isolated digital output goes OFF, no current is conducted to flow through the power MOSFETS. Take note that when the load is of an inductance nature such as a relay, coil or motor, the VDD pin must be connected to an external power source.
3.4 Watchdog timer (WDT) In safety-critical applications, you can enable the watchdog timer (WDT) function to automatically generate an interrupt signal, in case the operating system or the PCI-7442/PCI-7444 card crashes. To access this function, you must first configure the watchdog timer overflow counter by windows API. Generally, the trigger source would come from the onboard 32-bit watchdog timer. The WDT overflow interval can be programmed through API.
32 Operation theory
4 Register Format This chapter provides the detailed descriptions of the register formats intended for programmers who want to operate the card series through low-level programming. This chapter is intended for users that have basic understanding of the PCI interface. The PCI-7442/7443/7444 card registers are all 16-bit wide and can only be accessed using 16-bit I/O instructions. The isolated digital input/output control is by accessing registers mentioned in this chapter. 4.
COS Interrupt Control Registers There are two different interrupt modes in PCI-7442. Both interrupt modes are disabled by default. You can write the registers listed below to enable the interrupt. In the first mode, users enable the COS (Change of State) interrupt function to monitor the status of enabled input channels and whenever the status change from 0 to 1 or 1 to 0. In the second mode, you can enable the Watchdog Timer (WDT) Counter. The interrupt asserts when the WDT Counter counts to zero.
Address: BASE+0x46h Reset Value: 0x0000h Read/Write: W -- -- -- -- -- -- -- Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 -- -- -- -- -- -- -- EA1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit15 - 9 Not used Bit7 - 1 Not used Bit0 CLR1: COS 1 interrupt clear Bit8 EA1: COS 1 interrupt enable/disable CLR1 1: Clear; 0: No effect 1: Enabled; 0: Disabled Register Format 35
Interrupt Status, COS INT Control Read Back Registers When any COS interrupts occur, these registers provide information for you to recognize the interrupt status and the interrupt setup condition read back.
COS Setup/Latch Registers The PCI-7442 provides a Change of State (COS) interrupt function on any one of digital input channel. This function allows you to monitor the status of digital input channels by setting these registers. By enabling the COS Setup registers, it will generate an interrupt when the corresponding channel changes its state. Address R/W Value Mapping (MSB----LSB) BASE+0x08h W IDI_COS_EN[15…0] BASE+0x0Ah W IDI_COS_EN[31...16] BASE+0x48h W IDI_COS_EN[47...32] W IDI_COS_EN[63...
TTL IO Setup, Status, DO and DI Registers The PCI-7442 provides an extra 32-channel TTL I/O function for optional applications. These TTL I/O channels are divided among two 16-bits banks and are divided between two connectors: JP3 and JP4. You may choose the direction of each TTL channel any time by setting up the two-bank TTL IO setup register. Address R/W Value Mapping (MSB----LSB) BASE+0x0Ch W TTL_IO_SETUP[15…0] W TTL_IO_SETUP[31..16] BASE+0x4Ch Bit value: 0: I/O direction is input (default).
When the I/O direction setting is input, you can read data through the TTL I/O input channel. Address R/W BASE+0x0Eh R TTL_IO_DI[15…0] BASE+0x4Eh R TTL_IO_DI[31...16] Bit value: Value Mapping (MSB----LSB) 0: Input is low. 1: Input is high.
Isolated Digital Output and Read Back Registers There are 64 isolated digital outputs on each PCI-7442 board. These lines are divided between two output connectors: CN2A and CN2B. These are controlled by four 16-bit registers in bank2. Each digital output line is controlled by each bit of the four control registers. You must send out the corresponding DO output data, then send out the start command to bank2 to complete the process. The 64-bit DO data will then be sent out at the same time.
The isolated DO statuses can be read back from the registers. When you want to read the 64-bit DO statuses, you must first send the Read Back Start command (BASE+0x80h). You can in turn read the isolated DO when DO read back procedure is ready. DO ReadBack Start does not need any register value. You only need to send out the address (BASE + 0x80h) in Read mode before reading back all 64-bit channel output data. When the back2 receives the Start command, the 64-bit DO data readback procedure proceeds.
Power-up DO Setup/Read Register When the system enters the power up status, PCI-7442 can enter the initial procedure which sends out the default initial value to 64CH digital outputs. You can configure the power-up default DO values and store them in the flash memory. With this, the DO goes to a definite status when the system turns on. You can program the 64-CH power-up default DO values by accessing the Power-up DO Setup Register in turn.
Watchdog Timer Load, Safety DO Setup/Read Back Registers The PCI-7442 provides a 32-bit watch dog timer (WDT) with 10 MHz clock. The WDT counter loads the 32-bit value of two 16-bit WDT_LOAD_CONFIG Registers in turn. The corresponding hexadecimal value you set determines the overflow time of WDT counter. The overflow time is calculated by the value that you set multiplied 100 ns. The timer interval is from 0 to 429.496 seconds.
You can read the configured the Safety DO values which are stored in the flash memory by sending out the WDTSafety DO ReadBack command (BASE+0x96h). The flash memory read procedure starts in 50 ms. The finished flag can be checked by nAction_Ready flag. After the Read Back procedure, you can read back the 64-bit WDTSafety DO Read Back registers in turn. Address R/W Value Mapping (MSB----LSB) BASE+0x96h R Read Back Start BASE+0x98h R IDO[15...0] BASE+0x9Ah R IDO[31...16] BASE+0x9Ch R IDO[47...
WDT INT Control, Hot-Reset, and Hold Control Register There are two different interrupt modes in PCI-7442: the COS INT function and the watch dog timer (WDT). You may enable the WDT counter and let it count down as a mode of intrrupt. The interrupt asserts when the watch dog timer counter counts to zero. You can control WDT enable and clear WDT INT by setting two bits (WDTE and WIC) in Bank2 WDT INT Control/Hot-Reset Hold Control Register.
1: Clear WDT interrupt 0: No effect Bit3 WSOE: WDT Safety DO Send Out Enable 1: Enabled 0: Disabled Address: BASE+0x8Ah Reset Value: 0x0000h Read/Write: R -- ARDYS SRDYS RBRDYS SOES WIS WDTES HRHES Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 -- -- -- -- -- -- -- -- Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit15 - 7 Not used Bit0 HRHES: Hot Reset Hold Enable Status 1: Enabled 0: Disabled Bit1 WDTES: WDT Interrupt Enable Status 1: Enabled 0: Disabled Bit2 WIS: WDT int
4.2 PCI-7443 I/O Registers Isolated Digital Input Registers There are 128 isolated digital inputs on the PCI-7443 card. The statuses of the 128 lines can be read from the registers listed below. Each bit corresponds to each channel. Address R/W Value Mapping (MSB----LSB) BASE+0x02h R IDI[15...0] BASE+0x04h R IDI[31...16] BASE+0x42h R IDI[47...32] BASE+0x44h R IDI[63...48] BASE+0x82h R IDI[79...64] BASE+0x84h R IDI[95...80] BASE+0xC2h R IDI[111...96] BASE+0xC4h R IDI[127...
COS Interrupt Control Registers The interrupt mode in the PCI-7443 is disabled by default. You can write the registers listed below to enable the interrupt function. In interrupt mode, you may enable the COS (Change of State) interrupt function to monitor the statuses of enabled input channels whenever the statuses change from 0 to 1 or from 1 to 0. After processing the interrupt request event, you must clear the interrupt request in order to handle another interrupt request.
Bit8 EA0: COS 0 Interrupt enable/disable 1: Enabled; 0: Disabled Address: BASE+0x46h Reset Value: 0x0000h Read/Write: W -- -- -- -- -- -- -- Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 -- -- -- -- -- -- -- EA1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit15 - 9 Not used Bit7 - 1 Not used Bit0 CLR1: COS 1 interrupt clear Bit8 EA1: COS 0 Interrupt enable/disable CLR1 1: Clear; 0: No effect 1: Enabled; 0: Disabled Address: BASE+0x86h Reset Value: 0x0000h Read/Write: W
Address: BASE+0xC6h Reset Value: 0x0000h Read/Write: W -- -- -- -- -- -- -- Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 -- -- -- -- -- -- -- EA3 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit15 - 9 CLR3 Not used Bit7 - 1 Not used Bit0 CLR3: COS 3 interrupt clear 1: Clear; 0: No effect Bit8 EA3: COS 3 interrupt enable/disable 1: Enabled; 0: Disabled 50 Register Format
Interrupt Status, COS INT Control Read Back Registers When any COS interrupt occurs, these registers provide information to recognize the interrupt status and the interrupt setup condition read back.
Address: BASE+0x46h Reset Value: 0x0000h Read/Write: R -- -- -- -- -- -- -- -- Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 COS1E -- -- -- -- -- -- -- Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit14 - 0 Not used Bit15 COS1E: COS 1 Interrupt enable status 1: Enabled 0: Disabled Address: BASE+0x86h Reset Value: 0x0000h Read/Write: R -- -- -- -- -- -- -- -- Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 COS2E -- -- -- -- -- -- -- Bit15 Bit14 Bit13 Bit12 B
COS Setup/Latch Registers The PCI-7443 provides the Change-of-State (COS) interrupt function in each digital input channel. This function allows you to monitor the status of input channels by setting these registers. By enabling the COS Setup registers, the card generates an interrupt when the corresponding channel changes its state. Address R/W Value Mapping (MSB----LSB) BASE+0x08h W IDI_COS_EN[63...0] BASE+0x0Ah W IDI_COS_EN[31...16] BASE+0x48h W IDI_COS_EN[47...
When COS occurs, the COS Latch registers also latch the DI[31..0], DI[63..32],DI[95..64], and DI[127..96] data, respectively. Once you clear the interrupt request, the COS Latch register clears automatically. Since you can read these registers to know the statuses after interrupts, these registers free the CPU from constantly polling all inputs and enable the system to handle more tasks. Address R/W Value Mapping (MSB----LSB) BASE+0x08h R IDI_COS_LATCH_DATA[15...
TTL IO Setup, Status, DO and DI Register The PCI-7443 provides an extra 32-CH TTL I/O function for optional applications. These TTL I/O channels are divided into two 16-bits banks. These channels are divided between two connectors: JP3 and JP4. You can choose the direction of each TTL channel any time by setting up the two-bank TTL IO setup register. Address R/W Value Mapping (MSB----LSB) BASE+0x0Ch W TTL_IO_SETUP[15...0] W TTL_IO_SETUP[31...16] BASE+0x4Ch Bit value: 0: I/O direction is input.
When the I/O direction setting is input , users can read data through the TTL I/O input channel. Address R/W Value Mapping (MSB----LSB) BASE+0x0Eh R TTL_IO_DI[15...] BASE+0x4Eh R TTL_IO_DI[31...16] Bit value: 0: Input in low logic. 1: Input in high logic.
4.3 PCI-7444 I/O Registers Isolated Digital Output/Read Back Registers The PCI-7444 has 128 isolated digital outputs. These lines are divided between four output connectors, CN1A, CN1B, CN2A, and CN2B. They are controlled by eight 16-bit registers. Each digital output line is controlled by each bit of the eight control registers. You must send out the corresponding DO output data and send out the start command in the end.
Port0: Isolated digital output channel range from bit0 to bit63 Port1: Isolated digital output channel range from bit64 to bit127 All Ch.: Isolated digital output channel range from bit0 to bit127 You may read the isolated DO statuses from the registers. To read the 128-bit DO statuses, you must first send the Read Back Start (All Ch., Port0, Port1) command. You can then read back isolated DO Read Back Register offset in turn if DO read back procedure is standby.
Power-up DO Setup/Read Back Register After the system powers up, the PCI-7444 can enter the initial procedure which sends out the default initial value to 128-CH digital outputs. You can configure the default power-up DO values and store them in the flash memory to prevent the DO from entering an unknown status when the system turns on. You may set the 128-CH power-up default DO values by accessing the Power-up DO Setup Registers in turn.
Address R/W Value Mapping (MSB----LSB) BASE+0x16h R Read Back Start BASE+0x18h R IDO[15...0] BASE+0x1Ah R IDO[31...16] BASE+0x1Ch R IDO[47...32] BASE+0x1Eh R IDO[63...48] BASE+0x20h R IDO[79...64] BASE+0x22h R IDO[95...80] BASE+0x24h R IDO[111...96] R IDO[127...112] BASE+0x26h Bit value: 0: Output PowerMOSFET is OFF. (Initial value) 1: Output PowerMOSFET is ON. You need not assign a register value for the Power-Up Initial DO All Ch. Status Read Back Start.
WDT Load Config, Safety DO Setup/Read Back Registers The PCI-7444 provides a 32-bit watch dog timer (WDT) with 10 MHz clock. The WDT counter loads the 32-bit value of two 16-bit WDT_LOAD_CONFIG Registers in turn. The corresponding hexadecimal value you set determines the overflow time of WDT counter. The overflow time is calculated by the value that you set multiplied 100 ns. The timer interval is from 0 to 429.496 seconds. Address R/W Value Mapping (MSB----LSB) BASE+0x36h W WDT_LOAD_CONFIG[15...
Address R/W Value Mapping (MSB----LSB) BASE + 0x26h W IDO[15…....0] BASE + 0x28h W IDO[31…..16] BASE + 0x2Ah W IDO[47…..32] BASE + 0x2Ch W IDO[63…..48] BASE + 0x2Eh W IDO[79…..64] BASE + 0x30h W IDO[95…..80] BASE + 0x32h W IDO[111….96] BASE + 0x34h W IDO[127..112] Bit value: 0: Output PowerMOSFET is OFF (Initial value). 1: Output PowerMOSFET is ON. You do not need to set any register for the WDTSafety DO ReadBack Start.
WDT INT Control / Hot-Reset Hold Control Register The PCI-7444 has the watchdog timer as interrupt mode. The WDT interrupt mode is disabled by default. In this mode, you can enable the WDT to count down. The interrupt asserts when the WDT Counter reaches to zero. You can enable the WDT and clear the WDT INT by setting two Bit (WDTE and WIC) in the WDT INT Control/Hot-Reset Hold Control Register. The PCI-7444 provides some special safety functions for industrial applications.
1: Function is enabled 0: Function is disabled Address: BASE+0x3Ah Reset Value: 0x0000h Read/Write: R -- ARDYS SRDYS RBRDYS SOES WIS WDTES HRHES Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 -- -- -- -- -- -- -- -- Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit15 - 7 Not used Bit6 ARDYS: Flash Data Read/Write Finished Status 1: Process is not finished. 0: Process is finished. Bit5 SRDYS: DO Data Sending Finishes Status 1: Process is not finished. 0: Process is finished.
TTL IO Setup, Status, DO and DI Registers The PCI-7444 provides an extra 32-CH TTL I/O function for optional applications. These TTL I/O channels are divided into two 16-bit banks. These channels are divided between two connectors: JP3 and JP4. You can choose the direction of each TTL channel any time by setting up the two-bank TTL IO setup register. Address R/W Value Mapping (MSB----LSB) BASE+0x3C W TTL_IO_SETUP[15…0] W TTL_IO_SETUP[31...16] BASE+0x3E Bit value: 0: I/O direction is input.
When the I/O direction setting is input, you can read data through the TTL I/O input channel. Address R/W BASE+0x40 R TTL_IO_DI[15…0] BASE+0x42 R TTL_IO_DI[31...16] Bit value: Value Mapping (MSB----LSB) 0: Input in low logic. 1: Input in high logic.
4.4 Handling PCI Controller Registers The PCI-7442/7443/7444 card adopts the PLX PCI-9030 PCI bus controller. You should notice some registers when you attempt to handle the card via low-level programming. The interrupt control register (INTCSR; 0x4Ch) of PCI-9030 takes charge of all interrupt information from local bus to PCI bus. When you want to develop your own interrupt function driver, both interrupt registers in PCI9030 and in the PCI-7442/7443/7444 card have to work together.
68 Register Format
Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the following carefully. 1. Before using ADLINK’s products please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form which can be downloaded from: http:// rma.adlinktech.com/policy/. 2.
3. Our repair service is not covered by ADLINK's guarantee in the following situations: X Damage caused by not following instructions in the User's Manual. X Damage caused by carelessness on the user's part during product transportation. X Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers. X Damage caused by unsuitable storage environments (i.e. high temperatures, high humidity, or volatile chemicals).
