NuDAQ PCI-9812/9810 4-CH, 20 MHz Simultaneous Analog Input Card User’s Manual Manual Rev. 3.02 Revision Date: December 2, 2008 Part No: 50-11116-2040 Advance Technologies; Automate the World.
Copyright 2008 ADLINK TECHNOLOGY INC. All Rights Reserved. Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.
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Using this manual Audience and scope This manual guides you when using ADLINK NuDAQ® multi-function PCI card. The card’s hardware, signal connections, and calibration information are provided for faster application building. This manual is intended for computer programmers and hardware engineers with advanced knowledge of data acquisition and highlevel programming.
Conventions Take note of the following conventions used throughout the manual to make sure that you perform certain tasks and instructions properly. NOTE Additional information, aids, and tips that help you perform particular tasks. IMPORTANT Critical information and instructions that you MUST perform to complete a task. WARNING Information that prevents physical injury, data loss, module damage, program corruption etc. when trying to complete a particular task.
Table of Contents List of Tables.......................................................................... iv List of Figures ......................................................................... v 1 Introduction ........................................................................ 1 1.1 1.2 1.3 1.4 1.5 Features............................................................................... 1 Applications ......................................................................... 1 Specifications......
4.2 4.3 Post Trigger Counter Register ...................................... 23 FIFO Status Register .................................................... 24 FIFO Control Register ................................................... 25 Acquisition Enable Register .......................................... 26 Clock Source Register .................................................. 27 High Level Programming ................................................... 28 Low Level Programming ...........................
W_9812_Free_DMA_Mem ........................................... 61 W_9812_Get_Sample .................................................. 62 7 Calibration......................................................................... 63 7.1 7.2 7.3 Before You Proceed .......................................................... 63 VR Assignment .................................................................. 63 A/D Calibration...................................................................
List of Tables Table 2-1: JP1 Pin Definition ................................................... Table 2-2: JP1 Pin Definition Connected to 9-pin D-type Connector ........................................... Table 2-3: Analog Input ........................................................... Table 2-4: Switches and Resistors .......................................... Table 4-1: I/O Address ............................................................. Table 4-2: Five Trigger Modes .............................
List of Figures Figure 2-1: Figure 5-1: Figure 5-2: Figure 5-3: Figure 5-4: Figure 5-5: List of Figures Location of Connectors............................................ Post-trigger Acquisition............................................ Pre-trigger Acquisition ............................................. Middle-trigger Acquisition ........................................ Delay-trigger Acquisition.......................................... Data Transfer Diagram of PCI-9812/9810...............
1 Introduction The PCI-9812/9810 is an advanced performance data acquisition card based on the 32-bit PCI bus architecture. With maximum sampling rate of up to 20 million samples per second, the PCI9812/9810 delivers continuous and high-speed streaming of A/D samples to the host memory. The high-performance design and state-of-the-art technology make these cards ideal for DSP, FFT, digital filtering, and image processing applications. 1.
1.3 Specifications Analog Input (AI) Converters B.B. ADS800 series Input Channels Four single-ended Resolution 12-bit (PCI-9812) 10-bit (PCI-9810) Over Voltage Protection Bipolar ±1 V, or ±5 V by soldering selection Maximum Sampling Rate1 20 MHz samples/second Accuracy Gain error ±1.5% at 25°C Input Impedance (soldering selectable) 50 Ω (±1 V and ±5 V) 1.25 KΩ (±5 V only) 5 MΩ (±1 V only) Dynamic Characteristic Differential Linearity Error ±0.4 LSB (Typ.) ±1.0 LSB (Max.
General Specifications Connectors 5 BNC-type, one 10-pin header Operating Temperature 0°C to 40°C Storage Temperature -20°C to 80°C Humidity 5% to 85%, non-condensing Power Consumption +5 V 2.5 A (maximum) Dimension 101 mm (H) X 173 mm (L) 1 With a single channel enabled, the maximum sampling rate is 20 MHz. With two channels enabled, the 20 MHz sampling rate may only be reached when the number of samples accessed for each channel is smaller than 16K.
1.4 Unpacking Checklist Before unpacking, check the shipping carton for any damage. If the shipping carton and/or contents are damaged, inform your dealer immediately. Retain the shipping carton and packing materials for inspection. Obtain authorization from your dealer before returning any product to ADLINK. Check if the following items are included in the package.
1.5 Software Support Software Support ADLINK provides versatile software drivers and packages to suit various user approach to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environment such as LabVIEW®, HP VEETM, DASYLabTM, InTouch™, InControl™, and ISaGRAFTMLabVIEW®. All software options are included in the ADLINK All-in-One CD. Commercial software drivers are protected with licensing codes.
PCIS-DASK/X Include device drivers and shared library for Linux. The developing environment can be Gnu C/C++ or any programming language that allows linking to a shared library. The user's guide and function reference manual of PCISDASK/X are in the CD. (\Manual_PDF\Software\PCIS-DASKX). These software drivers are shipped with the card. Refer to the Software Installation Guide for details.
DASYLab™ PRO DASYLab is an easy-to-use software package that provides easy-setup instrument functions such as FFT analysis. Contact ADLINK for DASYLab PRO support, including DASYLab and ADLINK hardware drivers.
8 Introduction
2 Hardware Information This chapter describes the PCI-9812/9810 layout, connectors, signal connection with external devices, and switch settings for various applications. 2.
2.2 Connectors The PCI-9812/9810 connects to external devices via five BNC connectors and one 10-pin dual-in-line header. Figure 2-1 shows the location of these connectors. Figure 2-1: Location of Connectors J1 Input signal of channel 0 A/D converter. J2 Input signal of channel 1 A/D converter. J3 Input signal of channel 2 A/D converter. J4 Input signal of channel 3 A/D converter. J5 Input signal of external clock 0.
JP1 Pin Definition Below is the default JP1 pin assignment.
2.3 Input Settings This section describes the characteristics and settings of the PCI9812/9810 inputs. Analog Input The PCI-9812/9810 has four analog input channels which are connected through the J1 to J4 connectors. The input impedance and input amplitude range can be changed through soldering the gap switches on the board (refer to PCI-9812/9810 layout). A solder gap switch consists of two copper pads. The switch can be turned on by soldering the copper pads.
CAUTION DO NOT leave the input connector unconnected when it is configured as high impedance input. The input connector must be connected to a low impedance signal source to provide a return path for the input bias current. Since the OPAMP has a maximum input bias current of 35 µA in the input stage, it will be placed in an abnormal environment when the input is left unconnected and will lead to saturation in the output stage.
External Clock 0 The external clock 0 (J5) is a sine wave signal that is converted to a TTL signal inside the PCI-9812/9810. This signal is AC coupled. The input impedance of external clock 0 is 50 Ω and the input level is 2 V peak-to-peak. Note that the external clock frequency is the system clock. The maximum A/D clock frequency is half of the system clock. When using the external sine clock for PCI-9812, take note that the frequency of the sine clock must be above 300 KHz.
3 Installation 3.1 Before You Proceed The PCI-9812/9810 card has electrostatic sensitive components that can be easily damaged by static electricity. The card must be handled on a grounded anti-static mat. The operator must wear an anti-static wristband, grounded at the same point as the anti-static mat. Inspect the card module carton for damages. Shipping and handling could cause damage to the module. Make sure that the card has no damage before installing.
3.3 Configuring the Card As a plug and play component, the card requests an interrupt number through its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These system parameters are determined by the installed drivers and the hardware load detected by the system. Troubleshooting If your system fails to boot or if you experience erratic operation with your PCI board in place, this is likely caused by an interrupt conflict (i.
4 Registers Descriptions of the register format and structure of the PCI-9812/ 9810 are specified in this chapter. This information is for programmers that want to handle the card using low-level programming. 4.1 I/O Port Address The PCI-9812/9810 functions as a 32-bit PCI target device to any master on the PCI bus. It supports burst transfer to memory space by using 32-bit data — where both data read and write are based on 32-bit data transfer.
ADC Channel Enable Register The PCI-9812/9810 has four analog input channels: CH0, CH1, CH2, and CH3. CH0 to CH3 may be enabled or disabled by bit 0 to bit 3 of the ADC channel enable register.
ADC Clock Divisor Register Feeding the ADC source clock to a clock frequency divider generates the ADC sampling clock. The output of the frequency divider becomes the sampling clock.
Trigger Mode Register The PCI-9812/9810 has five trigger modes: software trigger, post trigger, pre-trigger, middle trigger and delay trigger. The trigger mode register is used to specify which trigger mode is currently used. Address: BASE + 08h Attribute: write only Data Format: Bit 7 6 5 4 3 2 1 0 Base + 8 — — — — — TRGMOD2 TRGMOD1 TRGMOD0 Base + 9 — — — — — — — — Base + A — — — — — — — — Base + B — — — — — — — — TRGMOD2...0 Trigger mode.
Trigger Level Register The trigger condition of the PCI-9812/9810 includes a trigger level and a trigger slope. This register sets the trigger level and the trigger source register described in the next section, and sets the trigger slope. Address: BASE + 0ch Attribute: Write only Data Format: Bit 7 BASE+Ch 6 5 TRGLVL7 TRGLVL6 TRGLVL5 4 TRGLVL4 3 2 1 TRGLVL3 TRGLVL2 TRGLVL1 0 TRGLVL0 BASE+Dh — — — — — — — BASE+Eh — — — — — — — — BASE+Fh — — — — — — — — TRGLVL7...
Trigger Source Register The PCI-9812/9810 supports five trigger sources: CH0, CH1, CH2, CH3, and external digital trigger.
Post Trigger Counter Register The post trigger counter is a 16-bit down counter. The counter is pre-loaded with the value in the post trigger counter register and will count down on the rising edge of ADC sampling clock after the trigger condition is met. When the count reaches 0, the counter stops. The counter is used to control the delay time in delay trigger mode and to control the post trigger sampling count in middle trigger mode.
FIFO Status Register Monitors some of the PCI-9812/9810 status. Address: BASE + 18h Attribute: Read Data Format: Bit 7 6 5 4 3 BASE+18h — — ACQ TD PTCO 2 1 0 FIFOOR FIFOHF FIFOIR BASE+19h — — — — — — — — BASE+1Ah — — — — — — — — BASE+1Bh — — — — — — — — Bit 0 FIFOIR, FIFO input ready flag. 0: FIFO is not ready for input; FIFO is full. 1: FIFO is ready for input (not full). Bit 1 FIFOHF, FIFO half full flag. 0: FIFO is not half-full yet.
FIFO Control Register Controls the onboard FIFO memory. Address: BASE + 18h Attribute: Write Data Format: Bit 7 6 5 4 3 2 1 0 BASE+18h — — — — — — BASE+19h — — — — — — CLRTRG CLRFIFO — — BASE+1Ah — — — — — — — — BASE+1Bh — — — — — — — — Bit 0 CLRFIFO, clear the onboard FIFO When a “1” is written to this bit, the entire onboard FIFO is cleared. Bit 1 CLRTRG, clear trigger detection flag When a “1” is written to this bit, the trigger detection bit is cleared.
Acquisition Enable Register Enables or disables the ADC acquisition. Address: BASE + 1ch Attribute: Write only Data Format: Bit 7 6 5 4 3 2 1 0 BASE+18h — — — — — — — ACQEN BASE+19h — — — — — — — — BASE+1Ah — — — — — — — — BASE+1Bh — — — — — — — — Bit 31...1 No value Bit 0 ACQEN, acquisition enable When a “1” is written to this bit, the PCI-9812/9810 is ready to sample data. When a “0” is written, the PCI-9812/9810 is disabled.
Clock Source Register Selects the system clock source. Address: BASE + 20h Attribute: Write only Data Format: Bit 7 6 5 4 3 2 1 0 BASE+18h — — — — — BASE+19h — — — — — CLKSRC1 CLKSRC0 Freq_Sel — — — BASE+1Ah — — — — — — — — BASE+1Bh — — — — — — — — Bit 31...3 Any value Bit 2...1 CLKSRC1...0, ADC clock source Bit 0 Freq_Sel: Frequency selection.
4.2 High Level Programming The PCI-9812/9810 card can be controlled directly using highlevel Application Programming Interface (API) that bypasses the detailed register structures. The software libraries, including DOS for Borland C++ and DLL driver for Windows 95 are included in the ADLINK All-in-One CD. For further information, refer to Chapter 6. 4.3 Low Level Programming You are not required to write any hardware dependent low-level programs to operate the PCI-9812/9810 card.
5 Operation Theory The operation theorem of the PCI-9812/9810 card functions is described in this chapter. These functions include A/D conversion and digital input. This section aims to assist you in understanding, operating, and programming the PCI-9812/9810. 5.
X A/D data transfer mode In the end of an A/D conversion, the A/D data is buffered in a FIFO. The total FIFO size on PCI-9812/9810 is 32K samples. This buffer size is relative to the highest data transfer rate. The A/D data should be transferred to the computer’s memory for further processing. The cards use DMA to transfer the A/D data to host memory. Refer to section 5.5. X A/D data format To process the A/D data, programmers must be familiar with the A/D data format. Refer to section 5.6.
5.2 Signal Source Control To control the A/D signal source, the signal type, signal channel, and signal range must be determined. Signal Type The A/D signal sources of PCI-9812/9810 are single-ended (SE). Channels There are four channels for SE mode. The ADC Channel Enable Register controls the channel number. Refer to section 4.1. Signal Range and Input impedance The proper signal range is important for data acquisition.
5.3 Trigger Source Control When performing trigger acquisition in the PCI-9812/9810, the following parameters have to be specified before DMA operation starts: X Clock source. Refer to section 5.4 X Clock rate. Refer to section 5.4 X Trigger sources. Refer to next section. X Trigger level. The trigger event occurs when the trigger signal crosses the specified trigger voltage. Refer to Trigger Level Register section for the relationship between the 8-bit trigger level and the trigger voltage.
specified trigger level to a voltage that is higher than the specified trigger level. Z Negative-slope trigger The trigger event occurs the first time the trigger signal (analog input signal) changes from a voltage that is higher than the specified trigger level to a voltage that is lower than the specified trigger level.
Trigger Modes X Software-trigger acquisition This trigger mode does not require any external trigger source. The trigger event occurs when the _9812_AD_DMA_Start( ) function is called to start the operation. X Post-trigger acquisition Use post-trigger for applications where data needs to be collected after a specified trigger event. The trigger can either be an external analog trigger or digital trigger.
X Middle-trigger acquisition Use middle-trigger acquisition to collect data before and after a specified trigger event. The amount of data acquired before a trigger event occurs when using middle trigger may not equal to the specified count of data, just like the pre-trigger mode.
5.4 Clock Source Control The AD clock source determines how the board regulates the timing of conversions when acquiring multiple samples from a single-channel or from a group of multiple channels. The A/D clock sources on the PCI-9812/9810 must use a pacer clock, but not single-shot as the A/D converters are in a pipelined structure, that require eight conversion clocks to complete the conversion of digital data.
NOTE The clock divider must be an even number (2, 4, 6, 8, 10… 65534), with the minimum divider value being 2. Refer to section 6.2 to set the clock source and frequency divider. The first AD sample takes several clocks to convert because of the ADC’s pipelined architecture. Therefore, the external clock must be continuous for correct AD operation.
5.5 Data Transfer Data Transfer There are several function blocks on the PCI-9812/9810 designed to acquire AD data. Even as the maximum sampling rate is specified at up to 20 MHz, there are certain limitations due to the high total data throughput. Refer to the data transfer diagram below to understand how analog signal is converted to digital form and transferred to the host computer’s memory. The data transfer rate limitation and bottleneck are discussed in this section.
Total Data Throughput When four channels start simultaneously, the total data throughput from the AD converter to the onboard FIFO memory is: Sampling Rate x number of channels x 2 bytes/channel Therefore, the maximum total data throughput is 160 Mbytes/sec. 160MB/s = 20MHz x 4 channels x 2 bytes/channel This extremely high data rate is beyond the 32-bit/33 MHz PCI bus bandwidth. To address this two 16K words (samples) FIFO are designed to buffer the data.
Bus-mastering Data Transfer PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize the maximum PCI bandwidth. The bus-mastering controller—built into the AMCC-5933 PCI controller ASIC— controls the PCI bus when it becomes the master of the bus. Busmastering reduces the size of onboard memory and CPU loading since data is directly transferred to the computer’s memory without CPU intervention. The bus-mastering DMA provides the fastest data transfer rate on the PCI bus.
Storing data from the host memory to a hard disk or other storage devices must also be considered. The burst data rate of current HDD technology could be between 90 and 80 MB/s. However in reality, the effective bandwidth of a HDD is usually less than 10 MB/s, especially when the HDD seek time is longer. For example, if the HDD seek time is 20 ms, the FIFO is already full and the acquired data cannot be continuous. Several limitations may be due to the OS and host memory size.
5.6 Data Format The A/D data of 12-bit PCI-9812 is on the 12 MSB of the 16-bit A/ D data. The 4 LSB of the 16-bit A/D data must be truncated by software (Refer to section 6.2). The relationship between the real signal voltage and the sampled value is shown below: A/D Data (Hex) Decimal Value V (-1 V to +1 V) V (-5 V to +5 V) 7FF 0 +32752 +1.0000 +5.0000 400 0 +16384 +0.5002 +2.5010 001 0 +16 +0.0005 +0.0025 000 0 0 0.0000 0.0000 FFF 0 -16 0.0005 -0.0025 C00 0 -16384 -0.5002 -2.
The formula showing the relationship of the A/D data and the analog value is: Voltage = AD_data x (1/K) x (Gain) Where Gain and K are constants. For analog input range -1 V to 1 V, Gain=1 For analog input range -5 V to 5 V, Gain=5. For PCI-9812, K=2047x16=32752 For PCI-9810, K=511x64=32704.
44 Operation Theory
6 Function Reference This chapter describes the software library for operating the PCI9812/9810 card. Only the functions for DOS and Windows 95 DLL are described. Refer to the PCIS-DASK function reference manual in the ADLINK All-in-One CD for descriptions of DLL functions for Windows 98/NT/2000. The function prototypes and some useful constants are defined in the header files LIB directory (DOS) and INCLUDE directory (Windows 95). For Windows 95 DLL, the developing environment can be Visual Basic 4.
6.2 Programming Guide Naming Convention The functions of NuDAQ and NuIPC PCI/CompactPCI cards’ software driver use the following naming convention rules: In DOS: _{hardware_model}_{action_name} For example: _9812_Initial() All functions in the PCI-9812 driver uses 9812 as {hardware_model}. However, these may also be used by PCI9810. To differentiate the DOS from Windows 95 libraries, a capital W is placed in the beginning of each function name for Windows 95 DLL driver.
Data Types Some data types were defined in Pci_9812.h (DOS) and Acl_pci.h (Windows 95). These data types are used by the NuDAQ card library. It is recommended that you use these data types for your application programs. The following table lists the data type names and their ranges.
6.3 Function Reference _9812_Initial Description Initializes the PCI-9812/9810 card. Each PCI-9812/9810 card has to be initialized by this function before calling other functions.
Return Code(s) PCICardNumErr PCIBiosNotExist PCIBaseAddrErr NoError Function Reference 49
_9812_Close Description Closes a previously initialized 9812/9810 card. Syntax C/C++ (DOS) int _9812_Close (int card_number) C/C++ (Windows 95) int W_9812_Close (int card_number) Visual Basic (Windows 95) W_9812_Close (ByVal card_number As Long) As Long Argument(s) card_number Card number of the card to be initialized. Valid card numbers are from 0 to 9.
_9812_AD_DMA_Start Description Starts an operation of A/D conversion N times with DMA data transfer. It will take place in the background, which will not stop until the Nth conversion has been completed or until your program executes _9182_AD_DMA_Stop to stop the operation. After executing this function, check the status of the operation by using the _9812_AD_DMA_Status function.
buff (DOS) Start address of the memory buffer that stores the A/ D data. The buffer size must be larger than the number of A/D conversions. This memory should be in double-word alignment. The resolution of A/D data is 12-bit for PCI-9812 and 10-bit for PCI-9810. Refer to section 5.6 for the A/D data format. The buffer format is: DATA 1 DATA 2 DATA 3 DATA 4 ............ DATA N-1 DATA N 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit Each 16-bit data: D11 D10 D9 ...
Return Code(s) PCICardNumErr PCICardNotInit InvalidDMACnt BufNotDWordAlign DMATransferNotAllowed NoError Function Reference 53
_9812_AD_DMA_Status Description Since _9812_AD_DMA_Start is executed in the background, the function _9812_AD_DMA_Status can be used to check its operation status.
_9812_AD_DMA_Stop Description Stops the DMA data transfer. After executing this function, the _9812_AD_DMA_Start function stops. The function returns the number of transferred data, whether the A/D DMA data transfer is stopped by this function or by the DMA terminal count ISR.
_9812_Set_Clk_Src Description Specifies the ADC clock source.
_9812_Set_Clk_Rate Description Specifies the clock divider for the ADC clock. The value of the clock divider must be even and between 2 to 65534. Syntax C/C++ (DOS) int _9812_Set_Clk_Rate (int card_number, U16 clk_div) C/C++ (Windows 95) int W_9812_Set_Clk_Rate (int card_number, U16 clk_div) Visual Basic (Windows 95) W_9812_Set_Clk_Rate (ByVal card_number As Long, ByVal clk_div As Integer) As Long Argument(s) card_number The card number of the selected card. clk_div ADC clock divisor.
_9812_Set_Trig Description Sets up the trigger. The function specifies the trigger mode, trigger level (voltage), trigger source, trigger slope, and post trigger count. Refer to Chapter 5 for details.
AUX_TRIG trig_pol External digital trigger Trigger slope. 0 Positive slope trigger 1 Negative slope trigger trig_lvl Trigger level. Refer to section 4.1. post_trig_cnt Post trigger count. This value is pre-loaded to the post trigger counter when the post trigger counter register is written. It will count down on the rising edge of ADC sampling clock after the trigger condition is met. When the count reaches 0, the counter stops.
W_9812_Alloc_DMA_Mem Description Tells the Windows 95 system to allocate a block of contiguous memory for DMA transfer. This function is available only for Windows 95. Syntax C/C++ int W_9812_Alloc_DMA_Mem (U32 buf_size, HANDLE *memID, U32 *linearAddr) Visual Basic W_9812_Alloc_DMA_Mem (ByVal buf_size As Long, memID As Long, linearAddr As Long) As Long Argument(s) buf_size Bytes to allocate. Note thay the unit of this argument is byte and not sample.
W_9812_Free_DMA_Mem Description Releases a system DMA memory in Windows 95. This function is only available for Windows 95. Syntax C/C++ int W_9812_Free_DMA_Mem (HANDLE memID) Visual Basic W_9812_Free_DMA_Mem (ByVal memID As Long) As Long Argument(s) memID Memory ID of the system DMA memory to deallocate.
W_9812_Get_Sample Description For languages without pointer support such as Visual Basic, programmers can use this function to access the data in DMA buffer. This function is available only for Windows 95. Syntax C/C++ int W_9812_Get_Sample (U32 linearAddr, U32 index, I16 *ai_data) Visual Basic W_9812_Get_Sample (ByVal linearAddr As Long, ByVal idx As Long, ai_data As Integer) As Long Argument(s) linearAddr Linear address of the allocated DMA memory. index Index of the sample.
7 Calibration In data acquisition, you must calibrate your measurement devices to maintain accuracy. You can calibrate the analog input and analog output channels using your operating environment to optimize accuracy. This chapter describes the calibration process for the PCI-9812/9810 card. 7.1 Before You Proceed You need the following equipment for the calibration process: X Calibration utility. This application guides you through the calibration process and is available from the card package.
7.3 A/D Calibration A/D Calibration for Channel 0 1. Apply a +1 V input signal to A/D channel 0 and trim VR5 until the average reading of channel 0 is within the range of 2046.6±0.1 (PCI-9812) or 510.9±0.1 (PCI-9810). 2. Apply a +0 V input signal to A/D channel 0 and trim VR1 until the average reading of channel 0 is within the range of ±0.2. 3. Repeat steps 1 and 2, then adjust VR5 and VR1.
8 Software Utility The 9812util.exe included in the ADLINK all-in-One CD comes with three functions: system configuration, calibration, and functional testing. This utility is designed with a menu-driven based window style that provides not only text messages for operational guidelines, but also graphics to instruct you when setting up the hardware configuration. 8.
8.2 System Configuration Use the functions in System Configuration to configure the PCI-9812/9810 card. The following screen appears when the System Configuration menu is selected.
8.3 Calibration This function takes you through the card calibration process. The calibration program is a useful test for A/D, D/A, and DIO functions, and a tool when troubleshooting the card. NOTE For environments with frequent large fluctuations in temperature and vibration, a re-calibration interval of 3 months is recommended. For laboratory conditions, 6 months to 1 year is acceptable. When you select Calibration from the main menu, the calibration screen appears.
For example, if you select <3>, the following window appears: 68 Software Utility
8.4 Functional Testing This tool tests the A/D functions of the card. When you select Function testing. <3> from the main menu, the function test window appears. Use the function keys at the bottom of the window to set the trigger mode, trigger signal polarity, trigger level, channel number and post trigger count (for middle trigger and delay trigger). When finished, press to perform testing. This function tests and views the effects of various trigger modes.
The following diagram is a snapshot of the post-trigger testing.
