PCI/PXI-9816/26/46 4-CH 16-Bit 10/20/40 MS/s Digitizer with 512 MB SDRAM User’s Manual Manual Rev. 2.02 Revision Date: October 5, 2010 Part No: 50-17031-1020 Advance Technologies; Automate the World.
Copyright 2010 ADLINK TECHNOLOGY INC. All Rights Reserved. The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.
Getting Service from ADLINK Contact us should you require any service or assistance. ADLINK Technology, Inc. Address: 9F, No.166 Jian Yi Road, Chungho City, Taipei County 235, Taiwan קᗼխࡉؑ৬ԫሁ 166 ᇆ 9 ᑔ Tel: +886-2-8226-5877 Fax: +886-2-8226-5717 Email: service@adlinktech.com Ampro ADLINK Technology, Inc. Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com ADLINK Technology (China) Co., Ltd.
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Table of Contents Table of Contents..................................................................... i List of Tables.......................................................................... iii List of Figures ........................................................................ iv 1 Introduction ........................................................................ 1 1.1 1.2 1.3 Features............................................................................... 3 Applications ..............
3.5 3.6 3.7 3.8 Trigger Signal Exporting ............................................... 38 Trigger Modes.................................................................... 39 Post-trigger Acquisition ................................................. 39 Pre-trigger Acquisition .................................................. 40 Middle-trigger Acquisition ............................................. 41 Delay-trigger Acquisition ...............................................
List of Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1-1: 1-2: 1-3: 1-4: 1-5: 1-6: 1-7: 1-8: 1-9: 1-10: 1-11: 1-12: 2-1: 3-1: 3-2: 3-3: 3-4: Analog Input Specifications ...................................... 4 Offset and Gain Error ............................................... 4 -3dB Bandwidth, typical ............................................ 5 System Noise ...........................................................
List of Figures Figure 1-1: PCI/PXI-9816 Bandwidth Chart (50 Ω input impedance) ............................................. 6 Figure 1-2: PCI/PXI-9826 Bandwidth Chart (50 Ω input impedance) ............................................. 6 Figure 1-3: PXI-9846 Bandwidth Chart (50 Ω input impedance).. 7 Figure 1-4: PXI-9816 FFT with ±0.2 V Input Range..................... 8 Figure 1-5: PXI-9816 FFT with ±1 V Input Range........................ 9 Figure 1-6: PXI-9826 FFT with ±0.2 V Input Range...............
Characteristics......................................................... Figure 3-22: SSI_TRIG2 Output Timing....................................... Figure 3-23: SSI_TRIG2 Input Timing Requirement.................... Figure 3-24: SSI_START_OP Output and Input Timing Characteristics......................................................... Figure 3-25: The Location of Board ID Switch ............................. Figure 3-26: Enlargement of Board ID setting. ............................
vi List of Figures
1 Introduction The ADLINK PCI/PXI-9816/26/46 are 10 MS/s, 20 MS/s, and 40 MS/s sampling 16-bit 4-CH digitizers designed for digitizing high frequency and wide dynamic range signals with an input frequency up to 20 MHz. The analog input range can be programmed via software to ±1 V or ±0.2 V. With deep onboard acquisition memory up to 512 MB, the PCI/PXI-9816/26/46 are not limited by the data transfer rate of the PCI bus to enable the recording of waveforms for extended periods of time.
Flexible Triggering The PCI/PXI-9816/26/46 feature flexible triggering options such as a software trigger, external digital trigger, an analog trigger from any of the analog input channels and triggers from the PXI trigger bus. These versatile trigger sources allow you to configure the PCI/PXI-9816/26/46 to fit your application needs. Post-trigger, delay-trigger, pre-trigger and middle-trigger modes are also available to acquire data around the trigger event.
1.1 Features 3U Eurocard form factor (PXI version) Standard height, half-length PCI form factor (PCI version) Support 5 V and 3.3 V PCI signaling Support 32-bit / 66 MHz PCI interface 4 channels simultaneous single-ended analog input 16-bit high resolution ADC Up to 10 MS/s, 20 MS/s and 40 MS/s per channel 512 MB onboard memory for data storage Software selectable 50 Ω or 1 MΩ input impedance Programmable input voltage range: ±0.
1.3 Specifications Analog Input Specification Value Number of Channels 4 single-ended channels Input Connector BNC Input Impedance 50 Ω or 1 MΩ, software selectable, default 50Ω Input Coupling DC Input Range (±0.2V, ±1V) or (±1V, ±5V), software selectable Overvoltage Protection ±5V for (±0.
-3dB Bandwidth, typical Input Range PXI-9816D PXI -9826D PXI-9846D PXI-9846W PCI-9846D @50 Ω and 1 MΩ impedance ±0.2 V, ±1 V 5.1 MHz 9.6 MHz Input Range PCI-9816H PCI-9826H 20 MHz 80 MHz (±1 V) 50 MHz (±0.2 V) PXI-9846H --PCI-9846H @50 Ω and impedance ±1 V, ±5 V 5.1 MHz 9.
1 PXI-9816 0 -1 Amplitude (dB) -2 -3 -4 -5 -6 -7 -8 -9 -10 0.1M 1M Frequency (Hz) 10M Figure 1-1: PCI/PXI-9816 Bandwidth Chart (50 Ω input impedance) 1 PXI-9826 0 -1 Amplitude (dB) -2 -3 -4 -5 -6 -7 -8 -9 -10 0.
PXI-9846 1 0 -1 Amplitude (dB) -2 -3 -4 -5 -6 -7 -8 -9 -10 0.1M 1M Frequency (Hz) 10M Figure 1-3: PXI-9846 Bandwidth Chart (50 Ω input impedance) System Noise (measured and calculated under 50 Ω input impedance) Input Range PXI-9816D PXI-9826D PXI-9846D PXI-9846W PCI-9846D ±0.2 V 5.0 LSBRMS 6.0 LSBRMS 8.0 LSBRMS 15.0 LSBRMS 8.0 LSBRMS ±1 V 3.0 LSBRMS 4.0 LSBRMS 5.0 LSBRMS 7.0 LSBRMS 5.0 LSBRMS Input Range PCI-9816H PCI-9826H PCI-9846H PXI-9846H ±1 V 5.0 LSBRMS 6.0 LSBRMS 8.
Spectral Characteristics – PXI-9816 Specification Input Range ±1 V ±0.2 V 79.11 dBc 75.93 dBc Signal-to-Noise Ratio (SNR), typical 79.36 dBc 75.96 dBc Total Harmonic Distortion (THD), typical -89.90 dBc -95.77 dBc Spurious Free Dynamic Range (SFDR), typical 90.37 dBc 98.65 dBc Effective Number of Bit (ENOB), typical 12.85-Bit 12.32-Bit Signal to Noise and Distortion (SINAD), typical Test Conditions: Input signal frequency is 0.998 MHz.
PXI-9816, +/-1V, S-Rate = 10MS/s, Input Signal = 0. 998 MHz @ -1.1993 dBFS 0 -20 Magnitude (dB) -40 -60 -80 -100 -120 0 0.5 1 1.5 2 2.5 3 Frequency (Hz) 3.5 4 4.
Spectral Characteristics – PXI-9826 Specification Input Range ±1 V ±0.2 V 78.63 dBc 74.44 dBc Signal-to-Noise Ratio (SNR), typical 79.95 dBc 74.48 dBc Total Harmonic Distortion (THD), typical -88.29 dBc -93.52 dBc Signal to Noise and Distortion (SINAD), typical Spurious Free Dynamic Range (SFDR), typical 88.88dBc 95.52 dBc Effective Number of Bit (ENOB), typical 12.77-Bit 12.07-Bit Test Conditions: Input signal frequency is 0.998 MHz.
PXI-9826 +/ -1V, S-Rate = 20MS/s, I nput Signal = 0.998 MHz @ -1.
Spectral Characteristics – PXI-9846 Specification Input Range ±1 V ±0.2 V 76.06 dBc 71.97 dBc Signal-to-Noise Ratio (SNR), typical 76.17 dBc 71.98 dBc Total Harmonic Distortion (THD), typical -90.65 dBc -95.78 dBc Spurious Free Dynamic Range (SFDR), typical 91.62 dBc 96.15 dBc Effective Number of Bit (ENOB), typical 12.34-Bit 11.66-Bit Signal to Noise and Distortion (SINAD), typical Test Conditions: Input signal frequency is 0.998 MHz.
PXI-9846, +/-1V, S-Rate = 40MS/s, I nput Signal = 0.998 MHz @ -1.1732 dBFs 0 -20 Magnitude (dB) -40 -60 -80 -100 -120 0 0.2 0.4 0.6 0.8 1 1.2 Frequency (Hz) 1.4 1.6 1.
Timebase Specification Sample Clock Sources Timebase Frequency Range Value Internal: onboard oscillator External: CLK IN (front panel SMB connector), PXI STAR, PXI Trigger Bus[0..7], PXI 10MHz, SSI bus PCI/PXI-9816 PCI/PXI-9826 PCI/PXI-9846 10 MHz-1 MHz 20 MHz-1 MHz 40 MHz-1 MHz Sampling Rate Range (24-bit 10 MS/s-0.596 S/s 20 MS/s-1.192 S/s 40 MS/s-2.
Triggering Specification Value Trigger Sources Software, TRG IO (front panel SMB connector), analog trigger from CH0~CH3, PXI STAR, PXI Trigger Bus[0..7], SSI bus Trigger Modes Pre-trigger, Post-trigger, Middle-trigger, Delaytrigger TRG IO, as input port Connector type SMB Compatibility 3.3 V LVTTL, 5 V tolerant Input Level High threshold (VIH): 2.0 V, minimum Low threshold (VIL): 0.8 V, maximum Maximum Input Overload -0.5 V to +5.
Data Storage and Transfer Specification Value Onboard Memory Size 512 MB, share for four channels Data Transfer Scatter-gather DMA Table 1-10: Data Storage and Transfer Onboard Reference Specification Value Onboard Reference Voltage 5V Temperature Drift ±3 ppm/°C Recommended Warm-up Time 15 minutes Table 1-11: Onboard Reference 16 Introduction
General Information Specification Value Environment Operating Environment Ambient temperature: 0°C to +55°C for PXI version, 0°C to +50°C for PCI version Relative humidity: 10% to 90%, non-condensing Storage Environment Ambient temperature: -20°C to +85°C Relative humidity: 10% to 90%, non-condensing Physical PXI version: Single 3U PXI module, 100 mm by PCB Dimension 160 mm (not including connectors) PCI version: Standard height, half length PCI card, 167.64 mm by 106.
18 Introduction
2 Getting Started This chapter describes the proper installation environment, installation procedures, its package contents and basic information user should be aware of. NOTE: Diagrams and images of equipment mentioned are used for reference only. Actual system configuration and specs may vary. 2.1 Installation Environment Whenever unpacking and preparing to install any equipment described in this manual, please refer to the Important Safety Instructions chapter of this manual.
2.2 Package Contents Before continuing, check the package contents for any damage and check if the following items are included in the packaging: PCI/PXI-9816/26/46 digitizer card ADLINK All-in-one CD. Software installation guide PCI/PXI-9816/26/46 User’s Manual. CAUTION 20 Do not install or apply power to equipment that is damaged or if there is missing/incomplete equipment. Retain the shipping carton and packing materials for inspection.
2.3 Mechanical Drawing and I/O Connectors 160.00 20.00 CLK IN 122.50 130.63 TRG IO CH 0 100.00 CH 1 CH 2 CH 3 Unit in mm 210.03 Figure 2-1: PXI-98x6 Mechanical Drawing Figure 2-2: PCI-98x6 Mechanical Drawing The ADLINK PXI-9816/PXI-9826/PXI-9846 is packaged in a Eurocard form factor with PXI specifications measuring 160 mm in length and 100 mm in height (not including connectors). The PCI9816/9826/9846 is a half-length and standard height PCI form factor.
The connector types and functions are described as follows. Connector Direction Type CLK IN Input TRG IO Input Output SMB Description/Function The CLK IN is a 50Ω, AC-coupled external timebase input. The TRG IO is a bidirectional port SMB for external digital trigger input or output. CH0 CH1 CH2 Input BNC These channels are for attaching the analog input signals.
2.4 Installing the module To install the PXI-9816/PXI-9826/PXI-9846 module: 1. Turn off the PXI system/chassis and disconnect the power plug from the power source. 2. Align the module’s edge with the card guide in the PXI chassis. 3. Slide the module into the chassis, until resistance is felt from the PXI connector. 4. Push the ejector upwards and fully insert the module into the chassis. 5. Once inserted, a “click” can be heard from the ejector latch. 6. Tighten the screw on the front panel. 7.
2.5 Software Support ADLINK provides comprehensive software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environment such as LabVIEW® and MATLAB®. ADLINK also provides ActiveX component ware for measurement and SCADA/ HMI, and breakthrough proprietary software applications. All software options are included in the ADLINK All-in-One CD. 2.5.
You can download and install DAQPilot at: http://www.adlinktech.com/TM/DAQPilot.html DAQMaster The ADLINK DAQMaster is a smart device manager that opens up access to ADLINK data acquisition and test and measurement products. DAQMaster delivers all-in-one configurations and provides you with a full support matrix to properly and conveniently configure ADLINK Test and Measurement products.
2.5.2 WD-DASK (Legacy Drivers and Support) WD-DASK is composed for advanced 32-bit kernel drivers for customized DAQ application development. WD-DASK enables you to perform detailed operations and achieve superior performance and reliability from your digitizer system. DASK kernel drivers now support the revolutionary Windows Vista OS.
3 Operation Theory The operation theory of the PCI/PXI-9816/26/46 is described in this chapter, including the control and setting of signal sources, trigger sources, trigger modes, data transfers, and synchronizing multiple modules. 3.1 Functional Block Diagram PXI Trigger Bus[7..
3.2 Basic AI Acquisition In this section, we are going to explain the basic acquisition timing. 3.2.1 Analog Input Path The following figure shows the block diagram of the single analog input path of a digitizer. Each path provides a choice of 50 Ω input impedance or high impedance. The gain amplifier is optimized for each input range with low noise and high dynamic range. An antialiasing filter is also adopted to eliminate high frequency noise.
Table 3-1 shows several basic counters required for operating digitizers. Counter Name Length Valid value ScanIntrv DataCnt trigDelayTicks ReTrgCnt Description 24-bit Scan Interval Counter This counter is a TIMEBASE divider to the achieve equivalent sampling rate of digitizer. The equation is: Sampling rate = TIMEBASE / ScanIntrv 1 - 16777215 The value of TIMEBASE depends on the card type.
Analog signal TIMEBASE Trigger Acquisition In Progress DATA Acquisition starts right after this clock edge D1 D2 D3 D4 D253 D254 D255 D256 Trigger mode = post-trigger, DataCnt = 256, ScanIntrv = 1 Figure 3-4: Basic Acquisition Timing Of Digitizer 3.2.3 AI Data Format The following table illustrates the idea transfer characteristics of various input ranges of the PCI/PXI-9816/26/46. The data format of the PCI/PXI-9816/26/46 is straight binary.
3.3 ADC Sampling Rate and TIMEBASE Control The PXI/PCI-98X6 supports several timebase sources for analog input conversion: Internal oscillator External clock through front panel PXI_STAR (PCI version) PXI Trigger Bus[0..7] (PXI version) PXI 10M (PXI version) SSI (PCI version) The following diagram shows the timebase architecture of the PXI/ PCI-98X6.
external timebase from the front panel connector (CLK IN), PXI STAR or one of the PXI Trigger Bus lines. You can supply the timebase from external SMB connector CLK IN, which should be a sine wave or square wave signal. This signal is AC coupled with 50 Ω input impedance and the valid input level is from 1 to 2 volts peak-to-peak. Note that the external clock must be continuous for correct ADC operation because of the pipeline architecture of the ADC. 3.3.
Refer to Figure 3-6 for detail timing. Trigger TIMEBASE ScanIntrv = 1 D1 ScanIntrv = 2 D1 ScanIntrv = 3 D1 D2 D3 D4 D2 D5 D3 D6 D7 D4 D8 D9 D10 D5 D6 DATA Acquisition In Progress D2 D3 D4 Acquisition starts right after this clock edge Figure 3-6: Configuring Different Sampling Rate of a Digitizer. 3.3.5 Timebase Exporting The PCI/PXI-9816/26/46 can export timebase to one of the eight PXI trigger bus lines.
3.4 Trigger Sources In addition to the internal software trigger, the PCI/PXI-9816/26/46 also supports external analog triggers, external digital triggers, PXI_STAR triggers, PXI Trigger Bus[0..7] and SSI bus.. You can configure the trigger source by software command. Please refer to Figure 3.7 for trigger architecture.
3.4.2 External Digital Trigger An external digital trigger occurs when a TTL rising edge or a falling edge is detected at the SMB connector TRG IO on the front panel. As illustrated in Figure 3-8, the trigger polarity can be selected by software. Note that the signal level of the external digital trigger signal should be TTL-compatible, and the minimum pulse width is 20 ns.
3.4.3 Analog Trigger You can choose either CH0, CH1, CH2 or CH3 as the trigger signal while using external analog trigger source. The trigger level can be set by software with 8-bit resolution. Please refer to Table 3-3 for the ideal transfer characteristic. Trigger Level Trigger Voltage Trigger Voltage Setting (Hex) (-1V to +1V Range) (-0.2V to +0.2V) 0xFF 0.992V 0.1984V 0xFE 0.984V 0.1968V --- --- --- 0x81 0.0078V 1.56mV 0x80 0V 0V 0x7F -0.0078V -1.56mV --- --- --- 0x01 -0.
Positive-Slope Trigger Event Occurs Negative-Slope Trigger Event Occurs Trigger Level Analog Signal Figure 3-9: Analog Trigger Conditions 3.4.4 PXI STAR Trigger When you select PXI STAR as the trigger source, the PXI-9816/ PXI-9826/PXI-9846 can accept a TTL-compatible digital signal as a trigger signal. The trigger occurs when a rising edge or falling edge is detected at PXI STAR. You can use software to configure the trigger polarity.
3.4.6 Trigger Signal Exporting The PCI/PXI-9816/26/46 can export trigger signals to following connectors/bus: TRG IO on front panel and PXI Trigger Bus[0..7]. The TRG IO on the front panel can also be programmed to output the trigger signal when the trigger source is from software trigger, analog trigger, PXI STAR, or PXI Trigger Bus[0..7]. The timing characteristic is in Figure 3-10.
3.5 Trigger Modes There four trigger modes working with trigger sources to initiate different data acquisition timing when a trigger event occurs. They are described in this section. 3.5.1 Post-trigger Acquisition Use post-trigger acquisition when you want to collect data after the trigger event, as illustrated in Figure 3-11.
3.5.2 Pre-trigger Acquisition Use pre-trigger acquisition to collect data before the trigger event. The acquisition starts once specified function calls are executed to begin the pre-trigger operation, and it stops when the trigger event occurs. If the trigger event occurs after the specified amount of data has been acquired, the system only stores the data before the trigger event with specified amount, as illustrated in Figure 3-12.
3.5.3 Middle-trigger Acquisition Use middle-trigger acquisition when you want to collect data before and after the trigger event. The amount of stored data before and after trigger event can be set individually (M and N samples), as illustrated in Figure 3-14.
3.5.5 Post-trigger or Delay-trigger Acquisition with Retrigger Use post-trigger or delay trigger acquisition with re-trigger function to collect data after several trigger events, as illustrated in Figure 3-16. You can program the number of triggers then the digitizer will acquire a specific sample data each time a trigger is accepted. All of sampled data will be stored in onboard memory first until all trigger events occurred.
3.6 Data Transfers Since the maximum data throughput on the PCI/PXI-9846 (40MS/ s * 4 channels *2 Bytes/channel = 320MB/s) is much higher than the 32bit/33MHz PCI-bus bandwidth, samples are acquired into the onboard SDRAM memory before being transferred to the host computer. Since the number of stored samples per acquisition is limited by the amount of on-board memory, the PCI/PXI-9816/26/ 46 supports maximum 512MB in order to meet application requirements.
3.7 Synchronizing Multiple Modules The eight interconnected lines on PXI backplane named as PXI Trigger Bus[0:7] provide a flexible interface for multiple modules synchronization. The PXI-9816/26/46 utilizes the PXI Trigger Bus[0:7] as the System Synchronization Interface (SSI). By providing flexible routing of timebase clock and trigger signals onto PXI Trigger Bus, the PXI-9816/26/46 makes the synchronization between multiple modules easy and simple.
PXI Interface or SSI SSI_TIMEBASE Timing Control PXI Trigger Bus[0:7] or SSI SSI_TRG1 SSI_TRG2 SSI_START_OP Trigger Decision Figure 3-18: SSI Architecture For PCI-9816/26/46, a dedicate connector is served as system synchronization interface. Refer to Figure 3-19 for the connector position. All the SSI signals are routed to the 20-pin connector from FPGA. With this interface, PCI-9816/26/46 is capable of achieving multiple module synchronization.
Figure 3-19: SSI Connector Location on the PCI-9816/26/46 Figure 3-20: Installation of ACL-SSI-2 Cable CN11 19 17 15 13 11 9 7 5 3 1 20 18 16 14 12 10 8 6 4 2 PCB 46 Operation Theory
Signal Name Direction SSI_TIMEBASE Input/Output Description Location Timebase signal through SSI pin 1 SSI_TRIG1 Input/Output Trigger signal through SSI pin 11 SSI_TRIG2 Input/Output Clocked trigger signal through SSI pin 9 Acquisition start signal SSI_START_OP Input/Output in pre-trigger or middletrigger mode GND - Ground NC - No Connection Reserved Input/Output Reserved for future use pin 7 pins 2, 4, 6, 8, 10, 12, 14, 16, 18, 20 pins 3, 13 pins 5, 15, 17, 19 Table 3-5: SSI Signal
3.7.2 SSI_TRIG1 As an output, the SSI_TRIG1 signal reflects the trigger event signal in an acquisition sequence. You can use the function SSI_SourceConn() to output the SSI_TRIG1 signal. As an input, the PCI/PXI-9816/26/46 accepts the SSI_TRIG1 signal to be the trigger event source. The signal is configured in the rising edge-detection mode. When selecting the trigger sources of the PCI/PXI-9816/26/46, you can select TRSRC_SSI_1 to set SSI_TRIG1 as the source of trigger event.
3.7.3 SSI_TRIG2 and SSI_START_OP As an output, the SSI_TRIG2 signal is a clocked SSI_TRIG1 signal by TIMEBASE, as illustrated in Figure 3-22. SSI_TRIG1 TIMEBASE Tw SSI_TRIG2 Tw = 2 TIMEBASE Clocks Figure 3-22: SSI_TRIG2 Output Timing As an input, the PCI/PXI-9816/26/46 accepts the SSI_TRIG2 signal to be the source of a one-clock delayed trigger event. The controller on the PCI/PXI-9816/26/46 will then compensate the oneclock delay if using SSI_TRIG2 as the source of trigger event.
For enabling output operations, you can use the function SSI_SourceConn() to output the SSI_TRIG2 and SSI_START_OP signals. For the input operations, you can select TRSRC_SSI_2 to set SSI_TRIG2 and SSI_START_OP as the source of the trigger event and operation start signal. Two SSI_START_OP (Output) Two = 2 TIMEBASE Clocks Twi SSI_START_OP (Input) Twi = 20 ns minimum Figure 3-24: SSI_START_OP Output and Input Timing Characteristics 3.7.
tion between multiple PCI/PXI-9816/26/46 devices. A clocked SSI_TRIG2 can guarantee all PCI/PXI-9816/26/46 devices recognize the trigger event at the same clock edge if they use the same timebase. In pre-trigger and middle-trigger mode, SSI_START_OP guarantees all the PCI/PXI-9816/26/46 devices start the data acquisition at the same time.
3.8 Physical Location of the PXI and PCI Digitizer 3.8.1 Identify PXI Digitizer’s Physical Location by Geographic Address CompactPCI and PXI chassis accommodate slot numbering mechanism based on the definition of Geographical Address pins on its backplane. Users can identify module’s physical location by reading back Geographical Address. This is a useful feature especially when multiple modules are installed in one host system.
Figure 3-25: The Location of Board ID Switch Figure 3-26: Enlargement of Board ID setting. Note: Only dip switches 1-5 are valid for board ID settings. Dip switches 6- 9 are unused. When a dip switch is switched to ‘ON’, it represents ‘1’, the opposite direction represents ‘0’.
Board ID 1: ON 0: OFF Switch Number 1 2 3 4 5 0 1 1 1 1 1 1 0 1 1 1 1 2 1 0 1 1 1 3 0 0 1 1 1 4 1 1 0 1 1 5 0 1 0 1 1 6 1 0 0 1 1 7 0 0 0 1 1 8 1 1 1 0 1 9 0 1 1 0 1 10 1 0 1 0 1 11 0 0 1 0 1 12 1 1 0 0 1 13 0 1 0 0 1 14 1 0 0 0 1 15 0 0 0 0 1 16 1 1 1 1 0 17 0 1 1 1 0 18 1 0 1 1 0 19 0 0 1 1 0 20 1 1 0 1 0 21 0 1 0 1 0 22 1 0 0 1 0 23 0 0 0 1 0 24 1 1 1
Important Safety Instructions Please read and follow all instructions marked on the product and in the documentation before operating the system. Retain all safety and operating instructions for future use. Please read these safety instructions carefully. Please keep this User’s Manual for future reference. The equipment should be operated in an ambient temperature between 0 to 50C. The equipment should be operated only from the type of power source indicated on the rating label.
Openings in the case are provided for ventilation. Do not block or cover these openings. Make sure there is adequate space around the system for ventilation when setting up the work area. Never insert objects of any kind into the ventilation openings. To avoid electrical shock, always unplug all power and modem cables from the wall outlets before removing covers. Lithium Battery provided (real time clock battery) “CAUTION - Risk of explosion if battery is replaced by an incorrect type.
