PCI/PCIe/cPCI-7300A 80 MB Ultra-High Speed 32-CH Digital I/O Boards User’s Manual Manual Rev. 2.50 Revision Date: July 1, 2008 Part No: 50-11106-1030 Advance Technologies; Automate the World.
Copyright 2008 ADLINK TECHNOLOGY INC. All Rights Reserved. The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.
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Table of Contents List of Tables.......................................................................... iv List of Figures ......................................................................... v 1 Introduction ........................................................................ 1 1.1 1.2 1.3 1.4 Applications ......................................................................... 2 Features............................................................................... 2 Specifications..........
4 Operation Theory .............................................................. 33 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 I/O Configuration................................................................ 34 Block Diagram.................................................................... 35 Digital I/O Data Flow .......................................................... 36 Input FIFO and Output FIFO.............................................. 37 Bus-mastering DMA......................................
5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25 5.26 5.27 5.28 _7300_DO_DMA_Start...................................................... _7300_DO_DMA_Status ................................................... _7300_DO_DMA_Abort..................................................... _7300_DO_PG_Start......................................................... _7300_DO_PG_Stop......................................................... _7300_DI_Timer ................................................................
List of Tables Table Table Table Table iv 2-1: 3-1: 4-1: 5-1: Connector Pin Assignment ..................................... I/O Port Base Address ............................................ I/O Configuration ..................................................... Data Types .............................................................
List of Figures Figure 2-1: PCI-7300A Layout Diagram..................................... Figure 2-2: cPCI-7300A Layout Diagram................................... Figure 2-3: PCIe-7300A Layout Diagram................................... Figure 2-4: CN1 Pin Assignment ............................................... Figure 4-1: Block diagram.......................................................... Figure 4-2: Data flow of digital input ..........................................
vi List of Figures
1 Introduction The cPCI/PCI/PCIe-7300A is cPCI/PCI/PCI Express form factor ultra-high speed digital I/O card, it consists of 32 digital input or output channel. High performance designs and the state-of-the-art technology make this card to be ideal for high speed digital input and output applications. The cPCI/PCI/PCIe-7300A performs high-speed data transfers using bus mastering DMA and scatter/gather via 32-bit PCI bus architecture. The maximum data transfer rates can be up to 80MB per second.
1.1 Applications X Interface to high-speed peripherals X High-speed data transfers from other computers X Automated test equipment (ATE) X Electronic and logic testing X Interface to external high-speed A/D and D/A converter X Digital pattern generator X Waveform and pulse generation X Parallel digital communication 1.
1.3 Specifications Digital I/O (DIO) X Numbers of Channel: 32 TTL compatible inputs and/or outputs X Device: IDT 74FCT373 X I/O Configurations: Z 16 DI & 16 DO Z 32 DI Z 32 DO Input Voltage: X Low: Min. 0V; Max. 0.8 V X High: Min. +2.0 V Input Load: X X Terminator OFF: Z Low: +0.5 V @ ±20 mA Z High: +2.7 V @ ±1 mA max. Terminator ON: Z Termination resistor: 110 Ohms Z Termination voltage: 2.9V Z Low: +0.5 V @ ±22.4mA Z High: +2.7 V @ ±1mA max. Output Voltage: X Low: Min.
Transfer Characteristic X Mode: Bus Mastering DMA with Scatter/Gather X Data Transfers: 8/16/32-bit input or output (programmable) DMA Transfer count: X No limitation for chaining mode (scatter/gather) DMA Max.
X Power Consumption: PCI-7300A: Z +5 V @ 830 mA typical (onboard terminator off), 1.0 A typical (onboard terminator on) PCIe-7300A: Z +12 V @ 119 mA typical (onboard terminator off), 287 mA typical (onboard terminator on) Z +3.3 V @ 499 mA typical (onboard terminator off), 543 mA typical (onboard terminator on) cPCI-7300: Z Introduction +5 V @ 830 mA typical (onboard terminator off), 1.
1.4 Software Support ADLINK provides versatile software drivers and packages for users’ different approach to built-up a system. We not only provide programming library such as DLL for many Windows systems, but also provide drivers for software packages such as LabVIEW® and HP VEETM. All the software options are included in the ADLINK CD. Commercial software drivers are protected with serial licensed code.
are free shipped with the board. You can install and use them without license. For detail information about DAQ-LVIEW PnP, please refer to the user’s guide in the CD. (\\Manual\Software Package\DAQ-LVIEW PnP) 1.4.3 PCIS-VEE: HP-VEE Driver The PCIS-VEE includes the user objects, which are used to interface with HP VEE software package. PCIS-VEE supports Windows 98/NT/2000/XP. The HP-VEE drivers are free shipped with the board. You can install and use them without license.
8 Introduction
2 Installation This chapter describes how to install the cPCI/PCI/PCIe-7300A. At first, the contents in the package and unpacking information that you should be careful are described. Because the cPCI/PCI/PCIe7300A is following the PCI design philosophy, it is no more jumpers and DIP switches setting for configuration. The Interrupt and I/ O port address are the variables associated with automatic configuration, the resource allocation is managed by the system BIOS.
2.2 Unpacking Your cPCI/PCI/PCIe-7300A card contains sensitive electronic components that can be easily damaged by static electricity. The card should be placed on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat. Inspect the card module carton for obvious damage. Shipping and handling may cause damage to your module. Be sure there are no shipping and handling damages on the module before processing.
2.
Figure 2-2: cPCI-7300A Layout Diagram 111.15 167.
2.5 Hardware Installation Outline PCI configuration The cPCI/PCI/PCIe cards are equipped with plug and play PCI controller, it can request base addresses and interrupt according to PCI standard. The system BIOS will install the system resource based on the PCI cards’ configuration registers and system parameters (which are set by system BIOS). Interrupt assignment and memory usage (I/O port locations) of the PCI cards can be assigned by system BIOS only.
2.6 Connector Pin Assignment The PCI/cPCI/PCIe-7300A comes equipped with one 100-pin SCSI type connector (CN1) located on the rear mounting plate. The pin assignment of CN1 is illustrated in the Figure 2-3. Legend: Pins Signal Name Signal Type 1…50 GND GND 51..66 PB15…PB0 DATA Signa Direction Description Ground – these lines are the ground reference for all other signals I/O PortB bidirectional data liness-PB15 is the MSB, and PB0 is the LSB.
Pins Signal Name Signal Type Signa Direction Description 84 DITRIG CONTROL I DI TRIG – can be used to control the start of data acquisition in all DI modes. 78…81 AUXDI3…0 DATA I AUX DI 3…0 – can be used as extra input data or can be used as extra control signals. 74…77 TERMPWR POWER TERMPWR -- 4.
Figure 2-4: CN1 Pin Assignment 16 Installation
2.7 Wiring and Termination Transmission line effects and environment noise, particularly on clock and control lines, can lead to incorrect data transfers if you do not take care when running signal wires to and from the devices. Take the following precautions to ensure a uniform transformation line and minimize noise pickup: 1. Use twisted-pair wires to connect digital I/O signals to the device. Twist each digital I/O signal with a GND line. In PCI/cPCI/PCIe-7300A, 50 signals are used as GND. 2.
2.8 Termination Board Support The cPCI/PCI/PCIe-7300A can be connected with two termination boards: DIN-100S or DIN-502S. The functionality and connections are specified as follows. 2.8.1 Connect with DIN-100S The DIN-100S is a direct connection for the add-on card that is equipped with SCSI-100 connector. User can connect this daughter board by a 100-pin SCSI type cable (ACL-102100) to the cPCI/ PCI/PCIe-7300A. It is suitable for the applications of 32-bit digital input or 32-bit digital output. 2.8.
3 Registers In this chapter, the registers’ format of the cPCI/PCI/PCIe-7300A is described. This information is quite useful for the programmers who wish to handle the card by low-level programming. In addition, users can realize how to use software driver to manipulate this card after understanding the registers' structure of the cPCI/PCI/PCIe-7300A The cPCI/PCI/PCIe-7300A functions as a 32-bit PCI master device on the PCI bus.
3.1 I/O Port Base Address The registers of the cPCI/PCI/PCIe-7300A are shown in Table 3.1. The base address of these registers is also assigned by the PCI P&P BIOS. The assigned base address is stored at offset 18h of the PCR. Therefore, users can read the PCR to know the base address by using BIOS function call. Note that the cPCI/PCI/ PCIe-7300A registers are all 32 bits. Users should access these registers by 32 bits I/O instructions.
Legend: X DI_CSR: Digital input control & status register X DO_SCR: Digital output control & status register X AUX_DIO: Auxiliary digital I/O port X INT_CSR: Interrupt control and status register X DI_FIFO: DI FIFO direct access port X DO_FIFO: DO FIFO direct access port X FIFO_CR: FIFO almost empty/full programming register X POL_CTRL: Polarity control register for the control signals Caution: X I/O port is 32-bit width X 8-bit or 16-bit I/O access is not allowed.
3.2 DI_CSR: DI Control & Status Register Digital input control and status checking is done by this register.
DI_EN (R/W) X 0: Disable digital inputs X 1: Enable digital inputs DI_FIFO_CLR (R/W) X 0: No effect X 1: Clear digital input FIFO. If both PORTA and PORTB are configured as inputs, both FIFO will be cleared. Always get 0 when read.
3.3 DO_CSR: DO Control & Status Register Digital input control and status checking is done by this register. Address: BASE + 04 Attribute: READ/WRITE Data Format: Bit # 3-0 DO_WAIT_NAE Bit # 7-4 PG_STOP_TRIG PB_TERM_OFF DO_MODE Bit # 11-8 DO_FIFO_FULL DO_UNDER Bit # 15-12 - - Bit # 31-16 DO_32 DO_WAIT_TRG PAT_GEN DO_FIFO_CLR DO_EN BURST_HNDSH (2) DO_FIFO_EMPTY Don’t Care (2) This bit is different between Rev.A and Rev.B.
X 0: start output data immediately X 1: delay output data until DOTRIG is actived PB_TERM_OFF (R/W) X 0: PORTB terminator ON X 1: PORTB terminator OFF PG_STOP_TRIG (R/W) X 0: no effect X 1: Stop pattern generation when DOTRIG is deasserted DO_EN (R/W) X 0: Disable digital outputs X 1: Enabled digital outputs DO_FIFO_CLR (R/W) X 0:No effect X 1:Clear digital output FIFO. If both PORTA and PORTB are configured as outputs, both FIFO will be cleared. Always get 0 when read.
3.4 Auxiliary Digital I/O Register Auxiliary 4-bit digital inputs and 4-bit digital outputs Address: BASE + 08 Attribute: READ/WRITE Data Format: Bit # 3-0 DO_AUX_3 DO_AUX_2 DO_AUX_1 DO_AUX_0 Bit # 7-4 DI_AUX_3 DI_AUX_2 Bit # 31-8 DI_AUX_1 DI_AUX_0 Don’t Care This auxiliary digital I/O is controlled by porgram I/O only. DO_AUX_3 - DO_AUX_0 (R/W) 4-bit auxiliary output port. Program I/O only. DI_AUX_3 - DI_AUX_0 (R) 4-bit auxiliary input port.
3.5 INT_CSR: Interrupt Control and Status Register The interrupt of cPCI/PCI/PCIe-7300A is controlled and status is checked through this register.
3.6 DI_FIFO: DI FIFO direct access port The digital input FIFO data can be accessed through this port directly. Address: BASE + 0x10 Attribute: READ/WRITE Data Format: Bits 7 6 5 4 3 2 1 0 Bit # 7-0 DI_FIFO_8 Bit # 15-8 DI_FIFO_16 Bit # 31_16 DI_FIFO_32 DI_FIFO_8 Bit 7 - Bit 0 of digital input FIFO DI_FIFO_16 Bit 15 - Bit 8 of digital input FIFO if the digital input is configured as 16-bit wide or 32-bit wide.
3.7 DO_FIFO: DO external data FIFO direct access port The digital output FIFO data can be accessed through this port directly. Address: BASE + 0x0C Attribute: READ/WRITE Data Format: Bits 7 6 5 4 3 2 1 0 Bit # 7-0 DO_FIFO_8 Bit # 15-8 DO_FIFO_16 Bit # 31_16 DO_FIFO_32 DO_FIFO_8 Bit 7 - Bit 0 of digital output FIFO DO_FIFO_16 Bit 15 - Bit 8 of digital output FIFO if the digital output is configured as 16-bit wide or 32-bit wide.
3.8 FIFO_CR: FIFO almost empty/full register The register is used to control the FIFO programmable almost empty/full flag. Address: BASE + 0x018 Attribute: WRITE Only Data Format: Bits 7 6 5 4 3 2 1 0 Bit 15-0 PB_PAE_PAF Bit 31_16 PA_PAE_PAF PB_PAE_PAF (WO) Programmable almost empty/full threshold of PORTB FIFO, 2 consecutive writes are required to program PORTB FIFO. Programmable almost empty threshold first.
3.9 POL_CNTRL: Control Signal Polarity Control Register The register is used to control the control signals’ polarity. The control signals include DI_REQ, DI_ACK, DI_TRG, DO_REQ, DO_ACK and DO_TRG.
3.10 PLX PCI-9080 DMA Control Registers The registers of bus-mastering DMA as well as the control and status registers of PCI-bus interrupts are built in the PLX PCI-9080 ASIC. Users can refer to the manual of PLX PCI-9080 for detailed information.
4 Operation Theory This chapter provides the detailed operation information for the cPCI/PCI/PCIe-7300A, including I/O configuration, block diagram, input/output FIFO, bus-mastering DMA, scatter/gather, clocking mode, starting mode, termination, I/O transfer mode, and auxiliary digital I/O.
4.1 I/O Configuration The 32-bit I/O data path of PCI/cPCI/PCIe-7300A can be configured as 8-bit, 16-bit, or 32-bit, the possible configuration modes are listed as follows. Mode Channel Description DI32 PORTA (DI0…DI15) PORTB (DI16..
4.2 Block Diagram Figure 4-1 shows the block diagram of the cPCI/PCI/PCIe-7300A, it includes the I/O registers, two 16K FIFOs, auxiliary DIO, active terminators, and so on. Figure 4-1: Block diagram PORTA: 16 Digital I/O Port, it can be set as terminated mode or non-terminated mode PORTB: 16 Digital I/O Port, it can be set as terminated mode or non-terminated mode FIFO: Two 16K words FIFO for digital I/O data buffer AUX DO 3..0: Four auxiliary digital outputs AUX DI 3..
4.3 Digital I/O Data Flow When applying digital input functions, the data will be sampled into the input FIFO periodically as we configured and then transfer to the system memory by the bus mastering DMA of the PCI Bridge. Figure 4-2 show the data flow of the 16-bit digital input operation. Figure 4-2: Data flow of digital input On the other hand, Figure 4-3 shows the data flow of 16-bit digital output operation.
4.4 Input FIFO and Output FIFO Due to the data transfer rate between external devices and the cPCI/PCI/PCIe-7300A is independent from that between cPCI/ PCI/PCIe-7300A and PCI bus. Two 16K words FIFO are provided to be I/O buffers. For digital input operation, data is sampled and transferred to the input FIFO. When the input FIFO is non-empty, the PCI bridge will automatically transfer the data from the input FIFO to the system memory in the background when PCI bus is available.
4.5 Bus-mastering DMA Digital I/O data transfer between cPCI/PCI/PCIe-7300A and PC’s system memory is through bus mastering DMA, which is controlled by PCI bridge chip PLX PCI-9080. The PCI bus master means the device requires fast access to the bus or high data throughput in order to achieve good performance. However, users should note that when more than one bus masters request the bus ownership, all masters will share the bandwidth of PCI bus and the performance of each master will unavoidably drop.
hard-disk rather than memory, the bottleneck would be the data transfer rate of the hard-disk driver.
4.6 Scatter/gather DMA The PCI Bridge also supports the function of scatter/gather bus mastering DMA, which helps the users to transfer a large amount of data by linking the all memory blocks into a continuous linked list. In the multi-user or multi-tasking OS, like Microsoft Windows, Linux, and so on. It is difficult to allocate a large continuous memory block to do the DMA transfer.
4.7 Clocking Mode The data input to or output from the FIFO is operated in a specific rate. The specific sampling rate or the pacer rate can be programmable by software, by external clock, or by easy handshaking protocol. Four clocking modes are provided in the cPCI/PCI/PCIe-7300A to sample input data to the FIFO or output date from FIFO to the external devices. They are: 1. Internal Clock: Three sources are available to activate both digital input and digital output.
tion of DI-ACK. If the external device follows the rule, there would be no data lost due to FIFO overrun. 3. Handshaking: For the digital input, through DI-REQ input signal from external device and DI-ACK output signal to the external deviec, the digital input can have simple handshaking data transfer. For the digital output, through DO-REQ output signal to the dexternal device and DO-ACK input signal from external device, the digital output can have simple handshaking data transfer 4.
4.8 Starting Mode Users can also control the starting mode of digital input and output by external signals (DITRIG and DOTRIG) with the software programs. The trigger modes includes NoWait, WaitTRIG, WaitFIFO, and WaitBoth. 1. NoWait: The data transfer is started immediately when a I/O transfer command is issued. 2. WaitTRIG: The data transfer will not start until external trigger signal (DI-TRIG for digital input, DO-TRIG for digital output) is activated. 3.
4.9 Active Terminator For cPCI/PCI/PCIe-7300A, it is important to terminate your cable properly to reduce or eliminate signal reflections in the cable. The PCI/cPCI/PCIe-7300A support active terminator on board, you can enable or disable the terminator by software selection. The active terminator is the same as the one used in SCSI 2. When the terminator is ON, it presents a terminal 110-ohm impedance to the transmission line to match the line impedance.
4.10 Digital Input Operation Mode 4.10.1 Digital Input DMA in Internal Clock Mode There are three sources to trigger digital input in the internal clock mode: 20MHz, 10MHz, and programmable timer 82C54. There are three counters in 82C54, where the counter 0 is used for sampling clock source for digital input. The operations sequence of digital input with internal clock are listed as follows: 1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width. 2.
The operation flow is show as below: Note: When the DMA function of digital input starts, the input data will be stored in the FIFO of the cPCI/PCI/PCIe-7300A. The data then transfer to system memory if PCI bus is available. If the speed of translation from external device to the FIFO on board is higher than that from FIFO to system memory or the PCI bus is busy for a long time, the FIFO become full and overrun situation occurs after the next data being written to the input FIFO.
than the on-board FIFO buffer time. The FIFO size is 16K sample, so it has 1.6 ms buffer time for 10MHz sampling rate if the FIFO is empty when last DMA is complete. Users may try different DMA buffer size to see how the DMA buffer size affects the overall performance. Generally, the larger DMA size the less overhead, however, the process time required between DMAs also increases. 4.10.
The operation flow is show as below: The followings are timing diagrams of the DI-REQ and the input data. The active edge of DI-REQ can be programmed by the function 5.5.
Figure 4-8: DIREQ as input data strobe (Falling Edge Active) Note: From the timing diagram of external clock mode, the maximum frequency can be up to 40MHz. However, users should note that when the sampling frequency of digital input is higher than the PCI bus bandwidth (33Mhz), or the bandwidth of chipset (30Mhz typically) from PCI bus to system memory. Users should check the overrun status when the DMA block size is larger than 16K samples.
fer.The operations sequence of digital input with handshaking are listed: 1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width. 2. Enable or disable the active terminators. 3. Define the input sampling rate as handshaking mode. Connect the handshaking signals of the external device to input pin DI-REQ and output pin DI-ACK. 4. Define the starting mode to be NoWait or WaitTRIG. 5.
The following figure shows the timing requirement of the handshaking mode digital input operation. Figure 4-9: DIREQ & DIACK Handshaking Note: DIREQ must be asserted until DIACK asserts, DIACK will be asserted until DIREQ de-asserted. 4.10.
and remove the unnecessary processes in your application programs. 3. When high-speed sampling frequency is applied, the larger block size will improve the efficiency of DMA transferring, and probability of overrun in the DMA process will be reduced. 4. To apply the high-speed continuous digital input, it is recommended to execute your application programs in the non-multitask operation system to reduce the latency time between two DMA transfers.
4.11 Digital Output Operation Mode 4.11.1 Digital Output DMA in Internal Clock Mode There are three sources to trigger digital output: 20MHz, 10MHz, and programmable timer 82C54. There are three counters in 82C54, where the counter 1 is used timer pacer for digital output. The operations sequence of digital output with internal clock are listed: 1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width. 2. Enable or disable the active terminators. 3.
As the data output in the internal clock mode, the DOREQ signal could be use as the output strobe to indicate the output operation to the external device. The timing diagram of the DOREQ is shown as follows: Figure 4-10: DOREQ as output data strobe 4.11.2 Digital Output DMA in Handshaking Mode For digital output, through DO-REQ output signal and DO-ACK input signal, the digital output can have simple handshaking data transfer.
The operations sequence of digital output in handshaking mode are listed: 1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width. 2. Enable or disable the active terminators. 3. Define the output clock mode as handshaking mode. Connect the handshaking signals of the external device to output pin DO-REQ and input pin DO-ACK. 4. Define the starting mode to be NoWait, WaitTRIG, WaitFIFO, or WaitBoth 5.
The timing diagram of the DOREQ and DOACK in the DO handshaking mode is shown as follows: Figure 4-11: DOREQ & DOACK Handshaking Note: DOACK must be deserted before DOREQ asserts, DOACK can be asserted any time after DOREQ asserts, DOREQ will be reasserted after DOACK is asserted. 4.11.3 Digital Output DMA in Burst Handshaking Mode The burst handshaking mode is a fast and reliable data transfer protocol.
The operations sequence of digital output in burst handshaking mode are listed: 1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width. 2. Enable or disable the active terminators. 3. Define the output clock as burst handshaking mode and decide the timer pacer rate to be 20Mhz, 10Mhz, or the output of 82C54 timer 1. 4. Connect the handshaking signals of the external device to output pin DO-REQ and input pin DO-ACK. 5.
The operation flow is show as below: Note: When the DMA function of digital output starts, the output data will transfer to the output FIFO of cPCI/PCI/PCIe-7300A when PCI bus is available. If the speed of translation from the FIFO on board to the external device is higher than that from system memory to the output FIFO or the PCI bus is busy for a long time, the FIFO become empty and under-run situation occurs after the next data being read from the output FIFO.
4.11.4 Pattern Generator The digital data is output to the peripheral device periodically based on the clock signals occur at a constant rate. The digital pattern are stored in the cPCI/PCI/PCIe-7300A’s on-board FIFO with the length of pattern less than or equal to 16K samples. The operations sequence of pattern generator are listed: 1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width. 2. Enable or disable the active terminators. 3.
4.12 Auxiliary DIO The cPCI/PCI/PCIe-7300A also includes four auxiliary digital inputs and four digital outputs, which can be applied to achieve the simple I/O functions. Users can refer to the functions 5.8 - 5.11 for the detailed information.
5 C/C++ Libraries This chapter describes the software library for operating this card. Only the functions in DOS library and Windows 95 DLL are described. Please refer to the PCIS-DASK function reference manual, which included in ADLINK CD, for the descriptions of the Windows 98/NT/2000/Vista DLL functions. The function prototypes and some useful constants are defined in the header files LIB directory (DOS) and INCLUDE directory (Windows 95).
5.1 Libraries Installation Please refer to the “Software Installation Guide” for the detail information about how to install the software libraries for DOS, or Windows 95 DLL, or PCIS-DASK for Windows 98/NT/2000. The device drivers and DLL functions of Windows 98/NT/2000 are included in the PCIS-DASK. Please refer the PCIS-DASK user’s guide and function reference, which included in the ADLINK CD, for detailed programming information.
5.2 Programming Guide Naming Convention The functions of the NuDAQ PCI cards or NuIPC CompactPCI cards’ software driver are using full-names to represent the functions' real meaning. The naming convention rules are: In DOS Environment: _{hardware_model}_{action_name}. e.g. _7300_Initial(). All functions in cPCI/PCI/PCIe-7300A driver are with 7300 as {hardware_model}. But they can be used by cPCI/PCI/PCIe7300A, cPCI-7300.
5.3 _7300_Initial @ Description A cPCI/PCI/PCIe-7300A card is initialized according to the card number. Because the cPCI/PCI/PCIe-7300A is PCI bus architecture and meets the plug and play design, the IRQ and base address (pass-through address) are assigned by system BIOS directly. Every cPCI/PCI/PCIe-7300A card has to be initialized by this function before calling other functions.
irq_no:system will give an available interrupt number to this card automatically.
5.4 _7300_Close @ Description Close a previously initialized cPCI/PCI/PCIe-7300A card. @ Syntax Visual C/C++ (Windows 95) int W_7300_Close (int card_number) Visual Basic (Windows 95) W_7300_Close (ByVal card_number As Long) As Long C/C++ (DOS) int _7300_Close (int card_number) @ Argument card_number:The card number of the cPCI/PCI/PCIe-7300A card.
5.5 _7300_Configure @ Description Set the port DI/O configuration, terminator control, and control signal polarity for the cPCI/PCI/PCIe-7300A card.
PAON_PBOFF: PORTA terminator ON, PORTB terminator OFF PAON_PBON: PORTA terminator ON, PORTB terminator ON Note: term_cntrl is used to control the ON/OFF of the active terminators, not terminal power output: TERMPER) cntrl_pol:The polarity configuration. This argument is an integer expression formed from one or more of the manifest constants defined in 7300.h.
5.6 _7300_DI_Mode @ Description Set the clock mode and start mode for the cPCI/PCI/PCIe-7300A DI operation. @ Syntax Visual C/C++ (Windows 95) int W_7300_DI_Mode (int card_number, int clk_mode, int start_mode) Visual Basic (Windows 95) W_7300_DI_Mode (ByVal card_number As Long, ByVal clk_mode As Long, ByVal start_mode As Long) As Long C/C++ (DOS) int _7300_DI_Mode (int card_number, int clk_mode, int start_mode) @ Argument card_number:The card number of the cPCI/PCI/PCIe-7300A card.
5.7 _7300_DO_Mode @ Description Set the clock mode and start mode for the cPCI/PCI/PCIe-7300A DO operation.
DO_WAIT_FIFO: delay output data until FIFO is not almost empty DO_WAIT_BOTH: delay output data until DOTRIG is active and FIFO is not almost empty. fifo_threshold:programmable almost empty threshold of both PORTB FIFO and PORTA FIFO (if PORTA is set as output).
5.8 _7300_AUX_DI @ Description Read data from auxiliary digital input port. You can get all 4 bits input data by using this function. @ Syntax Visual C/C++ (Windows 95) int W_7300_AUX_DI (int card_number, int *aux_di) Visual Basic (Windows 95) W_7300_AUX_DI (ByVal card_number As Long, aux_di As Long) As Long C/C++ (DOS) int _7300_AUX_DI (int card_number, int *aux_di) @ Argument card_number:The card number of the cPCI/PCI/PCIe-7300A card. aux_di:returns 4-bit value from auxiliary digital input port.
5.9 _7300_AUX_DI_Channel @ Description Read data from auxiliary digital input channel. There are 4 digital input channels on the cPCI/PCI/PCIe-7300A auxiliary digital input port. When performs this function, the auxiliary digital input port is read and the value of the corresponding channel is returned. * channel means each bit of digital input port.
5.10 _7300_AUX_DO @ Description Write data to auxiliary digital output port. There are 4 auxiliary digital outputs on the cPCI/PCI/PCIe-7300A. @ Syntax Visual C/C++ (Windows 95) int W_7300_AUX_DI (int card_number, int do_data) Visual Basic (Windows 95) W_7300_AUX_DI (ByVal card_number As Long, ByVal do_data As Long) As Long C/C++ (DOS) int _7300_AUX_DI (int card_number, int do_data) @ Argument card_number:The card number of the cPCI/PCI/PCIe-7300A card.
5.11 _7300_AUX_DO_Channel @ Description Write data to auxiliary digital output channel (bit). There are 4 auxiliary digital output channels on the cPCI/PCI/PCIe-7300A. When performs this function, the digital output data is written to the corresponding channel. * channel means each bit of digital output port.
5.12 _7300_Alloc_DMA_Mem @ Description Contact Windows 95 system to allocate a memory for DMA transfer. This function is only available in Windows 95 version. @ Syntax Visual C/C++ (Windows 95) int W_7300_Alloc_DMA_Mem (U32 buf_size, HANDLE *memID, U32 *linearAddr) Visual Basic (Windows 95) W_7300_Alloc_DMA_Mem (ByVal buf_size As Long, memID As Long, linearAddr As Long) As Long @ Argument buf_size:Bytes to allocate. Please be careful, the unit of this argument is BYTE, not SAMPLE.
5.13 _7300_Free_DMA_Mem @ Description Deallocate a system DMA memory under the Windows 95 environment. This function is only available in the Windows 95 version. @ Syntax Visual C/C++ (Windows 95) int W_7300_Free_DMA_Mem (HANDLE memID) Visual Basic (Windows 95) W_7300_Free_DMA_Mem (ByVal memID As Long ) As Long @ Argument memID:The memory ID of the system DMA memory to deallocate.
5.14 _7300_DI_DMA_Start @ Description The function will perform digital input by DMA data transfer. It will take place in the background which will not stop until the N-th input data is transferred or your program execute the _7300_DI_DMA_Abort function to stop the process. After executing this function, it is necessary to check the status of the operation by using the function _7300_DI_DMA_Status. The cPCI/PCI/PCIe-7300A bus mastering DMA is different from traditional PC style DMA.
transfers are always longwords, this is 2 million longwords (2^21). 3. After the input sampling is started, the input data is stored in the FIFO of PCI controller. Each bus mastering data transfer continually tests if any data in the FIFO and then blocks transfer, the system will continuously loop until the conditions are satisfied again but will not exit the block transfer cycle if the block count is not complete.
ByVal clear_fifo As Long, ByVal disable_di As Long) As Long C/C++ (DOS) int _7300_DI_DMA_Start (int card_number, int mode, U32 *buffer, U32 count, int clear_fifo, int disable_di) @ Argument card_number:The card number of the cPCI/PCI/PCIe-7300A card. mode (DOS):CHAIN_DMA: chaining DMA mode. By using the scatter-gather capability of cPCI/PCI/PCIe-7300A, the input data is put to several buffers which chained together. NON_CHAIN_DMA: The input data is stored in a block of contiguous memory.
disable_di:0: digital input operation still active after DMA transfer complete 1: disable digital input operation immediately when DMA transfer complete @ Return Code NoError PCICardNumErr PCICardNotInit DMATransferNotAllowed InvalidDIOCount BufNotDWordAlign DMADscrBadAlign C/C++ Libraries 81
5.15 _7300_DI_DMA_Status @ Description Since the _7300_DI_DMA_Start function is executed in background, you can issue this function to check its operation status. @ Syntax Visual C/C++ (Windows 95) int W_7300_DI_DMA_Status (int card_number, int *status) Visual Basic (Windows 95) W_7300_DI_DMA_Status (ByVal card_number As Long, status As Long) As Long C/C++ (DOS) int _7300_DI_DMA_Status (int card_number, int *status) @ Argument card_number:The card number of the cPCI/PCI/PCIe-7300A card.
5.16 _7300_DI_DMA_Abort @ Description This function is used to stop the DMA DI operation. After executing this function, the DMA transfer operation is stopped. @ Syntax Visual C/C++ (Windows 95) int W_7300_DI_DMA_Abort (int card_number) Visual Basic (Windows 95) W_7300_DI_DMA_Abort (ByVal card_number As Long ) As Long C/C++ (DOS) int _7300_DI_DMA_Stop (int card_number) @ Argument card_number:The card number of the cPCI/PCI/PCIe-7300A card.
5.17 _7300_GetOverrunStatus @ Description When you use _7300_DI_DMA_Start to input data, the input data is stored in the FIFO of PCI controller. The data then transfer to memory through PCI-bus if PCI-bus is available. If the FIFO is full and next data is written to the FIFO, overrun situation occurs. Using this function to check overrun status.
5.18 _7300_DO_DMA_Start @ Description The function will perform digital output N times with DMA data transfer. It will takes place in the background which will not be stop until the Nth conversion has been completed or your program execute _7300_DO_DMA_Abort function to stop the process. After executing this function, it is necessary to check the status of the operation by using the function _7300_DO_DMA_Status.
** This memory should be double-word alignment count:For non-chaining mode, this is the total number of digital output data in double-words (4-byte). The value of count can not exceed 2^21 (about 2 million). For chaining mode, please set this argument as 0. The number of digital output is determined by the information in DMA descriptor nodes. repeat (DOS):0: Use non-chaining mode DMA transfer. The digital output data is stored in buff. 1: Use chaining mode DMA transfer.
5.19 _7300_DO_DMA_Status @ Description Since the _7300_DO_DMA_Start function is executed in background, you can issue the function _7300_DO_DMA_Status to check its operation status.
5.20 _7300_DO_DMA_Abort @ Description This function is used to stop the DMA DO operation. After executing this function, the _7300_DO_DMA_Start function is stopped. @ Syntax Visual C/C++ (Windows 95) int W_7300_DO_DMA_Abort (int card_number) Visual Basic (Windows 95) W_7300_DO_DMA_Abort (ByVal card_number As Long) As Long C/C++ (DOS) int _7300_DO_DMA_Abort (int card_number) @ Argument card_number:The card number of the cPCI/PCI/PCIe-7300A card.
5.21 _7300_DO_PG_Start @ Description The function will perform pattern generation with the data stored in buff_ptr. It will takes place in the background which will not be stop until your program execute _7300_DO_PG_Stop function to stop the process.
BufNotDWordAlign DMADscrBadAlign 90 C/C++ Libraries
5.22 _7300_DO_PG_Stop @ Description This function is used to stop the pattern generation operation. After executing this function, the _7300_DO_PG_Start function is stopped. @ Syntax Visual C/C++ (Windows 95) int W_7300_DO_PG_Stop (int card_number) Visual Basic (Windows 95) W_7300_DO_PG_Stop (ByVal card_number As Long) As Long C/C++ (DOS) int _7300_DO_PG_Stop (int card_number) @ Argument card_number:The card number of the cPCI/PCI/PCIe-7300A card.
5.23 _7300_DI_Timer @ Description This function is used to set the internal timer pacer for digital input. Timer pacer frequency = 10Mhz / C0. @ Syntax Visual C/C++ (Windows 95) int W_7300_DI_Timer (int card_number, U16 c0) Visual Basic (Windows 95) W_7300_DI_Timer (ByVal card_number As Long, ByVal c0 As Integer) As Long C/C++ (DOS) int _7300_DI_Timer (int card_number, U16 c0) @ Argument card_number:The card number of the cPCI/PCI/PCIe-7300A card. c0: frequency divider of Counter #0.
5.24 _7300_DO_Timer @ Description This function is used to set the internal timer pacer for digital output. Timer pacer frequency = 10Mhz / C1. @ Syntax Visual C/C++ (Windows 95) int W_7300_DO_Timer (int card_number, U16 c1) Visual Basic (Windows 95) W_7300_DO_Timer (ByVal card_number As Long, ByVal c1 As Integer) As Long C/C++ (DOS) int _7300_DO_Timer (int card_number, U16 c1) @ Argument card_number:The card number of the cPCI/PCI/PCIe-7300A card. c1: frequency divider of Counter #1.
5.25 _7300_Int_Timer @ Description This function is used to set Counter #2. @ Syntax Visual C/C++ (Windows 95) int W_7300_Int_Timer (int card_number, U16 c2) Visual Basic (Windows 95) W_7300_Int_Timer (ByVal card_number As Long, ByVal c2 As Integer) As Long C/C++ (DOS) int _7300_Int_Timer (int card_number, U16 c2) @ Argument card_number:The card number of the cPCI/PCI/PCIe-7300A card. c2: frequency divider of Counter #2. Valid value ranges from 2 to 65535.
5.26 _7300_Get_Sample @ Description For the language without pointer support such as Visual Basic, programmer can use this function to access the index-th data in input DMA buffer. This function is only available in Windows 95 version.
5.27 _7300_Set_Sample @ Description For the language without pointer support such as Visual Basic, programmer can use this function to write the output data to the index-th position in output DMA buffer. This function is only available in Windows 95 version.
5.28 _7300_GetUnderrunStatus @ Description When you use _7300_DO_DMA_Start to output data, the output data is read from the FIFO on the cPCI/PCI/PCIe-7300A. If the FIFO becomes empty and next data is read from the FIFO, underrun situation occurs. Using this function to check underrun status.
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Appendix 8254 Programmable Interval Timer Note: The material of this section is adopted from “Intel Microprocessor and Peripheral Handbook Vol. II --Peripheral” The Intel (NEC) 8254 The Intel (NEC) 8254 contains three independent, programmable, multi-mode 16 bit counter/timers. The three independent 16 bit counters can be clocked at rates from DC to 5 MHz. Each counter can be individually programmed with 6 different operating modes by appropriately formatted control words.
Control Byte: (Base + 7, Base + 11) Bit 7 6 5 4 3 2 1 0 SC1 SC0 RL1 RL0 M2 M1 M0 BCD X SC1 & SC1 - Select Counter (Bit7 & Bit 6) SC1 SC0 COUNTER X 0 0 0 0 1 1 1 0 2 1 1 ILLEGAL RL1 & RL0 - Select Read/Load operation (Bit 5 & Bit 4) RL1 RL0 X OPERATION 0 0 COUNTER LATCH 0 1 READ/LOAD LSB 1 0 READ/LOAD MSB 1 1 READ/LOAD LSB FIRST, THEN MSB M2, M1 & M0 - Select Operating Mode (Bit 3, Bit 2, & Bit 1) M2 M1 M0 MODE X 0 0 0 0 0 0 0 1 1 x 1 0 2 x 1 1 3 1 0
2. The count of the BCD counter is from 0 up to 99,999. Mode Definition In 8254, there are six different operating modes can be selected. They are: Mode 0: Interrupt on terminal count The output will be initially low after the mode set operation. After the count is loaded into the selected count register, the output will remain low and the counter will count.
The gate input when low, will force the output high. When the gate input goes high, the counter will start form the initial count. Thus, the gate input can be used to synchronized by software. When this mode is set, the output will remain high until after the count register is loaded. The output then can also be synchronized by software. Mode 3: Square Wave Rate Generator.
Mode 5: Hardware Triggered Strobe. The counter will start counting after the rising edge of the trigger input and will go low for one clock period when the terminal count is reached. The counter is re-triggerable. the output will not go low until the full count after the rising edge of any trigger. The detailed description of the 8254, please refer to the Intel Microsystem Components Handbook.
104 Appendix
