PCIe-7350 32-CH High-speed DIO Board User’s Manual Manual Rev. 2.00 Revision Date: April 8, 2009 Part No: 50-11039-1000 Advance Technologies; Automate the World.
Copyright 2009 ADLINK TECHNOLOGY INC. All Rights Reserved. The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.
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Table of Contents List of Tables.......................................................................... iii List of Figures ........................................................................ iv 1 Introduction ........................................................................ 1 1.1 1.2 1.3 1.4 Features............................................................................... 1 Applications ......................................................................... 1 Specifications.........
3.9 Application Function I/O..................................................... 56 I2C Master .................................................................... 60 SPI Master .................................................................... 62 External Digital Trigger ................................................. 64 Trigger Out .................................................................... 65 Event Out ...................................................................... 66 Handshaking ..
List of Tables Table Table Table Table Table Table Table Table 2-1: 2-2: 2-3: 2-4: 3-1: 3-2: 3-3: 3-4: Table Table Table Table Table 3-5: 3-6: 3-7: A-1: A-2: List of Tables Connector CN1 Pin Assignment ............................. I/O Signal Descriptions ........................................... SMB Jack Connector Signal Descriptions .............. LED indicator .......................................................... PCIe-7350 Logic Levels .........................................
List of Figures Figure 1-1: Acquisition Timing Diagram ....................................... 6 Figure 1-2: Generation Timing Diagram....................................... 7 Figure 2-1: PCB Layout and Mechanical Drawing of the PCIe-7350 ..................................................... 11 Figure 3-1: PCIe-7350 Block Diagram ....................................... 20 Figure 3-2: DI Row Data Mapping for 8 Bits Data Width............ 24 Figure 3-3: DI Row Data Mapping for 16 Bits Data Width..........
Figure 3-35: Configured AFI as Internal Software Trigger Output ......................................................... Figure 3-36: Pattern Match and COS Event Configuration.......... Figure 3-37: Configured AFI as Handshaking Interface............... Figure 3-38: Configured AFI7 as DI Sampled Clock In/Out ......... Figure 3-39: Configured AFI6 as DO Sampled Clock In/Out ....... Figure 3-40: Example of Pattern Match ....................................... Figure 3-41: Example of Pattern Match ..........
vi List of Figures
1 Introduction ADLINK’s PCIe-7350 is a high-speed digital I/O board with 32channel bi-direction parallel I/O lines. The data rate can achieve up to 200 MB/s through the x1 PCI Express® interface. The clock rate can support up to 50 MHz internal clock or 100 MHz external clock, which is ideal for the applications of high-speed and largescale digital data acquisition or exchange, such as digital image capture, video playback and IC testing. 1.
1.3 Specifications Digital I/O Specifications Number of Channels 32 Input or output, per group (8 channel) basis Direction (programmable) Logic Level (programmable) Input Voltage Output Voltage 2.5 V 3.3 V (5 V compatible) Min. VIH 1.2 V 1.6 V 2V Max. VIL 0.63 V 0.7 V 0.8 V Min. VOH 1.6 V 2.3 V 3.1 V Max. VOL 0.2 V 0.2 V 0.2 V ±8 mA ±16 mA ±32 mA Driving capacity(max.
Note*: DI DMA throughput DI DMA Bandwidth T est 250 192.7058 BW (MB/s) 200 168 164 160 150 192 188 184 180 176 172 192.7138 100 50 0 40 41 42 43 44 45 46 47 48 49 50 Ext ernal Clock Rat e (MHz) DI DMA Bandwidth T est 202 200 200 200 200 200 200 BW (MB/s) 198 196 194 192.58 192.01 192.64 192.56 191.98 192 190 188 186 50 100 150 200 250 300 350 400 450 500 Dat a Count (K samples) Note**: DO DMA throughput DO DMA Bandwidth Test 125 BW (MB/s) 120 11 9.2 119.34 119.
If you want to have DO throughput to be up to 200M Byte/s, the data size is limited to less than the 8K FIFO size by the following steps: Step1: Read 8K DO data from system memory into DO FIFO by DMA before writing 8K DO data from DO FIFO to the external device Step2: After 8K DO data are all stored into DO FIFO, and then start writing these 8K DO data to the external device with 50MHz DO sample clock rate and 32-bit data width.
Timing Specifications Sample Clock Clock Sources Internal clock: on-board 100MHz with 16-bit divider External clock: 1. AFI6 (for DO) 2. AFI7 (for DI) 3. SMB CLK in 1526 Hz – 50 MHz (100 MHz/ N; 2≤N≤65,535) Internal Clock Rate (programmable) Ext. frequency range 0 - 100 MHz (no phase shift) 2 MHz - 50MHz (phase shift enabled)* Phase shift Internal clock: N/A External clock: 16 steps; 1 step = 22.5° Sample Clock Exporting Destination 1. AFI6 (only for DO) 2. AFI7 (only for DI) 3.
DI Sampled Clock (AFI7) DI Data (connector) D0 t SU D1 tH D2 D3 Trace & component delay t AF7D DI Sampled Clock (into FPGA) DI Data (into FPGA) D0 D1 t D2 D3 DID t AF7D = Time delay of external sampled clock from AFI7 to internal t DID = Time delay of DI data from VHDCI connector to internal Figure 1-1: Acquisition Timing Diagram 6 Introduction
Gerenation start DO Sampled Clock (internal) Trace & component delay Exported DO Sampled Clock (SMB CLK out/ non-inverted) t SC2AF6 t ECskew Exported DO Sampled Clock (AFI6/ non-inverted) Exported DO Sampled Clock (AFI6/ inverted) Phase delay (0° ~ 360°) Exported DO Sampled Clock (AFI6/ phase delay) t AF62D DO Data D0 D1 D2 Write data to external device t SC2AF6 = Time delay from sampled clock (internal) to exported sampled clock (AFI6) t ECskew = Time delay from exported clock (AFI6) to exported
External Clock I/O Specification CLK IN (SMB Jack Connector) DI or DO sample clock Destination AC Input coupling 50 Ω Input Impedance 8 ns Minimum detectable pulse width Square Wave Voltage 0.2 Vpp to 5 Vpp Frequency 100 KHz - 50 MHz Duty cycle External sampled clock range 40% - 60% Sine Wave Voltage 0.2 Vpp to 5 Vpp Frequency 100 KHz – 50 MHz CLK OUT (SMB Jack Connector) DI or DO sample clock Sources 50 Ω Source impedance The same logic level of AFI I/O (1.8 V, 2.5 V, or 3.
SPI Master Specification Signal Direction Pin SCK O AFI0 SDO O AFI1 SDI I AFI2 CS_0 O AFI3 CS_1 O AFI4 CS_2 O AFI5 244.14 kHz -62.5 MHz, 62.5 MHz / (n + 1); 0 ≤ n ≤ 255 Supported clock rate (programmable) CS# Clock mode Mode =1 SCK Mode =0 MSB/ LSB (Default: MSB) The first bit be transferred Transfer size of Data 0 - 32 bits Transfer size of Cmd/ Addr 0 - 32 bits 0 - 15 bits Dummy size Max.
1.4 Software Support ADLINK provides versatile software drivers and packages for users’ different approach to building up a system. ADLINK not only provides programming libraries such as DLL for most Windows based systems, but also provide drivers for other software packages such as LabVIEW®. All software options are included in the ADLINK CD. Non-free software drivers are protected with licensing codes.
2 Hardware Information This chapter provides information on the PCIe-7350 layout, connectors, and pin assignments. 2.1 Card Layout Figure 2-1 shows the PCIe-7350 board layout and dimensions. 16 9 .6 5 16 7 .6 5 T1 U3 8 U2 3 LED5 U5 2 U3 9 U5 1 U4 4 LED6 JP1 U3 5 U4 6 OSC 1 U4 0 C N1 U2 4 U12 U2 5 U4 1 U4 3 U4 4 U14 U13 U11 C N4 111.15 10 0 .3 6 12 6 .
2.2 Connector Pin Assignment The PCIe-7350 card is equipped with one 68-pin SCSI-VHDCI connector and two SMB connectors. The SCSI-VHDCI connector is for high-speed digital I/O and programmable function I/O, while the SMB connectors are for sample clock input or exporting.
Pin # Pin # GND 68 34 GND (DI CLK) AFI7 67 33 AFI6 (DO CLK) GND 66 32 GND D0 65 31 D1 AFI5 64 30 AFI4 D2 63 29 D3 GND 62 28 GND D4 61 27 D5 AFI3 60 26 AFI2 D6 59 25 D7 GND 58 24 GND D8 57 23 D9 GND 56 22 GND D10 55 21 D11 GND 54 20 GND D12 53 19 D13 AFI1 52 18 GND D14 51 17 D15 GND 50 16 GND D16 49 15 D17 GND 48 14 GND D18 47 13 D19 GND 46 12 GND D20 45 11 D21 GND 44 10 GND D22 43 9 D23 GND 42 8 AFI0
Signal Descriptions Below are the signal descriptions for the SCSI-VHDCI and SMB connectors: Pin Number Signal Name Signal Type Direction Description 25, 27, 29, 31, 59, 61, 63, 65 D0 – D7 Data I/O Port_A bi-directional digital data lines 17, 19, 21, 23, 51, 53, 55, 57 D8 – D15 Data I/O Port_B bi-directional digital data lines 9, 11, 13, 15, 43, 45, 47, 49 D16 – D23 Data I/O Port_C bi-directional digital data lines 1, 3, 5, 7, 35, 37, 39, 41 D24 – D31 Data I/O Port_D bi-directional di
2.3 LED indicator There are two LEDs on the bracket which display the I2C & SPI communication and digital I/O status of the PCIe-7350.
2.4 Installing the Card IMPORTANT Install the card driver before you install the card into your computer system. Refer to section 1.5 for driver support information. To install the card: 1. Turn off the system/chassis and disconnect the power plug from the power source. 2. Remove the system/chassis cover. 3. Select the PCI Express slot that you intend to use, then remove the bracket opposite the slot, if any. 4.
2.5 Unpacking Checklist Before unpacking, check the shipping carton for any damage. If the shipping carton and/or contents are damaged, inform your dealer immediately. Retain the shipping carton and packing materials for inspection. Obtain authorization from your dealer before returning any product to ADLINK. Check if the following items are included in the package.
18 Hardware Information
3 Function Block and Operation Theory The operation theory of the PCIe-7350 card is described in this chapter. These functions include high-speed digital pattern acquisition, digital pattern generation, application function I/O, and etc. The operation theory can help you understand how to configure and operate the PCIe-7350 card.
3.1 Block Diagram There are 32-channel bi-direction high-speed digital I/O lines, 8channel AFI (Application Function I/O) lines, and two sample clock input/output channels available on the PCIe-7350 card. All the 32channel high-speed digital I/O lines are connected to level shifter, Fairchild FXL4245 and can be programmed as 1.8 V, 2.5 V, or 3.3 V (5 V compatible) logic levels.
3.2 Programmable Logic Level To interface different logic level applications, the PCIe-7350 supports three software selectable logic levels of 1.8 V, 2.5 V, or 3.3 V (5 V compatible) for all digital I/O lines, sample clocks, I2C, SPI, triggers, and events. When you choose one of these three logic levels, all the I/O lines will be at the same logic level you choose. Below are the definition and high/low range for different logic levels.
3.3 Digital I/O Configuration The 32-channel high-speed digital I/O lines are bi-direction and divided into four groups. Each group contains 8 channels and can be configured as input port or output port individually. At power-up status, all the I/O lines are preset to input ports. When configuring to digital output mode, the initial status of digital outputs are in tristate.
3.3.1 DI Row Data Mapping For digital pattern acquisition, the data width can be configured to 8-bit, 16-bit, 24-bit, or 32-bit and the data transfer is based on 32bit data width. Below is the mapping table for different DI port combination.
Configured input ports D C B A CH7 ~ CH0 (sample #4) CH7 ~ CH0 (sample #3) CH7 ~ CH0 (sample #2) CH7 ~ CH0 (sample #1) A CH15 ~ CH8 (sample #4) CH15 ~ CH8 (sample #3) CH15 ~ CH8 (sample #2) CH15 ~ CH8 (sample #1) A CH23 ~ CH16 (sample #4) CH23 ~ CH16 (sample #3) CH23 ~ CH16 (sample #2) CH23 ~ CH16 (sample #1) A CH31 ~ CH24 (sample #4) CH31 ~ CH24 (sample #3) CH31 ~ CH24 (sample #2) CH31 ~ CH24 (sample #1) Configured input ports D C B Configured input ports D C B Configured input
Configured input ports D C CH15 ~ CH0 (sample #2) CH15 ~ CH0 (sample #1) A CH23 ~ CH16 CH7 ~ CH0 (sample #2) CH23 ~ CH16 CH7 ~ CH0 (sample #1) A CH31 ~ CH24 CH7 ~ CH0 (sample #2) CH31 ~ CH24 CH7 ~ CH0 (sample #1) A CH23 ~ CH8 (sample #2) CH23 ~ CH8 (sample #1) A CH31 ~ CH24 CH15 ~ CH8 (sample #2) CH31 ~ CH24 CH15 ~ CH8 (sample #1) A CH31 ~ CH16 (sample #2) CH31 ~ CH16 (sample #1) B A Configured input ports D C B Configured input ports D C B Configured input ports D C B Configure
Configured input ports D C B A Configured input ports D C B A Configured input ports D C B CH7 ~ CH0 (sample #2) A CH7 ~ CH0 (sample #2) A CH15 ~ CH8 (sample #2) Configured input ports D C B CH7 ~ CH0 (sample #2) CH23 ~ CH0 (sample #1) CH31 ~ CH24 CH15 ~ CH0 (sample #1) CH31 ~ CH16 CH7 ~ CH0 (sample #1) CH31 ~ CH8 (sample #1) Figure 3-4: DI Row Data Mapping for 24 bits Data Width Configured input ports D C B A CH31 ~ CH0 (sample #1) Figure 3-5: DI Row Data Mapping for 32 Bits Data
3.4 Phase Shift of Sample Clock PCIe-7350 features phase shift of sample clock (on SMB connector or AFI6 & AFI7 of SCSI-VHDCI connector). The sample clock can be from external DUT or can be the exporting clock generated from internal time base. The resolution of phase shift is 4-bit (16 steps) implemented by Phase-Locked Loop (PLL) function of FPGA. In other words, the phase shift of sample clock is 22.5° x N, where N is any integer from 1 to 15.
Value Revolution 16 steps (1 step = 22.
3.5 Bus-mastering DMA Data Transfer Digital I/O data transfer between PCIe-7350 and PC’s system memory is through bus mastering DMA, which is controlled by PCIe IP Core. System Memory 120MB/s NB Chipset 250MB/s PC Main-board PCI-Express IP Core 500MB/s 8K FIFO 200MB/s DUT PCIe-7350 Figure 3-7: Maximum Data Throughput of the PCIe-7350 The bus-mastering controller controls the PCI/PCIe bus when it becomes the master of the bus.
In a multi-user or multi-tasking OS, like Microsoft Windows, Linux, and so on, it is difficult to allocate a large continuous memory block to do the DMA transfer. Therefore, the PCI/PCIe controller provides the function of scatter -gather or chaining mode DMA to link the non-continuous memory blocks into a linked list so that users can transfer very large amounts of data without being limited by the fragment of small size memory.
3.6 Sample Clock The sample clock controls the data rate of digital pattern acquisition and generation. For PCIe-7350, the sample clock can be configured from internal timer pacer or external clock through the SMB connectors or SCSI-VHDCI connector. 3.6.1 Digital Input (DI) Sample Clock For the operation of digital pattern acquisition in continuous mode or burst handshaking mode, the PCIe-7350 card can acquire digital data from external devices at a specific sampling rate (DI sample clock).
3.6.2 Digital Output (DO) Sample Clock For the operation of digital pattern generation in continuous mode or burst handshaking mode, PCIe-7350 card can generate digital data to external devices at a specific update rate (DO sample clock). DO sample clock can be selected as the following two clock sources: Internal DO sample clock – the PCIe-7350 can internally generate the sample clock signal for digital data generation.
16 steps phase shift Ext. DO sampled clk Int. DO sampled clk Ext. DO CLK Mux Gereration Engine DO CLK Mux DO Sampled CLK I AFI6 1/N 100MHz Int. Timebase SMB CLK in 1/N Int. DI sampled clk Ext. DI sampled clk Ext. DI CLK Mux 16 steps phase shift 16 steps phase shift DO sampled clk 16 steps phase shift Export. DO CLK Mux Export. DI/DO CLK Mux DI sampled clk I AFI7 Export.
Internal clock External clock Sample clock exporting DI Sample CLK DO Sample CLK On-board 100 MHz oscillator On-board 100 MHz oscillator 100 MHz/n (n = 2~65535) 100 MHz/n (n = 2~ 65535) Source AFI7 SMB CLK in AFI6 SMB CLK in Freq. 0 – 100 MHz 0 – 100 MHz Source Freq. Freq. 2 MHz – 50 MHz (phase shift) Destination Freq. 2 MHz – 50 MHz AFI7 SMB CLK out AFI6 SMB CLK out 0 – 50 MHz 0 – 50 MHz Freq.
3.7 Operation Mode The PCIe-7350 supports four different modes for acquisition and generation operation, including software polling, continuous, handshaking, and burst handshaking mode.. 3.7.1 Polling Mode (Single Read/Write) The PCIe-7350 supports a software polling mode to read or write a single chunk of data via a software command. That is, the 32-bit high-speed I/O lines can be used as a static I/O. The data width can be 8-bit, 16-bit, 24bit, or 32-bit. 3.7.
The operation architecture of DI DMA in continuous mode is shown as below: PCIe-7350 Card 100MHz 1/N AFI7 Int. DI sampled clk I Ext. DI CLK Mux DI CLK Mux Ext.
The timing diagram of DI DMA in continuous mode is shown as below: DI Sampled Clock Start Trigger t SU tH DO DI Data t SU Wait for start trigger D1 D2 D3 D4 D5 D6 tH Read data into DI FIFO t SU = Maximum required setup time t H = Maximum required hold time Figure 3-11: DI Timing Diagram Note: In the continuous mode of DI pattern acquisition, the input data will be stored in the DI FIFO of the PCIe-7350. The data then transfer to system memory by bus mastering DMA if PCIe bus is available.
3.7.3 DO DMA in Continuous Mode For the DO pattern generation operation in continuous mode, PCIe-7350 card can generate digital data to external devices at a specific update clock rate (DO sample clock). DO sample clock can be selected from internal or external clock source. The operation sequences are listed as follows: Steps: Define DO port configuration (32/24/16/8-bits data width) Define DO logic level configuration (3.3/2.5/1.
The operation architecture of DO DMA in continuous mode is shown as below: PCIe-7350 Card 100MHz 1/N AFI6 Int. DO sampled clk 16 steps phase shift Ext. DO CLK Mux DO CLK Mux Ext. DO sampled clk I External clock in Export.
The timing diagram of DO DMA in continuous mode is shown as below: DO Sampled Clock t ET2D Start Trigger (DO-Start) tW t IT2D Software Trigger out (DO-SW) Exported DO Sampled Clock (falling edge) D0 DO Data D1 D3 D4 Write data to external device Wait for start trigger tW D2 = Minimum detectable trigger width t ET2D = Delay from external trigger to do data out (about 5 cycle) t IT2D = Delay from software trigger out to do data out (about 4 cycle) Figure 3-13: DO Timing Diagram 40 Function Blo
3.7.4 DI DMA in Handshaking Mode For the DI pattern acquisition operation in handshaking mode, PCIe-7350 card can acquire input data from external devices by handshaking data transfer through DI-REQ input signal and DIACK output signal of AFI interface. The operation sequences are listed as follows: Step1: Configuration Define DI port configuration (32/24/16/8-bits data width) Define DI logic level configuration (3.3/2.5/1.
The operation architecture of DI DMA in handshaking mode is shown as below: PCIe-7350 Card AFI[7:0] DI-ACK DI-ACK DI-REQ DI-REQ D[31:0] ack clk Bus Master DMA 8K FIFO Flip Flop DI Data DI Data enable NoWait/ WaitTRIG Software trigger Start Trigger Mux AFI[7:0] DI-Start or DI-TRIG External trigger in Software trigger out Figure 3-14: DI Handshaking Mode Architecture 42 Function Block and Operation Theory
The timing diagram of DI DMA in handshaking mode is shown as below: t2 DI -REQ t3 t1 DI -ACK DO DI Data t SU D1 D2 tH Wait for DI-REQ Read data into DI FIFO t SU = Maximum required setup time t H = Maximum required hold time t 1 ≥ 20 ns t 2 ≥ 10 ns t 3 ≥ 50 ns Figure 3-15: DI Handshaking Timing Diagram Function Block and Operation Theory 43
3.7.5 DO DMA in Handshaking Mode For the DO pattern generation operation in handshaking mode, PCIe-7350 card can generate output data to external devices by handshaking data transfer through DO-REQ output signal and DO-ACK input signal of AFI interface. The operation sequences are listed as follows: Step1: Configuration Define DO port configuration (32/24/16/8-bits data width) Define DO logic level configuration (3.3/2.5/1.
The operation architecture of DO DMA in handshaking mode is shown as below: PCIe-7350 Card AFI[7:0] DO-ACK DO-ACK DO-REQ DO-REQ D[31:0] strobe out ack Bus Master DMA DO Data 8K FIFO DO Data Flip Flop enable NoWait/ WaitTRIG Start Trigger Mux Software trigger AFI[7:0] External trigger in DO-Start or DO-TRIG Software trigger out Figure 3-16: DO Handshaking Mode Architecture The timing diagram of DO DMA in handshaking mode is shown as below: t2 DO -REQ t3 DO -ACK DO Data DO D1 D2
3.7.6 DI DMA in Burst Handshaking Mode The burst handshaking mode is a fast and reliable data transfer protocol. It has both advantage of handshaking mode and continuous mode. In DI burst handshaking mode, DI-REQ signal will be active by external device when it is ready to send DI data and sample clock. And then DI-ACK signal will be generated by PCIe-7350 when it is ready to receive DI data from external device. External device should start to send DI data after it detect DI-ACK signal is active.
Step2: Execute DI DMA Read Command (burst handshaking mode) PCIe-7350 will generate DI-ACK signal when it is ready to receive DI data after DI-REQ signal is active. External device starts to send DI data and DI sample clock after DI-ACK signal is active. PCIe-7350 starts to receive DI data and DI sample clock from external device when DI-REQ and DI-ACK are all active. The DI data in the DI FIFO will be transferred into system memory directly and automatically by bus mastering DMA.
The timing diagram of DI DMA in burst handshaking mode is shown as below: DI Sampled Clock (from external) External Device is ready to send DI data DI -REQ (Active High) PCIe-7350 is ready to receive DI data DI -ACK (Active High) (DI FIFO is full) DO DI Data Wait DI-REQ asserted PCIe-7350 is not ready to receive DI data Wait DI-ACK asserted D1 D2 D3 D5 D7 DI data transfer starts DI data transfer stops (DI-REQ & DI-ACK are all asserted) (DI-ACK is de-asserted) D8 D9 DI data transfer re-s
Step1: Configuration Define DO port configuration (32/24/16/8-bits data width) Define DO logic level configuration (3.3/2.5/1.8 V) Define DO sample clock configuration (internal/external) If choose internal sampled clock, you can define sampling clock rate to be 100 MHz/n (n = 2-65535) If choose external sampled clock, the phase shift function is available when external clock rate is from 2 MHz 50 MHz.
Step2: Execute DO DMA Write Command (burst handshaking mode) The DO data saved in the system memory will be transferred to DO FIFO directly and automatically by bus mastering DMA. After DO data are ready, DO-REQ signal is asserted. PCIe-7350 start to send DO data and DO sampled clock to external device after DO-ACK signal is asserted.
The timing diagram of DO DMA in burst handshaking mode is shown as below: DO Sampled Clock PCIe-7350 is ready to send DO data DO -REQ (Active High) DO -ACK (Active High) Up to 4 samples are allowed to transfer after de-assertion of DO-ACK External device is ready to receive DO data Exported DO Sampled Clock (falling edge) DO Data DO D1 D2 D3 D4 D5 D6 D7 D8 Figure 3-21: DO Burst Handshaking Timing Diagram Function Block and Operation Theory 51
3.8 Trigger Source and Trigger Mode The PCIe-7350 supports 2 trigger sources, software command trigger and external digital trigger, to start or pause the DI or DO operation. In addition, the PCIe-7350 supports 3 trigger modes, including post trigger, gated trigger, and post trigger with re-trigger. In post trigger mode and post trigger with re-trigger mode, the polarity of digital trigger signal can be configured to rising edge or falling edge.
[Example 2] External digital trigger with post trigger DO data Count: 8 samples Trigger Event: DO-Start (rising edge) Re-Trigger Count: 3 DO Sampled Clock DO-Start (rising) tw DO Data Wait for DO-Start Write 8 data to external device Operation End t w = Minimum required pulse width time Figure 3-23: DO Post Trigger [Example 3] External digital trigger with post trigger and re-trigger DI data Count: 4 samples per trigger Trigger Event: DI-Start (rising edge) Re-Trigger Count: 3 DI Sampled Clock DI-St
[Example 4] External digital trigger with post trigger and re-trigger DO data Count: 4 samples per trigger Trigger Event: DO-Start (rising edge) Re-Trigger Count: 3 DO Sampled Clock DO-Start (rising) tw DO Data Write 4 data to external device Wait for Trigger Wait for Trigger Wait for Trigger Write 4 data to external device Write 4 data to external device Operation End t w = Minimum required pulse width time Figure 3-25: DO Post Trigger with Re-Trigger [Example 5] External digital trigger with gat
[Example 6] External digital trigger with gated trigger DO data Count: 12 samples Trigger Event: DO-Pause (logic high) DO Sampled Clock DO-Pause (logic high) DO Data Write 4 data to external device Operation Start Write 8 data to external device DO Generation Paused Operation End Figure 3-27: DO Gated Trigger Function Block and Operation Theory 55
3.9 Application Function I/O PCIe-7350 features eight AFI (Application Function I/O) lines. These bi-direction digital I/O lines allow you to route I2C, SPI, trigger, event, handshaking, and clock signals to/from the SCSIVHDCI I/O connector. The following table lists the supporting functions of AFI lines and the corresponding pin out.
Function Signal I/O Description 2 SCL I2C Master SDA SPI Master External Trigger in 2 I C Clock– I C clock signal to slave O device capable of clock rate up to 1953.125KHz. 2 2 I/O I C Serial Data– Data signal for I C read/ write communication. SCK SPI Clock– SPI clock signal to slave O device capable of clock rate up to 62.5MHz. SDI I Master Input Slave Output– Data signal for SPI read communication. SDO O Master Output Slave Input– Data signal for SPI write communication.
Function Signal I/O Description PM Pattern Match Event– A pulse signal outO put to indicate the event of pattern match of user-defined data lines. COS Change Detection Event– A pulse signal O output to indicate the change detection of any user-defined data lines. Event Digital Input Reques– In handshaking mode for DI pattern acquisition, DI-REQ carries handshaking control information from DUT to PCIe-7350.
Function Signal DI-SCLK Clock I/O Description External DI Sampled Clock in– In freerunning mode or burst handshaking mode, PCIe-7350 can receive external sampled clock from DUT for acquisition by DII/O SCLK. Export DI Sampled Clock out– In freerunning mode or burst handshaking mode, PCIe-7350 can export sampled clock of acquisition to DUT by DI-SCLK.
3.9.1 I2C Master PCIe-7350’s application function I/O (AFI) can be configured as I2C node for communicating with peripheral devices through PCIe-7350’s built-in I2C master protocol and provided Windows API directly. Along with I2C master of PCIe-7350, users can easily communicate with ADC/ Microcontroller/ EEPROM/ image sensor for initializing and programming.
I2C master of PCIe-7350 supports the clock range from 1.9 kHz to 244.14 kHz. After issuing command to I2C slave device, the clock rate might be changed according the request from I2C slave. The below formula is to calculate the I2C clock rate. Fscl = 488.
3.9.2 SPI Master PCIe-7350’s application function I/O (AFI) can be configured as SPI node for user to communicate with peripheral devices through PCIe-7350’s built-in SPI master protocol and provided API directly. Along with SPI master of PCIe-7350, user can easily communicate with ADC/ Microcontroller/ EEPROM/ image sensor for initializing and programming.
SPI master of PCIe-7350 provide at most 64 bits -- 32 bits address/ command and 32 bits data. SPI master of PCIe-7350 supports only three slave devices. Figure 3-32 shows the data transfer on SPI bus. CS# SCK SDO Cmd/Addr Cmd/Addr 0 ~ 32b Data dummy SDI TD 0 ~ 32b dummy Data dummy RD 0 ~ 32b Figure 3-32: Data Transfer on SPI Bus SPI master of PCIe-7350 supports clock frequency range from 244.14 kHz to 62.5 MHz.
3.9.3 External Digital Trigger PCIe-7350 supports external digital trigger mode to start or pause an acquisition or generation operation. PCIe-7350 supports two trigger sources, internal software trigger and external digital trigger. The digital pattern acquisition or generation will start upon a software command or an external digital trigger signal to start or pause the process. The PCIe-7350’s Application Function I/O (AFI) can be configured as the external digital trigger source.
3.9.4 Trigger Out PCIe-7350’s Application Function I/O (AFI) can be configured as trigger output when receiving a software start command of digital pattern acquisition or generation. The trigger out signal can synchronize the operation between PCIe-7350 and DUT. The pulse width of trigger out signal can be configured from 8ns to 34.359738368 sec.
3.9.5 Event Out PCIe-7350’s Application Function I/O (AFI) can be configured as event output of pattern match or COS (Change of State). Pattern Match event is a pulse signal generated while the PCIe7350’s digital data input lines matching the pre-defined pattern. COS (Change of State) event is a pulse signal generated while the PCIe-7350 detects a change on the pre-defined data input line. The pulse width of Event Out signal can be configured from 8ns to 34.359738368 sec.
3.9.6 Handshaking PCIe-7350’s Application Function I/O (AFI) can be configured as handshaking mode (DI-REQ/DI-ACK/DI-TRIG/DO-REQ/DO-ACK/ DO-TRIG) to communicate with an external device using an acknowledge signals to request and acknowledge each data transfer. The handshaking mode can ensure the data transfer without loss.
3.9.7 Sample Clock In/Out The AFI of PCIe-7350 can be configured to sample clock in/out pin. More details, please refer to section 3.6.
3.10 Pattern Match PCIe-7350 supports pattern match function to monitor the data input lines that conform to the user-defined pattern (for example, 10101110). When the data lines conform to the user-defined pattern, PCIe-7350 will generate a pulse signal of pattern match event to the AFI pin and generate the pattern match interrupt to host PC as well. Below are the conditions of pattern match. The pattern match can be a single change of specific data line or a combination of different data lines.
Figure 3-39 is an example of 9 channel (CH0 – CH8) pattern match operation. All of the enabled DI channel’s signal logic states will be compared with the user-defined pattern "1100RRFFX".
3.11 COS (Change of State) Event PCIe-7350 supports COS (Change of State) Event to monitor if there is any change on the user-defined or any data lines.
3.12 Termination Proper termination is very important for applications using highspeed digital data transfer to eliminate the signal reflection caused by cables, wiring, connectors, or PCB traces and improve signal quality. The output impedance (source impedance) of the PCIe-7350 is 50 Ω and the characteristic impedance of the SCSI-VHDCI cable is also 50 Ω.
Appendix A ADLINK DIN-68H The DIN-68H is a terminal board designed for PCIe-7350 to provide the easier wiring for test circuit or measure signal.
All jumpers on DIN-68H are used for the setting of pull-up or pulldown resistor termination. The proper termination setting can reduce signal refection during high-speed data transfer. The below diagram is the schematic of AF6, AF7, and D0 to D31. The default jumper setting of DIN-68H is set to 50Ω pull-down termination. When you change the jumper setting to 5V pull-up termination, you have to apply +5V power to +5VIN connector.
The DIN-68H also provides the option of user define pull-up resistor termination. Please note that the pad position of the resistor is on the back side of PCB and the resistor footprint is 1206 packaging. Below is the layout of the back side PCB and reference table of user-defined resistor termination.
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