PCIe-7360 100 MHz 32-CH High-Speed Digital I/O Card User’s Manual Manual Rev.: 2.00 Revision Date: Aug. 2, 2013 Part No: 50-11042-1000 Advance Technologies; Automate the World.
Revision History ii Revision Release Date Description of Change(s) 2.00 Aug.
PCIe-7360 Preface Copyright ©2013 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
Conventions Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly. Additional information, aids, and tips that help users perform tasks. NOTE: CAUTION: WARNING: iv Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.
PCIe-7360 Table of Contents Revision History...................................................................... ii Preface .................................................................................... iii List of Figures ....................................................................... vii List of Tables.......................................................................... ix 1 Introduction ........................................................................ 1 1.1 1.2 1.3 1.4 1.
3.6 Sample Clock..................................................................... 31 Digital Input (DI) Sample Clock ..................................... 31 Digital Output (DO) Sample Clock ................................ 33 3.7 Operating Modes ............................................................... 35 Polling Mode (Single Read/Write) ................................. 35 DI DMA in Continuous Mode ........................................ 35 DO DMA in Continuous Mode ...........................
PCIe-7360 List of Figures Figure 1-1: Acquisition Timing Diagram ............................................. 7 Figure 1-2: Generation Timing Diagram............................................. 8 Figure 1-3: PCIe-7360 Schematic Diagram ..................................... 12 Figure 1-4: PCIe-7360 Connectors .................................................. 13 Figure 3-1: PCIe-7360 Block Diagram ............................................. 22 Figure 3-2: DI Raw Data Mapping for 8-Bit Data Width .......
Figure 3-35: External Digital Trigger Input Configuration................... 67 Figure 3-36: Configured AFI as Internal Software Trigger Output ..... 68 Figure 3-37: Pattern Match and COS Event Configuration ................ 69 Figure 3-38: Configured AFI as Handshake Interface........................ 70 Figure 3-39: Configured AFI7 as DI Sampled Clock In/Out ............... 71 Figure 3-40: Configured AFI6 as DO Sampled Clock In/Out ............. 72 Figure 3-41: Example of Pattern Matching..................
PCIe-7360 List of Tables Table 1-1: PCIe-7360 SCSI-VHDCI 68-pin Assignment ................. 15 Table 1-2: Signal Descriptions for SCSI-VHDCI and SMB Connectors..................................................... 16 Table 1-3: SMB Jack Connector Signal Description ....................... 17 Table 1-4: LED indicator ................................................................. 17 Table 3-1: Logic Levels...................................................................
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PCIe-7360 1 Introduction ADLINK’s PCIe-7360 is a high-speed digital I/O board with 32-channel bi-directional parallel I/O lines. Data rate up to 400 MB/s is available through the x4 PCI Express® interfaces, with clock rate up to 100 MHz internal clock or 200 MHz external clock, ideally suited for high-speed and large scale digital data acquisition or exchange applications, such as digital image capture, video playback, and IC testing. 1.
1.3 Specifications 1.3.1 Interface x4 PCI Express interface Connectors SMB Jack Connector x2 (CLK IN & OUT) 68-pin SCSI-VHDCI x1 (32-bit Data Lines & 8-CH AFI) Operating Temperature 0°C - 55°C Storage Temperature -20°C - 70°C Humidity 5 - 95%, non-condensing Dimensions 168 mm (L) x 112 mm (H), not including connectors Power Consumption +3.3 VDC 1.3.2 Typical Maximum 860 mA 950 mA +12V VDC 270 mA 550 mA Total Power 6.1 W 9.
PCIe-7360 Buffer size Digital input: 8k samples Digital output: 20k samples Data transfer Software polling Bus-mastering DMA with scatter-gather Clock modes Internal clock: up to 100 MHz External clock: 200 MHz for DI, 100MHz for DO (see Note) Handshake Burst handshake Trigger source Software External digital signal Pattern match Trigger modes Post trigger with re-trigger Gate trigger Input impedance 10 kΩ Input protection range -1 to 6 V Input protection range -1 to 6 V Output impedance
1.3.3 Application Function I/O (AFI) Channels 8 Direction (programmable) Input or output, per channel basis Logic levels (programmable) 1.8 V 2.5 V 3.3 V (5 V compatible) Min. VIH 1.2 V 1.6 V 2V Max. VIL 0.63 V 0.7 V 0.8 V Min. VOH 1.6 V 2.3 V 3.1 V Max. VOL 0.2 V 0.2 V 0.2 V Driving capacity (max.
PCIe-7360 Internal clock rate (programmable) 1526 Hz – 100 MHz (100 MHz/ N; 1≤N≤65,535) Ext. frequency range Phase shift disabled: 0-200 MHz Phase shift enabled: 20MHz - 100MHz (see Note) Phase shift Internal clock: N/A External clock: 80 steps; 1 step = 4.
1.3.5 Timing Accuracy Acquisition Timing Channel-to-Cannel skew ±1.08 ns Setup time to sampled clock (tSU) 2 ns Hold time to sampled clock (tH) 2 ns Time delay of external sampled clock from AFI7 to internal (tAF7D) 6.3 ns Time delay of external sampled clock from SMB CLK 9.1 ns in to internal (tSMBID) Time delay of DI data from VHDCI connector to internal (tDID) 3.26 ns - 4.
PCIe-7360 DI Sampled Clock (AFI7) DI Data (connector) D0 t SU D1 tH D2 D3 Trace & component delay t AF7D DI Sampled Clock (into FPGA) DI Data (into FPGA) D0 D1 t D2 D3 DID t AF7D = Time delay of external sampled clock from AFI7 to internal t DID = Time delay of DI data from VHDCI connector to internal Figure 1-1: Acquisition Timing Diagram Introduction 7
Generation Start DO Sampled Clock (internal) Trace & component delay Exported DO Sampled Clock (SMB CLK out/ non-inverted) t SC2AF6 t ECskew Exported DO Sampled Clock (AFI6/ non-inverted) Exported DO Sampled Clock (AFI6/ inverted) Phase delay (0° ~ 360°) Exported DO Sampled Clock (AFI6/ phase delay) t AF62D DO Data D0 D1 D2 Write data to external device t SC2AF6 = Time delay from sampled clock (internal) to exported sampled clock (AFI6) t ECskew = Time delay from exported clock (AFI6) to exported
PCIe-7360 1.3.6 External Clock I/O Specification CLK IN (SMB Jack Connector) Destination DI or DO sample clock Input coupling AC Input Impedance 50 Ω Minimum detectable pulse 8 ns width Square Wave External sampled clock range Voltage 0.2 Vpp to 5 Vpp Frequency Phase shift disabled: 0-200 MHz Phase shift enabled: 20MHz - 100MHz Duty cycle 40% - 60% Sine Wave Voltage 0.
Transfer size of Data 0 - 4 Bytes Transfer size of Cmd/ Addr 0 - 4 Bytes Logic families (programmable) 1.8 V 2.5 V 3.3 V Min. VIH 1.2 V 1.6 V 2.0 V Max. VIL 0.63 V 0.7 V 0.8 V Min. VOH 1.6 V 2.3 V 3.1 V Max. VOL 0.2 V 0.2 V 0.2 V Input Voltage Output Voltage 1.3.8 SPI Master Specification Signal Supported clock rate (programmable) Clock mode Direction Pin SCK O AFI0 SDO O AFI1 SDI I AFI2 CS_0 O AFI3 244.14 kHz -62.5 MHz, 62.
PCIe-7360 1.4 Software Support ADLINK provides versatile software drivers and packages for users’ different approach to building up a system. ADLINK not only provides programming libraries such as DLL for most Windows based systems, but also provide drivers for other software packages such as LabVIEW®. All software options are included in the ADLINK CD. Non-free software drivers are protected with licensing codes.
1.5 Schematics, I/O and Indicators All dimensions shown are in mm NOTE: . 100.36 111.15 176.42 Figure 1-3: PCIe-7360 Schematic Diagram 1.
PCIe-7360 I/O, and two SMB connectors for sample clock input and output, as labeled on the faceplate.
ID GND 14 Pin Pin 68 ID 34 GND (DI CLK) AFI7 67 33 AFI6 (DO CLK) GND 66 32 GND D0 65 31 D1 AFI5 64 30 AFI4 D2 63 29 D3 GND 62 28 GND D4 61 27 D5 AFI3 60 26 AFI2 D6 59 25 D7 GND 58 24 GND D8 57 23 D9 GND 56 22 GND D10 55 21 D11 GND 54 20 GND D12 53 19 D13 AFI1 52 18 GND D14 51 17 D15 GND 50 16 GND D16 49 15 D17 GND 48 14 GND D18 47 13 D19 GND 46 12 GND D20 45 11 D21 GND 44 10 GND D22 43 9 D23 GND 42 8
PCIe-7360 ID Pin Pin ID D28 37 3 D29 GND 36 2 GND D30 35 1 D31 Table 1-1: PCIe-7360 SCSI-VHDCI 68-pin Assignment Pin Signal Signal Type Direction Description 25, 27, 29, 31, 59, 61, 63, 65 D0 – D7 Data I/O Port_A bi-directional digital data lines 17, 19, 21, 23, 51, 53, 55, 57 D8 – D15 Data I/O Port_B bi-directional digital data lines 9, 11, 13, 15, 43, D16 – D23 45, 47, 49 Data I/O Port_C bi-directional digital data lines 1, 3, 5, 7, 35, 37, D24 – D31 39, 41 Data I/O
Pin 33 Signal AFI6 Signal Type Control /Data Direction Description I/O Application Function I/O, can be configured as: X Handshake signal X External trigger in/out X Event out X DO sampled clock in/out 67 AFI7 Control /Data I/O Application Function I/O, can be configured as: X Handshake signal X External trigger in/out X Event out X DI sampled clock in/out 2, 4,6, 10, 12, 14, 16, 18,20, 22, 24, 28, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 54, 56, 58, 62, 66, 68 GND Ground N/A Ground refere
PCIe-7360 Signal Signal Type Direction CLK IN Clock I External clock input for DI/DO sampled clock from external device to the PCIe-7360 CLK OUT Clock O DI/DO sampled clock exporting from the PCIe-7360 to an external device Description Table 1-3: SMB Jack Connector Signal Description 1.7 LED indicator The LED on the faceplate indicates I2C & SPI communication and digital I/O status of the PCIe-7360.
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PCIe-7360 2 Getting Started 2.1 Unpacking Checklist Before unpacking, check the shipping carton for any damage. If the shipping carton and/or contents are damaged, inform your dealer immediately. Retain the shipping carton and packing materials for inspection. Obtain authorization from your dealer before returning any product to ADLINK. Check if the following items are included in the package.
5. Secure the card to the chassis with a screw. 6. Replace the system/chassis cover. 7. Connect the power plug to a power source, then turn on the system. Configuration All PCI/PCI Express cards on your system are configured individually. Because configuration is controlled by the system and the software, no jumper setting is required for base address, DMA, and interrupt IRQ. Configuration is subject to change with every boot of the system as new PCI/PCI Express® cards are added or removed.
PCIe-7360 3 Operations The PCIe-7360 provides functions including high-speed digital pattern acquisition, digital pattern generation, application function I/O, and others. 3.1 Block Diagram The PCIe-7360 provides 32-channel bi-directional high-speed digital I/O lines, 8-channel AFI (Application Function I/O) lines, and two sample clock input/output channels. All 32-channel high-speed digital I/O lines are connected to the level shifter and can be programmed as 1.8 V, 2.5 V, or 3.
. Int. Timebase 100MHz OSC Ext. CLK in 80-Step Phase Shift Control SMB IN Ext. CLK out SMB OUT DIO[31..24] Level Shifter Ext. CLK in/out DO DATA I2C/SPI 1.8/2.5/3.3V Logic Level Selectable AFI[5..0] Level Shifter AFI[7,6] Level Shifter 20K FIFO PCI Express x4 INTERFACE Level Shifter DI DMA DIO[23..16] ADLINK Smart Control Engine PCIe INTERFACE Level Shifter 8K FIFO DO DMA DIO[15..8] DI DATA DI Latch Level Shifter Logic Level Control DIO[7..
PCIe-7360 level. When connecting PCIe-7360 to a device under test (DUT), interface voltage levels must be compatible, as follows. X X X X VIH: The digital input voltage at logic high; senses a binary one (1) VIL: The digital input voltage at logic low; senses a binary zero (0) VOH: The digital output voltage at logic high; generates a binary one (1) VOL: The digital output voltage at logic low; generates a binary zero (0) Logic Levels Digital Input Digital Output 1.8 V 2.5 V 3.
DI Raw Data Mapping For digital pattern acquisition, the data width can be configured to 8-bit, 16-bit, 24-bit, or 32-bit and the data transfer is based on 32-bit data width. Below is the mapping table for different DI port combination.
PCIe-7360 Figure 3-2: DI Raw Data Mapping for 8-Bit Data Width Operations 25
Figure 3-3: DI raw data Mapping for 16-Bit Data Width 26 Operations
PCIe-7360 Figure 3-4: DI raw data Mapping for 24-Bit Data Width Figure 3-5: DI raw data Mapping for 32-Bit Data Width 3.4 Sample Clock Phase Shift PCIe-7360 features phase shift of sample clock (on SMB connector or AFI6 & AFI7 of SCSI-VHDCI connector). The sample clock can be from external DUT or can be the exporting clock generated from internal time base. The resolution of phase shift is 80 step, implemented by Phase-Locked Loop (PLL) function of FPGA.
other words, the phase shift of sample clock is 4.5° x N, where N is any integer from 1 to 80. Furthermore, in phase shifting mode, the supported clock frequency is from 20 to 100 MHz. This function can optimize the timing of digital pattern acquisition or generation to avoid sampling/exporting the data from/to DUT at transition state. Therefore, for digital input, the data can be sampled in clean and valid timing instead of transition timing.
PCIe-7360 Value Revolution 80 steps (1 step = 4.5°) Supported Frequency Range 20 MHz to 100MHz Supported CLK User can shift the clock phase ofthe following clock: External DI sample clock (from SMB CLK IN or AFI7) External DO sample clock (from SMB CLK IN or AFI6) Exported DI sample clock (from SMB CLK IN or AFI7) Exported DO sample clock (from SMB CLK IN or AFI6) 3.
due to the complexity of programming DMA transfer mode, It is recommended that a high-level program library provided by our driver be used to configure this card, a number needs only to be assigned to the sampling period and the number of conversion into the specified counters. After the trigger condition is matched, the data is transferred to the system memory by the bus-mastering DMA.
PCIe-7360 First PCI Address First Dual Address Transfer Size Next Descriptor PCI Address Dual Address Transfer Size Next Descriptor PCI Address Dual Address Transfer Size Next Descriptor PCI Bus Local Memory (FIFO) Figure 3-8: Scatter-Gather DMA for Data Transfer Choose Finite or Continuous Operation Data can be transferred continuously to or from computer memory (continuous operation), or you can specify the number of samples you want to transfer (one-shot operation).
clock). DI sample clock can be selected as the following two clock sources: X X Internal DI sample clock – the PCIe-7360 can internally generate the sample clock signal for digital data acquisition. With an internal base clock source of 100 MHz, the PCIe-7360 can generate any clock frequency of 100 MHz/n, where n is any integer from 1 to 65535. External DI sample clock – the PCIe-7360 can receive external clock signal from AFI7 or SMB CLK as the DI sample clock for synchronization applications.
PCIe-7360 Digital Output (DO) Sample Clock For the operation of digital pattern generation in continuous mode or burst handshake mode, PCIe-7360 card can generate digital data to external devices at a specific update rate (DO sample clock). DO sample clock can be selected as the following two clock sources: X X Internal DO sample clock – the PCIe-7360 can internally generate the sample clock signal for digital data generation.
80-step phase shift Int. DO sampled clk Ext. DO CLK Mux DO CLK Mux DO Sampled CLK Generation Engine Ext. DO sampled clk I AFI6 1/N 100MHz Int. Timebase SMB CLK in 1/N Int. DI sampled clk Ext. DI sampled clk Ext. DI CLK Mux 80-step phase shift 80-step phase shift DO sampled clk 80-step phase shift Export. DO CLK Mux Export. DI/DO CLK Mux DI sampled clk I AFI7 Export.
PCIe-7360 DI Sample CLK DO Sample CLK Onboard 100 MHz oscillator Onboard 100 MHz oscillator 100 MHz/n (n = 1 to 65535) 100 MHz/n (n = 1 to 65535) AFI7 SMB CLK in AFI6 SMB CLK in 0-100MHz @ 8/16/24/32-CH 0-200MHz @ 8/16-CH 0-100MHz @ 8/16/24/32-CH Freq. 20 to 100 MHz (phase shift) 20 to 100 MHz Source Internal clock Freq. Source External clock Freq. Sample clock exporting Destination AFI7 SMB CLK out AFI6 SMB CLK out Freq. 0 – 100 MHz 0 – 100 MHz Freq.
can be selected from internal or external clock source. The operation sequences are listed as follows: Steps: X X X X X X 36 Define DI port configuration (32/24/16/8-bits data width) Define DI logic level configuration (3.3/2.5/1.
PCIe-7360 Operating architecture of DI DMA in continuous mode is as shown. 100MHz 1/N AFI7 Int. DI sampled clk I Ext. DI CLK Mux DI CLK Mux Ext.
Figure 3-11: DI Timing Diagram DO DMA in Continuous Mode For the DO pattern generation operation in continuous mode, PCIe-7360 card can generate digital data to external devices at a specific update clock rate (DO sample clock). DO sample clock can be selected from internal or external clock source. The operation sequences are listed as follows: Steps: X X X X 38 Define DO port configuration (32/24/16/8-bits data width) Define DO logic level configuration (3.3/2.5/1.
PCIe-7360 PCIe-7360 can also export DO sample clock to external devices. The destination of DO sample clock exporting can be AFI6 or SMB CLK out connector. Z The phase shift function is available when exported clock is a free-running clock and the clock rate is 20 to 100 MHz. Define DO starting mode configuration (NoWait or WaitTRIG) Z If choose WaitTRIG, you can define start trigger source to be software trigger or external trigger (DO-Start) from AFI0 to AFI7. Define DO data count.
100MHz 1/N AFI6 Int. DO sampled clk I Ext. DO CLK Mux DO CLK Mux Ext. DO sampled clk 80-step phase shift Export.
PCIe-7360 DO Sampled Clock t ET2D Start Trigger (DO-Start) tW t IT2D Software Trigger out (DO-SW) Exported DO Sampled Clock (falling edge) D0 DO Data D1 Wait for start trigger tW D2 D3 D4 Write data to external device = Minimum detectable trigger width t ET2D = Delay from external trigger to do data out (about 5 cycle) t IT2D = Delay from software trigger out to do data out (about 4 cycle) Figure 3-13: DO Timing Diagram DI DMA in Handshake Mode For the DI pattern acquisition operation in han
X X nal (DI-REQ and DI-ACK) of external device to the AFI3 and AFI4. Define DI starting mode configuration (NoWait or WaitTRIG) Z If choose WaitTRIG, you can define start trigger source to be software trigger or external trigger (DI-Start or DI-TRIG) from AFI0 to AFI7. Define DI data count Step2: Execute DI DMA Read Command (handshake mode) X X X X After DI data is ready on device side, the peripheral device strobe data into the PCIe-7360 by asserting a DI-REQ signal.
PCIe-7360 AFI[7:0] DI-ACK DI-ACK DI-REQ DI-REQ D[31:0] ack clk Bus Master DMA DI Data 8kS FIFO DI Data Flip Flop enable NoWait/ WaitTRIG Software trigger Start Trigger Mux AFI[7:0] DI-Start or DI-TRIG External trigger in Software trigger out Figure 3-14: DI Handshake Mode Architecture Timing of DI DMA in handshake mode is as shown.
Figure 3-15: DI Handshake Timing Diagram DO DMA in Handshake Mode For the DO pattern generation operation in handshake mode, PCIe-7360 card can generate output data to external devices by handshake data transfer through DO-REQ output signal and DO-ACK input signal of AFI interface. The operation sequences are listed as follows: Step1: Configuration X X X 44 Define DO port configuration (32/24/16/8-bits data width) Define DO logic level configuration (3.3/2.5/1.
PCIe-7360 X X nal (DO-REQ and DO-ACK) of external device to the AFI3 and AFI4. Define DO starting mode configuration (NoWait or WaitTRIG) Z If choose WaitTRIG, you can define start trigger source to be software trigger or external trigger (DO-Start or DO-TRIG) from AFI0 to AFI7. Define DO write count Step2: Execute DO DMA Write Command (handshake mode) X X X The DO data saved in the system memory is transferred to DO FIFO directly and automatically by bus mastering DMA.
The operating architecture of DO DMA in handshake mode is as shown. AFI7 DI CLK Mux Ext. DI CLK Mux Ext.
PCIe-7360 Timing of DO DMA in handshake mode is as shown. t2 DO -REQ t3 DO -ACK DO Data DO D1 D2 Write data to external device t 2 40 ns t 3 50 ns Figure 3-17: DO Handshake Timing Diagram DI DMA in Burst Handshake Mode The burst handshake mode is a fast and reliable data transfer protocol. It has both advantage of handshake mode and continuous mode. In DI burst handshake mode, DI-REQ signal is active by external device when it is ready to send DI data and sample clock.
Step1: Configuration X X X X X X 48 Define DI port configuration (32/24/16/8-bits data width) Define DI logic level configuration (3.3/2.5/1.8 V) Define DI sample clock configuration (only external) Z The phase shift function is available when external clock is a free-running clock (not a strobe signal) and external clock rate is from 20 to 100 MHz.
PCIe-7360 Step2: Execute DI DMA Read Command (burst handshake mode) X X X X PCIe-7360 will generate DI-ACK signal when it is ready to receive DI data after DI-REQ signal is active. External device starts to send DI data and DI sample clock after DI-ACK signal is active. PCIe-7360 starts to receive DI data and DI sample clock from external device when DI-REQ and DI-ACK are all active. The DI data in the DI FIFO is transferred into system memory directly and automatically by bus mastering DMA.
Timing of DI DMA in burst handshake mode is as shown.
PCIe-7360 The PCIe-7360 can also export DO sampled clock to external devices. The destination of the exported DO sampled clock can be AFI6 or SMB CLK out connector. Z The phase shift function is available when exported clock rate is from 20 to 100 MHz. Define DO-REQ and DO-ACK signal (AFI0 - AFI7) Z For example: if configure AFI3 as DO-REQ and AFI4 as DO-ACK, and then you must connect the handshake signal (DO-REQ and DO-ACK) of external device to the AFI3 and AFI4.
100MHz 1/N AFI6 Int. DO sampled clk Ext. DO CLK Mux DO CLK Mux Ext. DO sampled clk 80-step phase shift I Export.
PCIe-7360 Timing of DO DMA in burst handshake mode is as shown. Figure 3-21: DO Burst Handshake Timing Diagram DO DMA in Burst Handshake Mode 2 DO burst handshake mode 2 improves tolerance in burst handshaking applications with large wire delay. In this mode, the PCIe-7360 confirms availability of the receiver indicated by the DO-ACK signal before it starts to send data.
3.8 Trigger Source and Trigger Mode The PCIe-7360 supports 2 trigger sources, software command trigger and external digital trigger, to start or pause the DI or DO operation. In addition, the PCIe-7360 supports 3 trigger modes, including post trigger, gated trigger, and post trigger with re-trigger. In post trigger mode and post trigger with re-trigger mode, the polarity of digital trigger signal can be configured to rising edge or falling edge.
PCIe-7360 [Example 2] External digital trigger with post trigger DO data Count: 8 samples Trigger Event: DO-Start (rising edge) Re-Trigger Count: 3 Figure 3-24: DO Post Trigger [Example 3] External digital trigger with post trigger and re-trigger DI data Count: 4 samples per trigger Trigger Event: DI-Start (rising edge) Re-Trigger Count: 3 Figure 3-25: DI Post Trigger with Re-trigger Operations 55
[Example 4] External digital trigger with post trigger and re-trigger DO data Count: 4 samples per trigger Trigger Event: DO-Start (rising edge) Re-Trigger Count: 3 Figure 3-26: DO Post Trigger with Re-Trigger [Example 5] External digital trigger with gated trigger DI data Count: 12 samples Trigger Event: DI-Pause (logic high) Figure 3-27: DI Gated Trigger 56 Operations
PCIe-7360 [Example 6] External digital trigger with gated trigger DO data Count: 12 samples Trigger Event: DO-Pause (logic high) Figure 3-28: DO Gated Trigger 3.9 Application Function I/O The PCIe-7360 features eight AFI (Application Function I/O) lines. These bi-directional digital I/O lines allow you to route I2C, SPI, trigger, event, handshake, and clock signals to/from the SCSI-VHDCI I/O connector. The following table lists the supporting functions of AFI lines and the corresponding pin out.
Function Signal Trigger out Event Handshake Clock Function I/O AFI0 AFI1 AFI2 AFI3 AFI4 AFI5 AFI6 AFI7 DI_SW O ● ● ● ● ● ● ● ● DO_SW O ● ● ● ● ● ● ● ● PM O ● ● ● ● ● ● ● ● COS O ● ● ● ● ● ● ● ● DI-REQ I ● ● ● ● ● ● ● ● DI-ACK O ● ● ● ● ● ● ● ● DI-TRIG I ● ● ● ● ● ● ● ● DO-REQ O ● ● ● ● ● ● ● ● DO-ACK I ● ● ● ● ● ● ● ● DO-TRIG I ● ● ● ● ● ● ● ● DO-SCLK I/O DI-SCLK ● I/O ● Signal I/O Description SC
PCIe-7360 Function External Trigger in Signal DI-Start I DI Start Trigger in– External digital trigger signal to begin an acquisition operation. DO-Start I DO Start Trigger in– External digital trigger signal to begin a generation operation. DI-Pause I DI Gate Trigger in– External digital signal to start/pause an acquisition operation. DO-Pause I DO Gate Trigger in– External digital signal to start/pause a generation operation.
Function Signal Digital Input Reques– In handshake mode for DI pattern acquisition, DI-REQ carries handshake control information from DUT to PCIe-7360. DI-REQ I DI-ACK Digital Input Acknowledge– In handshake mode for DI pattern acquisition, O DI-ACK carries handshake status information from PCIe-7360 to DUT. DI-TRIG I DO-REQ Digital Output Request– In handshake mode for DO pattern generation, DO-REQ O carries handshake control information from PCIe-7360 to DUT.
PCIe-7360 Function Clock Operations Signal I/O Description DI-SCLK External DI Sampled Clock in– In free-running mode or burst handshake mode, PCIe-7360 can receive external sampled clock from DUT for acquisition by I/O DI-SCLK. Export DI Sampled Clock out– In free-running mode or burst handshake mode, PCIe-7360 can export sampled clock of acquisition to DUT by DI-SCLK.
I2C Master PCIe-7360’s application function I/O (AFI) can be configured as I2C node for communicating with peripheral devices through PCIe-7360’s built-in I2C master protocol and provided Windows API directly. Along with I2C master of PCIe-7360, users can easily communicate with ADC/ Microcontroller/ EEPROM/ image sensor for initializing and programming. Figure 3-29: I2C Master of PCIe-7360 The I2C master of the PCIe-7360 provides at most 8 bytes data width -- 4 bytes address/ command and 4 bytes data.
PCIe-7360 Address or Data). Figure 3-29 shows the data transfer on the I2C bus. Figure 3-30: Data Transfer on the I2C Bus I2C master of PCIe-7360 supports the clock range from 1.9 kHz to 244.14 kHz. After issuing command to I2C slave device, the clock rate might be changed according the request from I2C slave. The below formula is to calculate the I2C clock rate. Fscl = 488.
I2C Cmd/Addr Count is less than 4 byte: I2C Data Count is less than 4 byte: Figure 3-31: I2C Data Format SPI Master PCIe-7360’s application function I/O (AFI) can be configured as SPI node for user to communicate with peripheral devices through PCIe-7360’s built-in SPI master protocol and provided API directly. Along with SPI master of PCIe-7360, user can easily communicate with ADC/ Microcontroller/ EEPROM/ image sensor for initializing and programming.
PCIe-7360 PCIe-7360 Card AFI0 SCK SPI Master SCK AFI1 SD0 SI AFI2 SDI Slave 0 S0 AFI3 CS#0 CS0 Figure 3-32: SPI Master of PCIe-7360 Operations 65
SPI master of PCIe-7360 provide at most 64 bits -- 32 bits address/ command and 32 bits data. SPI master of PCIe-7360 supports only one slave device. Figure 3-32 shows the data transfer on SPI bus. CS# SCK SDO Cmd/Addr Cmd/Addr 0 ~ 32b Data dummy SDI TD 0 ~ 32b dummy Data dummy RD 0 ~ 32b Figure 3-33: Data Transfer on SPI Bus SPI master of PCIe-7360 supports clock frequency range from 244.14 kHz to 62.5 MHz.
PCIe-7360 External Digital Trigger PCIe-7360 supports external digital trigger mode to start or pause an acquisition or generation operation. PCIe-7360 supports two trigger sources, internal software trigger and external digital trigger. The digital pattern acquisition or generation will start upon a software command or an external digital trigger signal to start or pause the process. The PCIe-7360’s Application Function I/O (AFI) can be configured as the external digital trigger source.
Trigger Out PCIe-7360’s Application Function I/O (AFI) can be configured as trigger output when receiving a software start command of digital pattern acquisition or generation. The trigger out signal can synchronize the operation between PCIe-7360 and DUT. The pulse width of trigger out signal can be configured from 16ns to 524.288 μs.
PCIe-7360 Event Out PCIe-7360’s Application Function I/O (AFI) can be configured as event output of pattern match or COS (Change of State). Pattern Match event is a pulse signal generated while the PCIe-7360’s digital data input lines matching the pre-defined pattern. COS (Change of State) event is a pulse signal generated while the PCIe-7360 detects a change on the pre-defined data input line. The pulse width of Event Out signal can be configured from 16ns to 524.288 μs.
Handshake PCIe-7360’s Application Function I/O (AFI) can be configured as handshake mode (DI-REQ/DI-ACK/DI-TRIG/DO-REQ/DO-ACK/ DO-TRIG) to communicate with an external device using an acknowledge signals to request and acknowledge each data transfer. The handshake mode can ensure the data transfer without loss.
PCIe-7360 Sample Clock In/Out The AFI of PCIe-7360 can be configured to sample clock in/out pin. For more details, please see Section 3.
PCIe-7360 Card 100MHz 1/N Internal clk DO CLK Mux DO Sampled CLK Generation 80-step phase shift DO-SCLK in I AFI6 80-step phase shift DO Data DO-SCLK out DUT O DI-CLK DI Data D0 ~ D31 DO Pattern DO Pattern Figure 3-40: Configured AFI6 as DO Sampled Clock In/Out 3.10 Pattern Match PCIe-7360 supports pattern match function to monitor the data input lines that conform to the user-defined pattern (for example, 10101110).
PCIe-7360 An example of 9 channel (CH0 – CH8) pattern match operation is shown. All of the enabled DI channel’s signal logic states is compared with the user-defined pattern "1100RRFFX".
Figure 3-41: Example of Pattern Matching 3.11 COS (Change of State) Event PCIe-7360 supports COS (Change of State) Event to monitor if there is any change on the user-defined or any data lines.
PCIe-7360 In COS mode, the DI data are sampled by 125 MHz clock rate. Therefore, the pulse width of the DI data should be longer than 8ns. Otherwise, the change detection latch register won’t latch the correct input data. An example of 8 channel change detection operation is shown. Any level change of the enabled DI data lines is detected and then generate the event and interrupt. The corresponding DI data is latched into change detection register. Figure 3-42: Example of Pattern Match 3.
by the DUT is almost the same as the output voltage of the PCIe-7360. The input impedance of the PCIe-7360 is 10 kΩ, which is a high impedance. So with a high impedance 10 kΩ load termination, the external source impedance of DUT should match the characteristic impedance (50 Ω) of the SCSI-VHDCI cable to achieve better signal integrity and avoid signal reflection. This page intentionally left blank.
PCIe-7360 Appendix A ADLINK DIN-68H The DIN-68H is a terminal board designed for PCIe-7360 to provide the easier wiring for test circuit or measure signal.
All jumpers on DIN-68H are used for the setting of pull-up or pulldown resistor termination. The proper termination setting can reduce signal refection during high-speed data transfer. The below diagram is the schematic of AF6, AF7, and D0 to D31. The default jumper setting of DIN-68H is set to 50Ω pull-down termination. When you change the jumper setting to 5V pull-up termination, you have to apply +5V power to +5VIN connector.
PCIe-7360 The DIN-68H also provides the option of user define pull-up resistor termination. Please note that the pad position of the resistor is on the back side of PCB and the resistor footprint is 1206 packaging. Below is the layout of the back side PCB and reference table of user-defined resistor termination.
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PCIe-2602 Important Safety Instructions For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment. X X X X X Read these safety instructions carefully. Keep this user’s manual for future reference. Read the specifications section of this manual for detailed information on the operating environment of this equipment.
X Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel. A Lithium-type battery may be provided for uninterrupted, backup or emergency power. Risk of explosion if battery is replaced with one of an incorrect type. Dispose of used batteries appropriately.
PCIe-7360 Getting Service Contact us should you require any service or assistance. ADLINK Technology, Inc. Address: 9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan ᄅؑקխࡉ৬ԫሁ 166 ᇆ 9 ᑔ Tel: +886-2-8226-5877 Fax: +886-2-8226-5717 Email: service@adlinktech.com Ampro ADLINK Technology, Inc. Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com ADLINK Technology (China) Co.
ADLINK Technology, Inc. (French Liaison Office) Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com ADLINK Technology Japan Corporation Address: ͱ101-0045 ᵅҀ䛑गҷ⬄ऎ⼲⬄䤯 ⬎ފ3-7-4 ⼲⬄ 374 ɛɳ 4F KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho, Chiyoda-ku, Tokyo 101-0045, Japan Tel: +81-3-4455-3722 Fax: +81-3-5209-6013 Email: japan@adlinktech.com ADLINK Technology, Inc.
