PCIe-9529 8-CH 24-Bit 192 kS/s Dynamic Signal Acquisition Module User’s Manual Manual Rev.: 2.00 Revision Date: July 11, 2014 Part Number: 50-11255-1000 Advance Technologies; Automate the World.
Revision History Revision Release Date 2.
PCIe-9529 Preface Copyright 2014 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
Additional information, aids, and tips that help users perform tasks. NOTE: CAUTION: WARNING: iv Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task. Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.
PCIe-9529 Table of Contents Preface .................................................................................... iii List of Figures ....................................................................... vii List of Tables.......................................................................... ix 1 Introduction ........................................................................ 1 1.1 1.2 1.3 Features...............................................................................
3.3 3.4 3.5 Trigger Source and Trigger Modes .................................... 22 Trigger Mode...................................................................... 25 ADC Timing Control ........................................................... 27 3.5.1 Timebase .................................................................. 27 3.5.2 DDS Timing vs. ADC ................................................ 27 3.5.3 Filter Delay in ADC ................................................... 27 3.
PCIe-9529 List of Figures Figure 1-1: Figure 1-2: Figure 1-3: Figure 1-4: Figure 1-5: Figure 1-6: Figure 1-7: Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 3-5: Figure 3-6: Figure 3-7: Figure 3-8: Figure 3-9: Figure 3-10: List of Figures Analog Input Channel Bandwidth, -1dBFS 108kS/s ... 6 Analog Input Channel Bandwidth, -1dBFS 108kS/s ... 7 Spurious Free Dynamic Range 54kS/s ...................... 7 Spurious Free Dynamic Range 108kS/s .................... 8 Spurious Free Dynamic Range 192kS/s .
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PCIe-9529 List of Tables Table Table Table Table Table Table Table Table Table Table 1-1: 1-2: 1-3: 3-1: 3-2: 3-3: 3-4: 3-5: 3-6: 3-7: List of Tables Timebase ......................................................................... 9 Trigger Source & Mode.................................................... 9 Digital Trigger Input ......................................................... 9 Input Range and Data Format ....................................... 19 Input Range Midscale Values ................
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PCIe-9529 1 Introduction The PCIe-9529 is a high-performance 8-CH 24-Bit 192 kS/s dynamic signal acquisition module, specifically designed for applications such as structural health monitoring, noise, vibration, and harshness (NVH) measurement, and phased array data acquisition.
1.3 Specifications 1.3.1 Analog Input Channel Characteristics 2 Channels 8 Type Differential or pseudo-differential Coupling AC or DC, software selectable AC coupling cutoff frequency 0.5Hz ADC resolution 24-Bit ADC type Delta-sigma Input signal range ±10V, ±1V Sampling rate (FS) 8 kS/s to 192 kS/s, 768 μS/s increments for Fs > 108 kS/s, 576 μS/s increments for 54 kS/s ≤ Fs ≤108 kS/s 192 μS/s increments for 8KS/s≤ Fs ≤54kS/s Over voltage protection Differential: ±42.
PCIe-9529 System Noise Sample Rate (kS/s) System Noise1 (LSBrms)1 Fs = 54 kS/s 37.4 Fs = 108 kS/s 66.5 Fs = 192 kS/s 74.6 1. Shorted input Common Mode Rejection Ratio (CMRR) CMRR1 (dB) Input Range (V) ±1V 65 ±10V 80 1. Input frequency < 1 kHz -3 dB Bandwidth Sample rate1 -3 dB bandwidth Fs < 108 kS/s >0.4863 FS Fs > 108 kS/s >0.22 FS 1.
Spurious Free Dynamic Range (SFDR) SFDR (dBc)1,2 Input Range (V) Fs = 54 kS/s Fs = 108 kS/s Fs = 192 kS/s ±1V, ±10V 104 104 105 1. 1 kHz input tone and -1 dBFS input amplitude. 2. Measurement Includes harmonics. Dynamic Range Dynamic Range (dBFS)1 Input Range (V) Fs = 54 kS/s Fs = 108 kS/s Fs = 192 kS/s ±1V, ±10V 107 100 100 1.
PCIe-9529 Total Harmonic Distortion plus noise (THD+N) THD+N (dBc)1 Input Range (V) 54 kS/s 20 Hz to 22 kHz 108 kS/s 20 Hz to 45 kHz 192 kS/s 20 Hz to 42 kHz ±1V -96 -94 -95 ±10V -96 -92 -95 1. 1 kHz input tone and -1 dBFS input amplitude Intermodulation Distortion IMD (dBc)1,2 Input Range (V) Fs = 54 kS/s Fs = 108 kS/s Fs = 192 kS/s ±1V -103 -99 -99 ±10V -105 -101 -101 1. CCIF 14 kHz + 15 kHz 2.
Interchannel Phase Mismatch Phase Mismatch (°)1 Input Range (V) ±1V, ±10V 1 khz 20 khz 86.4 khz 0.1 0.442 1.64 1.
PCIe-9529 Response when AC coupling enabled 0 −0.5 −1 Magnitude (dB) −1.5 −2 −2.5 −3 −3.5 −4 −4.5 −1 0 10 1 10 Frequency (Hz) 10 Figure 1-2: Analog Input Channel Bandwidth, -1dBFS 108kS/s SFDR 54 kS/s (1V Input Range, −1 dBFS and 1 kHz Sine Wave Input) 0 −20 Magnitude (dB) −40 −60 −80 −100 −120 −140 −160 0 0.5 1 1.5 Frequency (Hz) 2 2.
SFDR 108 kS/s (1V Input Range, −1 dBFS and 1 kHz Sine Wave Input) 0 −20 Magnitude (dB) −40 −60 −80 −100 −120 −140 −160 0 0.5 1 1.5 2 2.5 3 Frequency (Hz) 3.5 4 4.
PCIe-9529 1.3.2 Timebase Sampling Clock Internal: onboard synthesizer (10 MHz, accuracy < ± 25ppm) Sampling Clock Timebase External: SSI Delay Trigger Timebase PCIe clock (125 MHz) Table 1-1: Timebase 1.3.3 Triggers Trigger Source & Mode Trigger source Software, external digital trigger, analog trigger, and SSI Trigger mode Post trigger and delay trigger Table 1-2: Trigger Source & Mode Digital Trigger Input Sources Front panel SMB connector Compatibility 3.
Operating Temperature: 0°C - 55°C Relative humidity: 10% - 90%, non-condensing Storage Temperature: -20°C - +80°C Relative humidity: 10% - 90%, non-condensing Calibration Onboard reference +5.000 V Temperature coefficient < 5.0 ppm/°C Warm-up time 15 minutes Power Consumption Power Rail Standby Current (mA) Full Load (mA) +3.
PCIe-9529 1.4 Schematics and I/O All dimensions are in mm NOTE: 100.36 59.05 176.
The PCIe-9529 I/O array is labeled to indicate connectivity, as shown.
PCIe-9529 1.5 Software Support ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environments such as LabVIEW®. 1.5.1 SDK For customers who want to write their own programs, ADLINK provides the following software development kits. Z Z 1.5.
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PCIe-9529 2 Getting Started This chapter describes proper installation environment, installation procedures, package contents and basic information users should be aware of regarding the PCIe-9529. Diagrams and illustrated equipment are for reference only. Actual system configuration and specifications may vary. NOTE: 2.
Inspect the carton and packaging for damage. Shipping and handling could cause damage to the equipment inside. Make sure that the equipment and its associated components have no damage before installation. CAUTION: WARNING: The equipment must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the equipment and wear a grounded wrist strap when servicing.
PCIe-9529 3 Operations This chapter contains information regarding analog input, triggering and timing for the PCIe-9529. JFET Buffer OPAMP CH0 Quad 24bit ADC PGA BUF PGA ADC BUF PGA ADC BUF PGA ADC BUF PGA ADC SSI Bus [0..7] CH1 2-bit /12.288MHz SSI Connector 3.1 Functional Block Diagram CH2 CH4 BUF CLK Synthesizer Quad 24bit ADC PGA SSI_TIMEBASE ADC PGA CH5 2-bit / 12.
Differential and Pseudo-Differential Input Configuration The PCIe-9529 provides both differential and psuedo-differential input configurations, with differential input mode providing voltage to the anode and cathode inputs of the SMB connector according to signal voltage difference therebetween. If the signal source is ground-referenced, differential input mode can be used for common-mode noise rejection.
PCIe-9529 3.2.2 Input Range and Data Format When using an A/D converter, properties of the signal to be measured should be considered prior to selecting channel and signal connection to the module. A/D acquisition is initiated by a trigger source, which must be predetermined. Data acquisition commences once the trigger condition is established. Following completion of A/D conversion, A/D data is buffered in a Data FIFO, and can then be transferred to PC memory for further processing.
at 27.648MS/s, 256 times the sampling rate. The 1-bit 27.648MS/s data streams from 1-bit ADC to its internal digital filter circuit to produce 24-bit data at 108kS/s. The noise shaping removes quantization noise from low frequency to high frequency. At the last stage, the digital filter improves ADC resolution and removes high frequency quantization noise. The relationship between ADC sample rate and DDS output clock is as follows. Sampling Rate DDS(PLL) CLK 8k to 54kS/s 6.144M~41.
PCIe-9529 ing OS, such as Microsoft Windows, Linux, or other, it is difficult to allocate a large continuous memory block. Therefore, the bus controller provides DMA transfer with scatter-gather function to link non-contiguous memory blocks into a linked list to enable transfer of large amounts of data without memory limitations.
3.3 Trigger Source and Trigger Modes Software Trigger SSI BUS [5] Analog Trigger Analog Trigger Selection Trigger Source Mux Analog CH0 Analog CH1 Analog CH2 Analog CH3 Analog CH4 Analog CH5 Analog CH6 Analog CH7 Trigger Decision SSI_AD_TRIG SSI BUS [5] To Internal Circuit TRG IN SMB Connector Digital Trigger Input SSI_AD_TRIG Figure 3-3: Trigger Architecture The PCIe-9529 requires a trigger to implement acquisition of data. Configuration of triggers requires identification of trigger source.
PCIe-9529 Pulse Width > 20ns Rising edge trigger event Pulse Width > 20ns Falling edge trigger event Figure 3-4: External Digital Trigger SSI_AD_TRIG The PCIe-9529 utilizes SSI Bus Number 5 to act as a System Synchronization Interface (SSI). With the interconnected bus provided by SSI Bus, multiple modules are easily synched. When configured as input the PCIe-9529 serves as a slave module and can accept trigger signals from SSI Bus Number 5, asserted from other PCIe-9529 modules.
Z the specified trigger level to a voltage exceeding the specified trigger level. Negative-slope trigger: The trigger event occurs when the analog input signal changes from a voltage exceeding the specified trigger level to a voltage lower than the specified trigger level.
PCIe-9529 Trigger Export The PCIe-9529 utilizes SSI Bus Number 5 to act as a System Synchronization Interface (SSI). With the interconnected bus provided by SSI Bus, multiple modules are easily synched. When configured as input the PCIe-9529 serves as a slave module and can accept trigger signals from SSI Bus Number 5, asserted from other PCIe-9529 modules. When configured as output, the PCIe-9529 serves as a master module and can output trigger signals to SSI Bus Number 5. 3.
specified by a 32-bit counter value with the counter clocking based on the PCIe clock. Accordingly, maximum delay time is the period of PCIe_CLK X (2^32 - 1) and minimum is the period of PCIe_CLK (8 ns). Figure 3-7: Delay Trigger Mode Acquisition Post-Trigger or Delay-Trigger Acquisition with Re-Trigger Post-trigger or delay trigger acquisition with re-trigger function enables collection of data after several trigger events, as shown.
PCIe-9529 3.5 ADC Timing Control Timebase SYNC_CLK 1-to-4 Clock Buffer & PLL SSI_TIMEBASE Timebase Clock Mux SSI Bus [0] Onboard Oscillator 10M SSI_TIMEBASE ADC0_CLK SSI Bus [0] 3.5.1 ADC1_CLK FPGA_MCLK Figure 3-9: Timebase Architecture An onboard timebase clock drives the sigma-delta ADC, with frequency exceeding the sample rate and produced by a PLL chip, with output frequency programmable to superior resolution.
Update Rate (kS/s) Filter Delay (samples) 108 K-192 kS/s 5 Table 3-6: ADC Filter Delay 3.6 Synchronizing Multiple Modules The SSI (System Synchronization Interface) provides DAQ timing synchronization between multiple cards, with a bidirectional SSI I/O providing flexible connection between cards and allowing a single SSI master to output the signal to other slave modules. SSI signals are designed for card synchronization only, not external devices.
SSI Interface PCIe-9529 SSI Bus[0] SSI_TIMEBASE SSI Bus[5] SSI_AD_TRIG Timing Control SSI Bus[0:7] SSI Bus[1] SSI_AD_TRIG SSI_SYNC_START SSI_SYNC_START Figure 3-10: SSI Architecture Different signals cannot be routed onto the same trigger bus line. NOTE: The three internal timing signals can be routed to the SSI bus through software drivers.
nizing all on-chip ADCs in both SSI Master and SSI Slave modules. 3.6.3 SSI_AD_TRIG As output, the SSI_AD_TRIG signal reflects the trigger event signal in an acquisition sequence. As input, the PCIe-9529 accepts the SSI_AD_TRIG signal as the trigger event source. The signal is configured in the rising edge-detection mode, with minimum pulse width 20ns.
PCIe-9529 Appendix A Calibration This chapter introduces the calibration process to minimize analog input measurement errors. A.1 Calibration Constant The PCIe-9529 is factory calibrated before shipment, with associated calibration constants written to the onboard EEPROM. At system boot, the PCIe-9529 driver loads these calibration constants, such that analog input path errors are minimized. ADLINK provides a software API for calibrating the PCIe-9529.
Before initializing auto-calibration, it is recommended to warm up the PCIe-9529 for at least 20 minutes and remove connected cables. NOTE: 32 It is not necessary to manually factor delay into applications, as the PCIe-9529 driver automatically adds the compensation time.
PCIe-9529 Important Safety Instructions For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment. X X X X X Read these safety instructions carefully. Keep this user’s manual for future reference. Read the specifications section of this manual for detailed information on the operating environment of this equipment.
X X Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel. A Lithium-type battery may be provided for uninterrupted, backup or emergency power. Risk of explosion if battery is replaced with an incorrect type; please dispose of used batteries appropriately.
PCIe-9529 Getting Service Contact us should you require any service or assistance. ADLINK Technology, Inc. Address: 9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan ᄅؑקխࡉ৬ԫሁ 166 ᇆ 9 ᑔ Tel: +886-2-8226-5877 Fax: +886-2-8226-5717 Email: service@adlinktech.com Ampro ADLINK Technology, Inc. Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com ADLINK Technology (China) Co.
ADLINK Technology, Inc. (French Liaison Office) Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com ADLINK Technology Japan Corporation Address: ͱ101-0045 ᵅҀ䛑गҷ⬄ऎ⼲⬄䤯 ⬎ފ3-7-4 ⼲⬄ 374 ɛɳ 4F KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho, Chiyoda-ku, Tokyo 101-0045, Japan Tel: +81-3-4455-3722 Fax: +81-3-5209-6013 Email: japan@adlinktech.com ADLINK Technology, Inc.
