PCIe-9852 2-CH 14-Bit 200 MS/s digitizer User’s Manual Manual Rev.: 2.00 Revision Date: May 20, 2013 Part No: 50-11041-1000 Advance Technologies; Automate the World.
Revision History Revision Release Date 2.
PCIe-9852 Preface Copyright 2013 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
Additional information, aids, and tips that help users perform tasks. NOTE: CAUTION: Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task. Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.
PCIe-9852 Table of Contents Preface .................................................................................... iii List of Figures ....................................................................... vii List of Tables.......................................................................... ix 1 Introduction ........................................................................ 1 1.1 1.2 1.3 Features...............................................................................
3.3.2 External Digital Trigger ............................................. 17 3.3.3 Analog Trigger .......................................................... 18 3.3.4 Trigger Export ........................................................... 18 3.4 Trigger Modes.................................................................... 18 3.4.1 Post Trigger Mode .................................................... 18 3.4.2 Delayed Trigger Mode .............................................. 18 3.4.
PCIe-9852 List of Figures Figure 1-1: Figure 1-2: Figure 1-3: Figure 1-4: Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 3-5: Figure 3-6: Figure 3-7: Figure 3-8: Figure 3-9: Figure 3-10: Figure 3-11: Figure 3-12: Figure 3-13: Figure 3-14: List of Figures Analog Input Channel Bandwidth, ±0.2 Vpp............... 3 Analog Input Channel Bandwidth, ±2 Vpp.................. 4 PCIe-9852 Schematic................................................. 8 PCIe-9852 I/O Array ......................................
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PCIe-9852 List of Tables Table Table Table Table Table Table Table Table Table Table Table Table 1-1: 1-2: 1-3: 1-4: 1-5: 1-6: 3-1: 3-2: 3-3: 3-4: 3-5: 3-6: List of Tables Channel Characteristics................................................... 3 Timebase ......................................................................... 5 Trigger Source & Mode.................................................... 5 Digital Trigger Input .........................................................
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PCIe-9852 1 Introduction The PCIe-9852 is a high-speed 2-CH 14-Bit 200 MS/s digitizer, specifically designed for applications such as LIDAR testing, optical fiber testing and radar signal acquisition. Analog input with 90 MHz bandwidth receives ±10V high speed signals with 50Ω impedance, and a simplified front-end design and highly stable onboard reference provide both highly accurate measurement results and high dynamic performance.
1.2 Applications X X X X Distributed Temperature Sensing (DTS) Video IC testing Physics laboratory and research environments Cable fault location and partial discharge monitoring for power applications 1.3 Specifications 1.3.1 Analog Input Channel Characteristics Channels 2 single-ended Connector type SMA Input coupling AC or DC, software selectable Comment AC coupling cutoff 11Hz frequency ADC resolution 14-Bit Inout signal range ±0.
PCIe-9852 Channel Characteristics THD SFDR Crosstalk Comment -73dBc 1MΩ, ±0.2 V -69dBc 1MΩ, ±2 V -73dBc 50Ω, ±0.2 V -69dBc 50Ω, ±2 V -72dBc 1MΩ, ±0.2 V -72dBc 1MΩ, ±2 V -68dBc 50Ω, ±0.2 V -68dBc 50Ω, ±2 V -80dBc ±0.2 V, ±2 V Table 1-1: Channel Characteristics Bandwidth 0 −1 −2 Magnitude (dB) −3 −4 −5 −6 −7 −8 −9 0.1M 0.3M 1M 3M 10M Frequency (Hz) 30M 100M 300M Figure 1-1: Analog Input Channel Bandwidth, ±0.
Bandwidth 0 −1 −2 Magnitude (dB) −3 −4 −5 −6 −7 −8 −9 0.1M 0.3M 1M 3M 10M Frequency (Hz) 30M 100M 300M Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp 1.3.2 Timebase Sample Clock Comment Internal : on board synthesizer Timebase options Sampling clock frequency 4 External : CLK IN (front panel), SSI Internal : 200MHz 3.
PCIe-9852 Sample Clock Comment External reference clock 10MHz External reference clock input range 500mVpp ~ 5Vpp AC / DC compliant External sampling clock input range 1Vpp ~ 5Vpp AC / DC compliant Table 1-2: Timebase 1.3.
Digital Trigger Output Trigger polarity Positive or negative Pulse width 50 ns, 100 ns, 150 ns, 200 ns, 500 ns, 1 μs, 2 μs, 7.5 μs, and 10 μs Trigger output driving capacity Capable of driving 50Ω load Table 1-5: Digital Trigger Output 1.3.4 General Specifications Specifications Physical dimensions 167.64 W x 106.68 H mm (6.53 x 4.
PCIe-9852 tems, ADLINK also provides drivers for other application environments such as LabVIEW®. All software options are included in the ADLINK All-in-One CD. Commercial software drivers are protected with licensing codes. Without the code, you may install and run the demo version for trial/demonstration purposes for only up to two hours. Contact your ADLINK dealer to purchase the software license. 1.4.
1.5 Device Layout and I/O Array All dimensions are in mm NOTE: 174.52 111.15 100.36 59.05 176.42 Figure 1-3: PCIe-9852 Schematic The PCIe-9852 I/O array is labeled to indicate connectivity, as shown.
PCIe-9852 Figure 1-4: PCIe-9852 I/O Array Name Faceplate Type Legend Remark CH0 N/A Blue On indicates CH0 acquisition ongoing Off indicates CH0 acquisition stopped CH1 N/A Blue On indicates CH1 acquisition ongoing Off indicates CH1 acquisition stopped Introduction 9
Name Faceplate Type Legend Remark Ext. Clock Input CLK IN Input for external reference clock or sample clock to digitizer Ext.
PCIe-9852 2 Getting Started This chapter describes proper installation environment, installation procedures, package contents and basic information users should be aware of regarding the PCIe-9852. Diagrams and illustrated equipment are for reference only. Actual system configuration and specifications may vary. NOTE: 2.1 Installation Environment When unpacking and preparing to install, please refer to Important Safety Instructions.
Inspect the carton and packaging for damage. Shipping and handling could cause damage to the equipment inside. Make sure that the equipment and its associated components have no damage before installation. CAUTION: The equipment must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the equipment and wear a grounded wrist strap when servicing.
PXIe-9852 3 Operations This chapter contains information regarding analog input, triggering and timing for the PCIe-9852. 3.1 Functional Block Diagram AUX DIO Port Calibration CKT FPGA CH0 Analog Front End 14 bit ADC ADC Interface FIFO Trigger Interface Local Bus Interface CH1 B to B High Speed Interface CLK IN PCI Express BUS Synthesizer PCI Express Controller TRG IN buffer TRG OUT buffer Daughter Board Carrier Board 3.2 Analog Input Channel 3.2.
3.2.2 Input Range and Data Format Data format of the PCIe-9852 is 2’s complement. The ADC data of PCIe-9852 is on the 14 MSB of the 16-bit A/D data. The 2 LSB of the 16-bit A/D data should be truncated by software. A/D data structure is as follows. D15 D14 D13 D12 …. D3 D2 D1 D0 D15 ~ D2 bits represent the data from ADC (2’s complement) D1, D0 bits are always 0.
PXIe-9852 To provide efficient data transfer, a PCI bus-mastering DMA is essential for continuous data streaming, as it helps to achieve full potential PCI Express bus bandwidth. The bus-mastering controller releases the burden on the host CPU since data is directly transferred to the host memory without intervention. Once analog input operation begins, the DMA returns control of the program.
First PCI Address PCI Address PCI Address First Dual Address Dual Address Dual Address Transfer Size Transfer Size Next Descriptor Next Descriptor Transfer Size Next Descriptor PCI Express Bus Local Memory ( FIFO) Figure 3-2: Linked List of PCI Address DMA Descriptors 3.3 Trigger Source and Trigger Modes This section details PCIe-9852 triggering operations.
PXIe-9852 The PCIe-9852 requires a trigger to implement acquisition of data. Configuration of triggers requires identification of trigger source. The PCIe-9852 supports internal software trigger, external digital trigger, and analog trigger. 3.3.1 Software Trigger The software trigger, generated by software command, is asserted immediately following execution of specified function calls to begin the operation. 3.3.
3.3.3 Analog Trigger An analog trigger is generated when AI input signal level is detected at the SMA connector CH0, CH1 (selected by software). The trigger level is also selected by software. 3.3.4 Trigger Export When acquisition is initiated, a pulse synchronized with the Timebase clock asserts and is output through trigger output, at a pulse width programmable from 50ns to 10μs via software. 3.
PXIe-9852 ger event, a time delay is implemented before commencing acquisition. The delay is specified by a 16-bit counter value such that a maximum thereof is the period of TIMEBASE X (216), and the minimum is the Timebase period. Figure 3-6: Delayed Trigger Mode Acquisition 3.4.3 Pre-Trigger Mode Collects data before the trigger event, starting once specified function calls are executed to begin the pre-trigger operation, and stopping when the trigger event occurs.
3.4.4 Middle Trigger Mode Collects data before and after the trigger event, with the amount to be collected set individually (M and N samples), as follows Operation start Acquisition start Acquisition stop Data transfer to system begins Trigger event occurs Time Trigger Data M samples N samples Figure 3-8: Middle Trigger Mode Acquisition 3.4.5 Acquisition with Re-Triggering A digitizer acquires a trace of N samples/channel for a single acquisition.
PXIe-9852 Figure 3-9: Re-Trigger Mode Acquisition 3.4.6 Data Average Mode (Post-Trigger and DelayedTrigger only) In normal post-trigger mode acquisition, N samples/channel data are generated for a single trigger event. In Re-trigger mode (See “Acquisition with Re-Triggering” on page 20.), a total of N * R samples/channel data is generated for R trigger events, that is, R traces (A trace contains N samples/channel). In Data Average Mode, only N samples/channel data are generated for R trigger events.
3.5.2 External Reference Clock The PCIe-9852 can choose an external clock source for use as a reference clock. When an external clock reference is selected, the synthesizer input will switch to the clock source at SMA connector CLK IN, and generate precisely 200MHz clock for ADC. The frequency of clock source is restricted to 10MHz. 3.5.3 External Sampling Clock The PCIe-9852 can further choose an external clock source as ADC sampling clock.
PXIe-9852 from an onboard synthesizer. To achieve different sampling rates, a scan interval counter is used. Using the post-trigger mode as an example, as shown, when a trigger is accepted by the digitizer, the acquisition engine commences acquisition of data from ADC, and stores the sampled data to the onboard FIFO. When FIFO is not empty, data will be transferred to system memory immediately through the DMA engine.
in width, therefore the lowest sampling rate is 3.051KS/s (200MS/s / 65535).
PXIe-9852 Counter Name Length Valid Value ReTrgCnt 31-bit 1-2147483647 Enables re-trigger to accept multiple triggers. X 1 - 2147483647 for normal operation X 1 - 65535 for Data Average mode Description See Acquisition with ReTriggering Table 3-4: Counter Parameters and Description 3.7 Synchronizing Multiple Modules The PCIe-9852 provides a dedicated connector as system synchronization interface, enabling multiple module synchronization.
ACLeSSI-3/ACL-eSSI-4 cables can be used to synchronize 2, 3, or 4 modules. Signal Direction Descr. Pin SSI Clock Input/Output Timebase signal through SSI 1 SSI Trig Input/Output Trigger signal through SSI 11 SSI_pre_data_rdy Input/Output Trigger signal through SSI 3, 5, 13, 15, NC No Connection 7 GND Ground 2, 4, 6, 8, 10, 12, 14, 16 Reserved Input/Output Reserved for future use 9 Table 3-5: SSI Signal Location and Pin Definition 3.7.
PXIe-9852 72 3 SW1 2 ON DIP 1 4 Figure 3-14: Card Number Configuration Switch When all sliders are in ON position, card number is 0, when all are OFF, card number is 15, as shown.
Slider 1 Slider 2 Slider 3 Slider 4 Card # OFF ON OFF ON 10 OFF ON OFF OFF 11 OFF OFF ON ON 12 OFF OFF ON OFF 13 OFF OFF OFF ON 14 OFF OFF OFF OFF 15 Table 3-6: Card Number Configuration Settings Default card number is 0. 3.7.2 SSI Timebase As an output, the SSI_TIMEBASE signal outputs the onboard 10MHz through ACL-eSSI-2/ACLeSSI-3/ACL-eSSI-4 cables. As an input, the PCIe-9852 accepts the SSI_TIMEBASE signal to be the source of timebase. 3.7.
PCIe-9852 Appendix A Calibration This chapter introduces the calibration process to minimize analog input measurement errors. A.1 Calibration Constant The PCIe-9852 is factory calibrated before shipment, with associated calibration constants written to the onboard EEPROM. At system boot, the PCIe-9852 driver loads these calibration constants, such that analog input path errors are minimized. ADLINK provides a software API for calibrating the PCIe-9852.
Before initializing auto-calibration, it is recommended to warm up the PCIe-9852 for at least 20 minutes and remove connected cables. NOTE: 30 It is not necessary to manually factor delay into applications, as the PCIe-9852 driver automatically adds the compensation time.
PCIe-9852 Important Safety Instructions For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment. X X X X X Read these safety instructions carefully. Keep this user’s manual for future reference. Read the specifications section of this manual for detailed information on the operating environment of this equipment.
X X Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel. A Lithium-type battery may be provided for uninterrupted, backup or emergency power. Risk of explosion if battery is replaced with an incorrect type; please dispose of used batteries appropriately.
PCIe-9852 Getting Service Contact us should you require any service or assistance. ADLINK Technology, Inc. Address: 9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan ᄅؑקխࡉ৬ԫሁ 166 ᇆ 9 ᑔ Tel: +886-2-8226-5877 Fax: +886-2-8226-5717 Email: service@adlinktech.com Ampro ADLINK Technology, Inc. Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com ADLINK Technology (China) Co.
ADLINK Technology, Inc. (French Liaison Office) Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com ADLINK Technology Japan Corporation Address: ͱ101-0045 ᵅҀ䛑गҷ⬄ऎ⼲⬄䤯 ⬎ފ3-7-4 ⼲⬄ 374 ɛɳ 4F KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho, Chiyoda-ku, Tokyo 101-0045, Japan Tel: +81-3-4455-3722 Fax: +81-3-5209-6013 Email: japan@adlinktech.com ADLINK Technology, Inc.
